74AVC32T245EC [NEXPERIA]

32-bit dual supply translating transceiver with configurable voltage translation 3-state;
74AVC32T245EC
型号: 74AVC32T245EC
厂家: Nexperia    Nexperia
描述:

32-bit dual supply translating transceiver with configurable voltage translation 3-state

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中文:  中文翻译
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74AVC32T245  
32-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 1 — 16 January 2013  
Product data sheet  
1. General description  
The 74AVC32T245 is a 32-bit transceiver with bidirectional level voltage translation and  
3-state outputs. The device can be used as eight 8-bit input-output ports (nAn and nBn),  
two 16-bit transceiver or as a 32-bit transceiver. It has dual supplies (VCC(A) and VCC(B)  
)
for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own  
output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B)  
can be independently supplied at any voltage between 0.8 V and 3.6 V making the device  
suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V,  
1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while  
a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the  
outputs to assume a high-impedance OFF-state  
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both nAn and nBn are in the high-impedance OFF-state.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101D exceeds 1000 V  
Maximum data rates:  
380 Mbit/s (1.8 V to 3.3 V translation)  
200 Mbit/s (1.1 V to 3.3 V translation)  
200 Mbit/s (1.1 V to 2.5 V translation)  
200 Mbit/s (1.1 V to 1.8 V translation)  
150 Mbit/s (1.1 V to 1.5 V translation)  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
100 Mbit/s (1.1 V to 1.2 V translation)  
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74AVC32T245EC  
40 C to +125 C  
LFBGA96  
plastic low profile fine-pitch ball grid array  
SOT536-1  
package; 96 balls; body 13.5 5.5 1.05 mm  
4. Functional diagram  
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ꢏꢐꢑꢐꢏꢒꢓꢔꢑꢕꢓꢖꢓꢗꢑꢘꢒꢙꢗꢗꢓꢚꢕ  
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ꢀꢀꢀꢁꢂꢂꢃꢄꢄꢅ  
Fig 1. Logic diagram  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
2 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
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ꢀꢀꢀꢁꢂꢂꢃꢄꢄꢄ  
Fig 2. Logic symbol  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
3 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
5. Pinning information  
5.1 Pinning  
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)ꢔꢙꢗꢕ+ꢙꢔꢓꢗꢏꢑꢏꢐ+ꢑꢖ,ꢓ-  
Fig 3. Pin configuration SOT536-1 (LFBGA96)  
5.2 Pin description  
Table 2.  
Symbol  
Pin description  
Ball  
Description  
1DIR, 2DIR, 3DIR, 4DIR  
1OE, 2OE, 3OE, 4OE  
1A1 to 1A8  
A3, H3, J3, T3  
A4, H4, J4, T4  
direction control  
output enable input (active LOW)  
A5, A6, B5, B6, C5, C6, D5, D6 input or output  
A2, A1, B2, B1, C2, C1, D2, D1 input or output  
E5, E6, F5, F6, G5, G6, H6, H5 input or output  
E2, E1, F2, F1, G2, G1, H1, H2 input or output  
J5, J6, K5, K6, L5, L6, M5, M6 input or output  
J2, J1, K2, K1, L2, L1, M2, M1 input or output  
N5, N6, P5, P6, R5, R6, T6, T5 input or output  
N2, N1, P2, P1, R2, R1, T1, T2 input or output  
1B1 to 1B8  
2A1 to 2A8  
2B1 to 2B8  
3A1 to 3A8  
3B1 to 3B8  
4A1 to 4A8  
4B1 to 4B8  
GND[1]  
B3, B4, D3, D4, E3, E4, G3, G4, ground (0 V)  
K3, K4, M3, M4, N3, N4, R3, R4  
VCC(A)  
VCC(B)  
C4, F4, L4, P4  
supply voltage A (nAn, nOE and nDIR inputs are referenced  
to VCC(A)  
)
C3, F3, L3, P3  
supply voltage B (nBn inputs are referenced to VCC(B)  
)
[1] All GND pins must be connected to ground (0 V).  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
4 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
6. Functional description  
Table 3.  
Function table[1]  
Supply voltage  
VCC(A), VCC(B)  
0.8 V to 3.6 V  
0.8 V to 3.6 V  
0.8 V to 3.6 V  
GND[3]  
Input  
nOE[2]  
Input/output[3]  
nAn[2]  
nDIR[2]  
nBn[2]  
L
L
nAn = nBn  
input  
L
H
X
X
input  
Z
nBn = nAn  
H
X
Z
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
[2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B)  
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.  
.
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC(A)  
VCC(B)  
IIK  
Parameter  
Conditions  
Min  
0.5  
0.5  
50  
0.5  
50  
0.5  
0.5  
-
Max  
Unit  
V
supply voltage A  
supply voltage B  
input clamping current  
input voltage  
+4.6  
+4.6  
V
VI < 0 V  
-
mA  
V
[1]  
VI  
+4.6  
IOK  
output clamping current  
output voltage  
VO < 0 V  
-
mA  
V
[1][2][3]  
[1]  
VO  
Active mode  
VCCO + 0.5  
+4.6  
50  
Suspend or 3-state mode  
VO = 0 V to VCCO  
per VCC(A) or VCC(B) pin  
per GND pin  
V
[2]  
IO  
output current  
mA  
mA  
mA  
C  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
100  
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
Tamb = 40 C to +125 C  
[4]  
LFBGA96 package  
-
1000  
mW  
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] VCCO is the supply voltage associated with the output port.  
[3] VCCO + 0.5 V should not exceed 4.6 V.  
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
5 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC(A)  
VCC(B)  
VI  
Recommended operating conditions  
Parameter  
Conditions  
Min  
0.8  
0.8  
0
Max  
3.6  
Unit  
V
supply voltage A  
supply voltage B  
input voltage  
3.6  
V
3.6  
V
[1]  
[2]  
VO  
output voltage  
Active mode  
0
VCCO  
3.6  
V
Suspend or 3-state mode  
0
V
Tamb  
ambient temperature  
40  
-
+125  
5
C  
ns/V  
t/V  
input transition rise and fall rate  
VCCI = 0.8 V to 3.6 V  
[1] VCCO is the supply voltage associated with the output port.  
[2] VCCI is the supply voltage associated with the input port.  
9. Static characteristics  
Table 6.  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Typical static characteristics at Tamb = 25 C[1][2]  
Symbol Parameter Conditions  
VOH HIGH-level output voltage VI = VIH or VIL  
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V  
LOW-level output voltage VI = VIH or VIL  
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V  
Min  
Typ  
0.69  
0.07  
Max  
Unit  
-
-
-
V
V
VOL  
-
-
II  
input leakage current  
nDIR, nOE input; VI = 0 V or 3.6 V;  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
0.025 0.25 A  
[3]  
[3]  
[3]  
IOZ  
OFF-state output current  
A or B port; VO = 0 V or VCCO  
VCC(A) = VCC(B) = 3.6 V  
;
-
-
-
-
-
-
-
0.5  
0.5  
0.5  
0.1  
0.1  
2.0  
2.5  
2.5  
2.5  
1  
A  
A  
A  
A  
A  
pF  
pF  
suspend mode A port; VO = 0 V or VCCO  
VCC(A) = 3.6 V; VCC(B) = 0 V  
;
;
suspend mode B port; VO = 0 V or VCCO  
VCC(A) = 0 V; VCC(B) = 3.6 V  
IOFF  
power-off leakage current A port; VI or VO = 0 V to 3.6 V;  
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V  
B port; VI or VO = 0 V to 3.6 V;  
1  
V
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V  
CI  
input capacitance  
nDIR, nOE input; VI = 0 V or 3.3 V;  
VCC(A) = VCC(B) = 3.3 V  
-
CI/O  
input/output capacitance  
A and B port; VO = 3.3 V or 0 V;  
VCC(A) = VCC(B) = 3.3 V  
4.5  
-
[1] VCCO is the supply voltage associated with the output port.  
[2] VCCI is the supply voltage associated with the data input port.  
[3] For I/O ports, the parameter IOZ includes the input leakage current.  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
6 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
Table 7.  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Static characteristics [1][2]  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C  
Unit  
Min  
Max  
Min  
Max  
VIH  
HIGH-level  
data input  
input voltage  
VCCI = 0.8 V  
0.70VCCI  
0.65VCCI  
1.6  
-
-
-
-
0.70VCCI  
0.65VCCI  
1.6  
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V  
VCCI = 2.3 V to 2.7 V  
VCCI = 3.0 V to 3.6 V  
nDIR, nOE input  
2
2
VCC(A) = 0.8 V  
0.70VCC(A)  
-
-
-
-
0.70VCC(A)  
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V  
VCC(A) = 2.3 V to 2.7 V  
VCC(A) = 3.0 V to 3.6 V  
data input  
0.65VCC(A)  
0.65VCC(A)  
1.6  
2
1.6  
2
VIL  
LOW-level  
input voltage  
VCCI = 0.8 V  
-
-
-
-
0.30VCCI  
0.35VCCI  
0.7  
-
-
-
-
0.30VCCI  
0.35VCCI  
0.7  
V
V
V
V
VCCI = 1.1 V to 1.95 V  
VCCI = 2.3 V to 2.7 V  
VCCI = 3.0 V to 3.6 V  
nDIR, nOE input  
0.8  
0.8  
VCC(A) = 0.8 V  
-
-
-
-
0.30VCC(A)  
0.35VCC(A)  
0.7  
-
-
-
-
0.30VCC(A)  
0.35VCC(A)  
0.7  
V
V
V
V
VCC(A) = 1.1 V to 1.95 V  
VCC(A) = 2.3 V to 2.7 V  
VCC(A) = 3.0 V to 3.6 V  
VI = VIH or VIL  
0.8  
0.8  
VOH  
HIGH-level  
output voltage  
IO = 100 A;  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
VCCO 0.1  
0.85  
-
-
-
-
-
-
VCCO 0.1  
0.85  
-
-
-
-
-
-
V
V
V
V
V
V
IO = 3 mA;  
VCC(A) = VCC(B) = 1.1 V  
IO = 6 mA;  
1.05  
1.05  
VCC(A) = VCC(B) = 1.4 V  
IO = 8 mA;  
VCC(A) = VCC(B) = 1.65 V  
1.2  
1.2  
IO = 9 mA;  
VCC(A) = VCC(B) = 2.3 V  
1.75  
1.75  
IO = 12 mA;  
2.3  
2.3  
VCC(A) = VCC(B) = 3.0 V  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
7 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
[1][2]  
Table 7.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C  
Unit  
Min  
Max  
Min  
Max  
VOL  
LOW-level  
VI = VIH or VIL  
output voltage  
IO = 100 A;  
-
0.1  
-
0.1  
V
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V  
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V  
IO = 8 mA;  
-
-
-
0.25  
0.35  
0.45  
-
-
-
0.25  
0.35  
0.45  
V
V
V
VCC(A) = VCC(B) = 1.65 V  
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V  
-
-
0.55  
0.7  
-
-
0.55  
0.7  
V
V
IO = 12 mA;  
VCC(A) = VCC(B) = 3.0 V  
II  
input leakage nDIR, nOE input; VI = 0 V or 3.6 V;  
-
-
-
1  
5  
5  
-
-
-
5  
A  
A  
A  
current  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
[3]  
[3]  
IOZ  
OFF-state  
A or B port; VO = 0 V or VCCO  
;
30  
30  
output current VCC(A) = VCC(B) = 3.6 V  
suspend mode A port;  
VO = 0 V or VCCO; VCC(A) = 3.6 V;  
VCC(B) = 0 V  
[3]  
suspend mode B port;  
VO = 0 V or VCCO; VCC(A) = 0 V;  
VCC(B) = 3.6 V  
-
5  
-
30  
A  
IOFF  
power-off  
leakage  
current  
A port; VI or VO = 0 V to 3.6 V;  
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V  
-
-
5  
5  
-
-
30  
30  
A  
A  
B port; VI or VO = 0 V to 3.6 V;  
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
8 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
[1][2]  
Table 7.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter Conditions 40 C to +85 C  
40 C to +125 C  
Unit  
Min  
Max  
Min  
Max  
ICC  
supply current A port; VI = 0 V or VCCI; IO = 0 A  
VCC(A) = 0.8 V to 3.6 V;  
VCC(B) = 0.8 V to 3.6 V  
-
-
60  
50  
-
-
250  
200  
A  
A  
VCC(A) = 1.1 V to 3.6 V;  
VCC(B) = 1.1 V to 3.6 V  
VCC(A) = 3.6 V; VCC(B) = 0 V  
VCC(A) = 0 V; VCC(B) = 3.6 V  
B port; VI = 0 V or VCCI; IO = 0 A  
-
50  
-
-
200  
-
A  
A  
10  
40  
VCC(A) = 0.8 V to 3.6 V;  
VCC(B) = 0.8 V to 3.6 V  
-
-
60  
50  
-
-
250  
200  
A  
A  
VCC(A) = 1.1 V to 3.6 V;  
VCC(B) = 1.1 V to 3.6 V  
VCC(A) = 3.6 V; VCC(B) = 0 V  
VCC(A) = 0 V; VCC(B) = 3.6 V  
A plus B port (ICC(A) + ICC(B));  
10  
-
40  
-
A  
A  
A  
-
-
50  
-
-
200  
370  
110  
IO = 0 A; VI = 0 V or VCCI  
VCC(A) = 0.8 V to 3.6 V;  
VCC(B) = 0.8 V to 3.6 V  
;
A plus B port (ICC(A) + ICC(B));  
-
90  
-
300  
A  
IO = 0 A; VI = 0 V or VCCI  
VCC(A) = 1.1 V to 3.6 V;  
VCC(B) = 1.1 V to 3.6 V  
;
[1] VCCO is the supply voltage associated with the output port.  
[2] VCCI is the supply voltage associated with the data input port.  
[3] For I/O ports, the parameter IOZ includes the input leakage current.  
Table 8.  
VCC(A)  
Typical total supply current (ICC(A) + ICC(B)  
VCC(B)  
)
Unit  
0 V  
0
0.8 V  
0.2  
0.2  
0.2  
0.2  
0.2  
0.6  
3.2  
1.2 V  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
1.6  
1.5 V  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.8  
1.8 V  
2.5 V  
0.2  
0.6  
0.2  
0.2  
0.2  
0.2  
0.2  
3.3 V  
0.2  
3.2  
1.6  
0.8  
0.4  
0.2  
0.2  
0 V  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.4  
A  
A  
A  
A  
A  
A  
A  
0.8 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
9 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
10. Dynamic characteristics  
Table 9.  
Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
VCC(A) = VCC(B)  
Unit  
0.8 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
CPD  
power dissipation A port: (direction nAn to  
0.2  
0.2  
0.2  
0.2  
0.3  
0.4  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
capacitance  
nBn); output enabled  
A port: (direction nAn to  
nBn); output disabled  
0.2  
9
0.2  
9.7  
0.6  
9.7  
0.6  
0.2  
0.2  
0.2  
9.8  
0.6  
9.8  
0.6  
0.2  
0.2  
0.2  
10.3  
0.7  
0.3  
11.7  
0.7  
0.4  
13.7  
0.7  
A port: (direction nBn to  
nAn); output enabled  
A port: (direction nBn to  
nAn); output disabled  
0.6  
9
B port: (direction nAn to  
nBn); output enabled  
10.3  
0.7  
11.7  
0.7  
13.7  
0.7  
B port: (direction nAn to  
nBn); output disabled  
0.6  
0.2  
0.2  
B port: (direction nBn to  
nAn); output enabled  
0.2  
0.3  
0.4  
B port: (direction nBn to  
nAn); output disabled  
0.2  
0.3  
0.4  
[1] CPD is used to determine the dynamic power dissipation (PD in W).  
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
(CL VCC2 fo) = sum of the outputs.  
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL =  .  
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
10 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5  
Symbol Parameter  
Conditions  
VCC(B)  
1.5 V  
Unit  
0.8 V  
14.4  
14.4  
16.2  
17.6  
21.9  
22.2  
1.2 V  
7.0  
1.8 V  
6.0  
2.5 V  
5.9  
3.3 V  
6.0  
tpd  
tdis  
ten  
propagation delay nAn to nBn  
nBn to nAn  
6.2  
12.1  
16.2  
9.0  
ns  
ns  
ns  
ns  
ns  
ns  
12.4  
16.2  
10.0  
21.9  
11.1  
11.9  
16.2  
9.1  
11.8  
16.2  
8.7  
11.8  
16.2  
9.3  
disable time  
nOE to nAn  
nOE to nBn  
nOE to nAn  
nOE to nBn  
enable time  
21.9  
9.8  
21.9  
9.4  
21.9  
9.4  
21.9  
9.6  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5  
Symbol Parameter Conditions VCC(A)  
1.5 V  
Unit  
0.8 V  
14.4  
14.4  
16.2  
17.6  
21.9  
22.2  
1.2 V  
12.4  
7.0  
1.8 V  
11.9  
6.0  
2.5 V  
11.8  
5.9  
3.3 V  
11.8  
6.0  
tpd  
tdis  
ten  
propagation delay nAn to nBn  
nBn to nAn  
12.1  
6.2  
ns  
ns  
ns  
ns  
ns  
ns  
disable time  
nOE to nAn  
nOE to nBn  
nOE to nAn  
nOE to nBn  
5.9  
4.4  
4.2  
3.1  
3.5  
14.2  
6.4  
13.7  
4.4  
13.6  
3.5  
13.3  
2.6  
13.1  
2.3  
enable time  
17.7  
17.2  
17.0  
16.8  
16.7  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
11 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1]  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5.  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
VCC(A) = 1.1 V to 1.3 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
0.5  
0.5  
1.5  
1.5  
1.0  
1.1  
9.2  
9.2  
0.5  
0.5  
1.5  
1.5  
1.0  
1.1  
6.9  
8.7  
0.5  
0.5  
1.5  
1.5  
1.0  
1.1  
6.0  
8.5  
0.5  
0.5  
1.5  
1.0  
1.0  
1.0  
5.1  
8.2  
0.5  
0.5  
1.5  
1.0  
1.0  
1.0  
4.9 ns  
8.0 ns  
11.6 ns  
8.9 ns  
14.5 ns  
7.7 ns  
delay  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
11.6  
12.5  
14.5  
14.9  
11.6  
9.7  
11.6  
9.5  
11.6  
8.1  
enable time nOE to nAn  
nOE to nBn  
14.5  
11.0  
14.5  
9.6  
14.5  
8.1  
VCC(A) = 1.4 V to 1.6 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
8.7  
6.9  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
6.2  
6.2  
0.5  
0.5  
1.5  
1.5  
1.0  
0.5  
5.2  
5.9  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
4.1  
5.6  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
3.7 ns  
5.5 ns  
9.1 ns  
6.3 ns  
10.1 ns  
5.2 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
9.1  
9.1  
9.1  
7.5  
10.1  
8.1  
9.1  
11.4  
10.1  
13.5  
8.7  
6.5  
enable time nOE to nAn  
nOE to nBn  
10.1  
10.1  
10.1  
5.9  
VCC(A) = 1.65 V to 1.95 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
8.5  
6.0  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
5.9  
5.2  
7.7  
8.4  
7.8  
9.2  
0.5  
0.5  
1.5  
1.5  
1.0  
0.5  
4.8  
4.8  
7.7  
7.1  
7.8  
7.4  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
3.7  
4.5  
7.7  
5.9  
7.8  
5.3  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
3.3 ns  
4.4 ns  
7.7 ns  
5.7 ns  
7.8 ns  
4.5 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
7.7  
11.1  
7.8  
enable time nOE to nAn  
nOE to nBn  
13.0  
VCC(A) = 2.3 V to 2.7 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
8.2  
5.1  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
5.6  
4.1  
6.1  
7.9  
5.3  
9.4  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
4.6  
3.7  
6.1  
6.6  
5.3  
7.3  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
3.3  
3.4  
6.1  
6.1  
5.3  
5.1  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
2.8 ns  
3.2 ns  
6.1 ns  
5.2 ns  
5.3 ns  
4.5 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
6.1  
10.6  
5.3  
enable time nOE to nAn  
nOE to nBn  
12.5  
VCC(A) = 3.0 V to 3.6 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
8.0  
4.9  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
5.5  
3.7  
5.0  
7.7  
4.3  
9.3  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
4.4  
3.3  
5.0  
6.5  
4.2  
7.2  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
3.2  
2.9  
5.0  
5.2  
4.1  
4.9  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
2.7 ns  
2.7 ns  
5.0 ns  
5.0 ns  
4.0 ns  
4.0 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
5.0  
10.3  
4.3  
enable time nOE to nAn  
nOE to nBn  
12.4  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
74AVC32T245  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 1 — 16 January 2013  
12 of 24  
74AVC32T245  
Nexperia  
32-bit dual supply translating transceiver; 3-state  
Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
VCC(A) = 1.1 V to 1.3 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
0.5  
0.5  
1.5  
1.5  
1.0  
1.1  
10.2  
10.2  
12.8  
13.8  
16.0  
16.4  
0.5  
0.5  
1.5  
1.5  
1.0  
1.1  
7.6  
9.6  
0.5  
0.5  
1.5  
1.5  
1.0  
1.1  
6.6  
9.4  
0.5  
0.5  
1.5  
1.0  
1.0  
1.0  
5.7  
9.1  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
5.4 ns  
8.8 ns  
12.8 ns  
9.8 ns  
16.0 ns  
8.5 ns  
delay  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
12.8  
10.7  
16.0  
12.1  
12.8  
10.5  
16.0  
10.6  
12.8  
9.0  
enable time nOE to nAn  
nOE to nBn  
16.0  
9.0  
VCC(A) = 1.4 V to 1.6 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
9.6  
7.6  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
6.9  
6.9  
0.5  
0.5  
1.5  
1.5  
1.0  
0.5  
5.8  
6.5  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
4.6  
6.2  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
4.1 ns  
6.1 ns  
10.1 ns  
7.0 ns  
11.2 ns  
5.8 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
10.1  
12.6  
11.2  
14.9  
10.1  
9.6  
10.1  
8.3  
10.1  
7.2  
enable time nOE to nAn  
nOE to nBn  
11.2  
11.2  
11.2  
9.0  
11.2  
6.5  
VCC(A) = 1.65 V to 1.95 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
9.4  
6.6  
0.5  
0.5  
1.5  
1.5  
1.0  
1.0  
6.5  
5.8  
0.5  
0.5  
1.5  
1.5  
1.0  
0.5  
5.3  
5.3  
8.5  
7.9  
8.6  
8.2  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
4.1  
5.0  
8.5  
6.5  
8.6  
5.9  
0.5  
0.5  
1.5  
1.0  
1.0  
0.5  
3.7 ns  
4.9 ns  
8.5 ns  
6.3 ns  
8.6 ns  
5.0 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
8.5  
8.5  
9.3  
8.6  
10.2  
12.3  
8.6  
enable time nOE to nAn  
nOE to nBn  
14.3  
VCC(A) = 2.3 V to 2.7 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
9.1  
5.7  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
6.2  
4.6  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
5.1  
4.1  
6.8  
7.3  
5.9  
8.1  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
3.7  
3.8  
6.8  
6.8  
5.9  
5.7  
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
3.1 ns  
3.6 ns  
6.8 ns  
5.8 ns  
5.9 ns  
5.0 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
6.8  
6.8  
11.7  
5.9  
8.7  
5.9  
enable time nOE to nAn  
nOE to nBn  
13.8  
10.4  
VCC(A) = 3.0 V to 3.6 V  
tpd  
tdis  
ten  
propagation nAn to nBn  
delay  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
8.8  
5.4  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
6.1  
4.1  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
4.9  
3.7  
5.5  
7.2  
4.7  
8.0  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
3.6  
3.2  
5.5  
5.8  
4.6  
5.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
3.0 ns  
3.0 ns  
5.5 ns  
5.5 ns  
4.4 ns  
4.4 ns  
nBn to nAn  
disable time nOE to nAn  
nOE to nBn  
5.5  
5.5  
11.4  
4.8  
8.5  
4.8  
enable time nOE to nAn  
nOE to nBn  
13.7  
10.3  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
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Product data sheet  
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32-bit dual supply translating transceiver; 3-state  
11. Waveforms  
V
I
nAn, nBn input  
GND  
V
M
t
t
PLH  
PHL  
V
OH  
nBn, nAn output  
V
M
V
OL  
001aak285  
Measurement points are given in Table 14.  
OL and VOH are typical output voltage levels that occur with the output load.  
V
Fig 4. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times  
V
I
V
nOE input  
M
GND  
t
t
PLZ  
PZL  
V
CCO  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
OL  
t
t
PZH  
PHZ  
V
OH  
V
Y
output  
HIGH-to-OFF  
OFF-to-HIGH  
V
M
GND  
outputs  
enabled  
outputs  
disabled  
outputs  
enabled  
001aak286  
Measurement points are given in Table 14.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 5. Enable and disable times  
Table 14. Measurement points  
Supply voltage  
VCC(A), VCC(B)  
0.8 V to 1.6 V  
1.65 V to 2.7 V  
3.0 V to 3.6 V  
Input[1]  
Output[2]  
VM  
VM  
VX  
VY  
0.5VCCI  
0.5VCCI  
0.5VCCI  
0.5VCCO  
0.5VCCO  
0.5VCCO  
VOL + 0.1 V  
VOH 0.1 V  
VOH 0.15 V  
VOH 0.3 V  
VOL + 0.15 V  
VOL + 0.3 V  
[1] VCCI is the supply voltage associated with the data input port.  
[2] VCCO is the supply voltage associated with the output port.  
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32-bit dual supply translating transceiver; 3-state  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
EXT  
R
V
CC  
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
001aae331  
Test data is given in Table 15.  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance.  
VEXT = External voltage for measuring switching times.  
Fig 6. Test circuit for measuring switching times  
Table 15. Test data  
Supply voltage  
VCC(A), VCC(B)  
0.8 V to 1.6 V  
1.65 V to 2.7 V  
3.0 V to 3.6 V  
Input  
VI[1]  
Load  
CL  
VEXT  
[3]  
t/V[2]  
RL  
tPLH, tPHL  
open  
tPZH, tPHZ  
GND  
tPZL, tPLZ  
2VCCO  
VCCI  
VCCI  
VCCI  
1.0 ns/V  
1.0 ns/V  
1.0 ns/V  
15 pF  
15 pF  
15 pF  
2 k  
2 k  
2 k  
open  
GND  
2VCCO  
open  
GND  
2VCCO  
[1] VCCI is the supply voltage associated with the data input port.  
[2] dV/dt 1.0 V/ns  
[3]  
VCCO is the supply voltage associated with the output port.  
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Product data sheet  
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32-bit dual supply translating transceiver; 3-state  
12. Typical propagation delay characteristics  
001aai476  
001aai477  
24  
21  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
t
pd  
(ns)  
t
pd  
(1)  
(ns)  
20  
17  
16  
12  
8
13  
(2)  
(3)  
(4)  
(5)  
(6)  
4
9
0
20  
40  
60  
0
20  
40  
60  
C
L
(pF)  
C (pF)  
L
a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V  
(1) VCC(B) = 0.8 V.  
b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V  
(1)  
(2)  
V
V
CC(A) = 0.8 V.  
CC(A) = 1.2 V.  
(2)  
VCC(B) = 1.2 V.  
(3) VCC(B) = 1.5 V.  
(4) VCC(B) = 1.8 V.  
(3) VCC(A) = 1.5 V.  
(4) VCC(A) = 1.8 V.  
(5)  
V
CC(B) = 2.5 V.  
(5)  
VCC(A) = 2.5 V.  
(6) VCC(B) = 3.3 V.  
(6) VCC(A) = 3.3 V.  
Fig 7. Typical propagation delay versus load capacitance; Tamb = 25 C  
74AVC32T245  
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Product data sheet  
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32-bit dual supply translating transceiver; 3-state  
001aai478  
001aai491  
7
7
(1)  
t
t
PHL  
PLH  
(ns)  
(ns)  
(1)  
(2)  
(3)  
5
3
1
5
3
1
(2)  
(3)  
(4)  
(5)  
(4)  
(5)  
0
20  
40  
60  
0
20  
40  
60  
C
L
(pF)  
C
L
(pF)  
a. LOW to HIGH propagation delay (nAn to nBn);  
VCC(A) = 1.2 V  
b. HIGH to LOW propagation delay (nAn to nBn);  
VCC(A) = 1.2 V  
001aai479  
001aai480  
7
7
(1)  
t
t
PHL  
PLH  
(ns)  
(ns)  
(1)  
5
3
1
5
3
1
(2)  
(3)  
(2)  
(3)  
(4)  
(5)  
(4)  
(5)  
0
20  
40  
60  
0
20  
40  
60  
C
L
(pF)  
C
L
(pF)  
c. LOW to HIGH propagation delay (nAn to nBn);  
VCC(A) = 1.5 V  
d. HIGH to LOW propagation delay (nAn to nBn);  
CC(A) = 1.5 V  
V
(1) VCC(B) = 1.2 V.  
(2) VCC(B) = 1.5 V.  
(3) VCC(B) = 1.8 V.  
(4)  
VCC(B) = 2.5 V.  
(5) VCC(B) = 3.3 V.  
Fig 8. Typical propagation delay versus load capacitance; Tamb = 25 C  
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32-bit dual supply translating transceiver; 3-state  
001aai481  
001aai482  
7
7
(1)  
t
t
PHL  
PLH  
(ns)  
(ns)  
(1)  
5
3
1
5
3
1
(2)  
(3)  
(2)  
(3)  
(4)  
(5)  
(4)  
(5)  
0
20  
40  
60  
0
20  
40  
60  
C
L
(pF)  
C
L
(pF)  
a. LOW to HIGH propagation delay (nAn to nBn);  
VCC(A) = 1.8 V  
b. HIGH to LOW propagation delay (nAn to nBn);  
VCC(A) = 1.8 V  
001aai483  
001aai486  
7
7
t
t
PHL  
(ns)  
PLH  
(1)  
(ns)  
(1)  
5
3
1
5
3
1
(2)  
(3)  
(2)  
(3)  
(4)  
(5)  
(4)  
(5)  
0
20  
40  
60  
0
20  
40  
60  
C
L
(pF)  
C
L
(pF)  
c. LOW to HIGH propagation delay (nAn to nBn);  
VCC(A) = 2.5 V  
d. HIGH to LOW propagation delay (nAn to nBn);  
CC(A) = 2.5 V  
V
(1) VCC(B) = 1.2 V.  
(2) VCC(B) = 1.5 V.  
(3) VCC(B) = 1.8 V.  
(4)  
VCC(B) = 2.5 V.  
(5) VCC(B) = 3.3 V.  
Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C  
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32-bit dual supply translating transceiver; 3-state  
001aai485  
001aai484  
7
7
t
t
PHL  
(ns)  
PLH  
(1)  
(ns)  
(1)  
5
3
1
5
3
1
(2)  
(3)  
(2)  
(3)  
(4)  
(5)  
(4)  
(5)  
0
20  
40  
60  
0
20  
40  
60  
C
L
(pF)  
C
L
(pF)  
a. LOW to HIGH propagation delay (nAn to nBn);  
VCC(A) = 3.3 V  
b. HIGH to LOW propagation delay (nAn to nBn);  
VCC(A) = 3.3 V  
(1) VCC(B) = 1.2 V.  
(2) VCC(B) = 1.5 V.  
(3) VCC(B) = 1.8 V.  
(4)  
VCC(B) = 2.5 V.  
(5) VCC(B) = 3.3 V.  
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C  
74AVC32T245  
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32-bit dual supply translating transceiver; 3-state  
13. Package outline  
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1  
B
A
D
ball A1  
index area  
A
2
A
E
A
1
detail X  
e
1
C
1/2 e  
y
y
v M  
w M  
C
C
A B  
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e  
E
D
C
B
A
ball A1  
index area  
1
2
3
4
5
6
X
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
UNIT  
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.  
0.41  
0.31  
1.2  
0.9  
0.51  
0.41  
5.6  
5.4  
13.6  
13.4  
mm  
1.5  
4
12  
0.1  
0.2  
0.8  
0.15  
0.1  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
00-03-04  
03-02-05  
SOT536-1  
Fig 11. Package outline SOT536-1 (LFBGA96)  
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Product data sheet  
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32-bit dual supply translating transceiver; 3-state  
14. Abbreviations  
Table 16. Abbreviations  
Acronym  
CDM  
DUT  
Description  
Charged Device Model  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
ESD  
HBM  
MM  
15. Revision history  
Table 17. Revision history  
Document ID  
Release date  
20130116  
Data sheet status  
Change notice  
Supersedes  
74AVC32T245 v.1  
Product data sheet  
-
-
74AVC32T245  
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16. Legal information  
16.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nexperia.com.  
Suitability for use — Nexperia products are not designed,  
16.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of a Nexperia product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. Nexperia and its suppliers accept no liability for  
inclusion and/or use of Nexperia products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local Nexperia sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the Nexperia  
product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
Nexperia and its customer, unless Nexperia and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the Nexperia product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
Nexperia does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using Nexperia  
products in order to avoid a default of the applications and  
16.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, Nexperia does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. Nexperia takes no  
responsibility for the content in this document if provided by an information  
source outside of Nexperia.  
the products or of the application or use by customer’s third party  
customer(s). Nexperia does not accept any liability in this respect.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall Nexperia be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — Nexperia  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. Nexperia hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of Nexperia products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of Nexperia.  
Right to make changes — Nexperia reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
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Product data sheet  
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Nexperia  
32-bit dual supply translating transceiver; 3-state  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Nexperia’s specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies Nexperia for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond Nexperia’s  
standard warranty and Nexperia’s product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific Nexperia product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. Nexperia  
accepts no liability for inclusion and/or use of  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without Nexperia’s warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
16.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
17. Contact information  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
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Product data sheet  
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32-bit dual supply translating transceiver; 3-state  
18. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
6
Functional description . . . . . . . . . . . . . . . . . . . 5  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Recommended operating conditions. . . . . . . . 6  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6  
Dynamic characteristics . . . . . . . . . . . . . . . . . 10  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Typical propagation delay characteristics . . 16  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21  
7
8
9
10  
11  
12  
13  
14  
15  
16  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
16.1  
16.2  
16.3  
16.4  
17  
18  
Contact information. . . . . . . . . . . . . . . . . . . . . 23  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
© Nexperia B.V. 2017. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 16 January 2013  

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