74AVCH2T45DC-Q100 [NEXPERIA]
Dual-bit, dual-supply voltage level translator/transceiver; 3-stateProduction;
| 型号： | 74AVCH2T45DC-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Dual-bit, dual-supply voltage level translator/transceiver; 3-stateProduction |
| 文件： | 总18页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver;
3-state
Rev. 1 — 7 December 2022
Product data sheet
1. General description
The 74AVCH2T45-Q100 is a dual bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (nA and nB), a direction control input (DIR)
and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage
between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage
nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and
pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on
DIR allows transmission from nB to nA.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are
in the high-impedance OFF-state.
The 74AVCH2T45-Q100 has active bus hold circuitry which is provided to hold unused or floating
data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down
resistors.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
Wide supply voltage range: 0.8 V to 3.6 V for VCC(A) and VCC(B)
High noise immunity
Suspend mode
Bus hold on data inputs
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Maximum data rates:
•
•
•
•
•
500 Mbps (1.8 V to 3.3 V translation)
320 Mbps (< 1.8 V to 3.3 V translation)
320 Mbps (translate to 2.5 V or 1.8 V)
280 Mbps (translate to 1.5 V)
240 Mbps (translate to 1.2 V)
•
•
Latch-up performance exceeds 100 mA per JESD 78 Class II
Complies with JEDEC standards:
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
•
ESD protection:
•
•
HBM: ANSI/ESDA/Jedec JS-001 Class 3B exceeds 8000 V
CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVCH2T45DC-Q100 -40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
4. Marking
Table 2. Marking
Type number
Marking code [1]
74AVCH2T45DC-Q100
K45
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
5
DIR
DIR
2
1A
1A
7
1B
1B
2B
3
2A
2A
6
2B
V
V
CC(B)
CC(A)
V
V
CC(B)
CC(A)
001aag577
001aag578
Fig. 1. Logic symbol
Fig. 2. Logic diagram
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
2 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
6. Pinning information
6.1. Pinning
DC package
SOT765-1 (VSSOP8)
1
2
3
4
8
7
6
5
V
V
CC(B)
CC(A)
1A
1B
2A
2B
GND
DIR
aaa-035796
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
VCC(A)
1A
supply voltage port A and DIR
data input or output
data input or output
ground (0 V)
2
2A
3
GND
DIR
2B
4
5
direction control
6
data input or output
data input or output
supply voltage port B
1B
7
VCC(B)
8
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[3]
Input
Input/output[1]
DIR[2]
nA
nB
L
nA = nB
input
Z
input
nB = nA
Z
H
X
[1] The input circuit of the data I/O is always active.
[2] The DIR input circuit is referenced to VCC(A)
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
3 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-50
-0.5
-50
-0.5
-0.5
-
Max
+4.6
+4.6
-
Unit
V
VCC(A) supply voltage A
VCC(B) supply voltage B
V
IIK
input clamping current
VI < 0 V
mA
V
VI
input voltage
[1]
+4.6
-
IOK
VO
output clamping current
output voltage
VO < 0 V
mA
Active mode
[1][2][3]
[1]
VCCO + 0.5 V
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
+4.6
±50
100
-
V
IO
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[4]
mW
[1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SOT765-1 (VSSOP8) package: Ptot derates linearly with 4.9 mW/K above 99 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
VCC(A) supply voltage A
VCC(B) supply voltage B
3.6
V
VI
input voltage
3.6
V
VO
output voltage
Active mode
[1]
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
-40
-
+125
5
°C
ns/V
Δt/ΔV
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
4 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
10. Static characteristics
Table 7. Typical static characteristics at Tamb = 25 °C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). [1][2]
Symbol Parameter
Conditions
Min
Typ
Max Unit
VOH
VOL
II
HIGH-level output
voltage
VI = VIH or VIL; IO = -1.5 mA;
VCC(A) = VCC(B) = 0.8 V
-
0.69
-
V
LOW-level output
voltage
VI = VIH or VIL; IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
-
0.07
-
V
input leakage current
DIR input; VI = 0 V or 3.6 V;
±0.025 ±0.25 μA
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW current VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
bus hold HIGH current VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
[3]
[4]
[5]
-
-
-
26
-24
28
-
-
-
μA
μA
μA
IBHH
IBHLO
bus hold LOW
VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V
overdrive current
IBHHO
IOZ
bus hold HIGH
overdrive current
VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V
[6]
[7]
-
-
-
-
-
-
-26
±0.5
±0.1
±0.1
1.0
-
μA
OFF-state output
current
A or B port; VO = 0 V or VCCO
;
±2.5 μA
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOFF
power-off leakage
current
A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V;
VCC(B) = 0.8 V to 3.6 V
±1
±1
-
μA
μA
pF
pF
B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V;
VCC(A) = 0.8 V to 3.6 V
CI
input capacitance
DIR input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
CI/O
input/output
capacitance
A and B port; Suspend mode; VO = VCCO or GND;
VCC(A) = VCC(B) = 3.3 V
4.0
-
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max.
IBHL should be measured after lowering VI to GND and then raising it to VIL max.
[4] The bus hold circuit can source at least the minimum high sustaining current at VIH min.
IBHH should be measured after raising VI to VCC and then lowering it to VIH min.
[5] An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7] For I/O ports, the parameter IOZ includes the input leakage current.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
5 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).[1][2]
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 0.8 V
0.70VCCI
0.65VCCI
1.6
-
-
-
-
0.70VCCI
0.65VCCI
1.6
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
2
2
DIR input
VCC(A) = 0.8 V
0.70VCC(A)
-
-
-
-
0.70VCC(A)
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
0.65VCC(A)
0.65VCC(A)
1.6
2
1.6
2
VIL
LOW-level
data input
input voltage
VCCI = 0.8 V
-
-
-
-
0.30VCCI
0.35VCCI
0.7
-
-
-
-
0.30VCCI
0.35VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
0.9
0.9
DIR input
VCC(A) = 0.8 V
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
0.9
0.9
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -100 μA;
VCCO - 0.1
-
VCCO - 0.1
-
V
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IO = -3 mA; VCC(A) = VCC(B) = 1.1 V
IO = -6 mA; VCC(A) = VCC(B) = 1.4 V
0.85
1.05
1.2
-
-
-
0.85
1.05
1.2
-
-
-
V
V
V
IO = -8 mA;
VCC(A) = VCC(B) = 1.65 V
IO = -9 mA; VCC(A) = VCC(B) = 2.3 V
1.75
2.3
-
-
1.75
2.3
-
-
V
V
IO = -12 mA;
VCC(A) = VCC(B) = 3.0 V
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 100 μA;
-
0.1
-
0.1
V
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
IO = 8 mA; VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
IO = 12 mA; VCC(A) = VCC(B) = 3.0 V
-
-
-
-
-
-
0.25
0.35
0.45
0.55
0.7
-
-
-
-
-
-
0.25
0.35
0.45
0.55
0.7
V
V
V
V
V
II
input leakage DIR input; VI = 0 V or 3.6 V;
current VCC(A) = VCC(B) = 0.8 V to 3.6 V
±1
±1.5
μA
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
6 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Max
Min
Max
IBHL
bus hold LOW A or B port
current
[3]
[4]
VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V
15
25
-
-
15
25
-
-
μA
μA
VI = 0.58 V;
VCC(A) = VCC(B) = 1.65 V
VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V
VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V
45
-
-
45
90
-
-
μA
μA
100
IBHH
bus hold
A or B port
HIGH current
VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V
-15
-25
-
-
-15
-25
-
-
μA
μA
VI = 1.07 V;
VCC(A) = VCC(B) = 1.65 V
VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V
VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V
-45
-
-
-45
-
-
μA
μA
-100
-100
IBHLO
bus hold LOW A or B port
overdrive
[5]
[6]
[7]
VCC(A) = VCC(B) = 1.6 V
125
200
300
500
-
-
-
-
125
200
300
500
-
-
-
-
μA
μA
μA
μA
current
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
IBHHO
bus hold
HIGH
overdrive
current
A or B port
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port; VO = 0 V or VCCO
-125
-200
-300
-500
-
-
-
-125
-200
-300
-500
-
-
μA
μA
μA
μA
μA
-
-
-
-
-
IOZ
OFF-state
;
±5
±7.5
output current VCC(A) = VCC(B) = 0.8 to 3.6 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
-
±5
±5
-
-
±35
±35
μA
μA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
8
-
11.5
μA
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
B port; VI = 0 V or VCCI; IO = 0 A
-
8
-
-
11.5
-
μA
μA
-2
-8
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
8
-
11.5
μA
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
A plus B port (ICC(A) + ICC(B));
-2
-
-
-8
-
-
μA
μA
μA
8
11.5
23
-
16
-
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
;
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max.
IBHL should be measured after lowering VI to GND and then raising it to VIL max.
[4] The bus hold circuit can source at least the minimum high sustaining current at VIH min.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
7 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
IBHH should be measured after raising VI to VCC and then lowering it to VIH min.
[5] An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7] For I/O ports, the parameter IOZ includes the input leakage current.
11. Dynamic characteristics
Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5; for waveforms see Fig. 3 and Fig. 4. [1] [2]
Symbol Parameter
Conditions
VCC(B)
1.5 V
Unit
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
1.2 V
8.4
1.8 V
8.0
2.5 V
8.7
3.3 V
9.5
tpd
tdis
ten
propagation delay
A to B
8.0
12.4
12.2
7.6
ns
ns
ns
ns
ns
ns
B to A
12.7
12.2
7.9
12.2
12.2
8.2
12.0
12.2
8.7
11.8
12.2
10.2
22.0
21.7
disable time
enable time
DIR to A
DIR to B
DIR to A
DIR to B
20.6
20.6
20.0
20.2
20.4
20.2
20.7
20.9
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
[2] ten is a calculated value using the formula shown in Section 12.4
Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5; for waveforms see Fig. 3 and Fig. 4. [1] [2]
Symbol Parameter
Conditions
VCC(A)
1.5 V
Unit
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
1.2 V
12.7
8.4
1.8 V
12.2
8.0
2.5 V
12.0
8.7
3.3 V
11.8
9.5
tpd
tdis
ten
propagation delay
A to B
12.4
8.0
ns
ns
ns
ns
ns
ns
B to A
disable time
enable time
DIR to A
DIR to B
DIR to A
DIR to B
4.9
3.8
3.7
2.8
3.4
9.2
9.0
8.8
8.7
8.6
17.6
17.6
17.0
16.2
16.8
15.9
17.4
14.8
18.1
15.2
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
[2] ten is a calculated value using the formula shown in Section 12.4
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V).[1] [2]
Symbol Parameter
Conditions
VCC(A) and VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
CPD
power dissipation A port: (direction A to B);
1
2
2
2
2
2
pF
pF
capacitance
B port: (direction B to A)
A port: (direction B to A);
B port: (direction A to B)
9
11
11
12
14
17
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
8 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5; for waveforms see Fig. 3 and Fig. 4. [1][2]
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
2.2
2.2
-
9.0
9.0
0.7
0.8
2.2
1.8
-
6.8
8.0
0.6
0.7
2.2
2.0
-
6.1
7.7
0.5
0.6
2.2
1.7
-
5.7
7.2
0.5
0.5
2.2
2.4
-
6.1 ns
7.1 ns
8.8 ns
7.2 ns
14.3 ns
14.9 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
8.8
8.8
8.8
8.8
8.4
6.7
6.9
6.2
enable time
17.4
17.8
14.7
15.6
14.6
14.9
13.4
14.5
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.6
2.0
-
8.0
6.8
0.7
0.8
1.6
1.8
-
5.4
5.4
0.6
0.7
1.6
1.6
-
4.6
5.1
0.5
0.6
1.6
1.2
-
3.7
4.7
0.5
0.5
1.6
1.7
-
3.5 ns
4.5 ns
6.3 ns
5.5 ns
10.0 ns
9.8 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
6.3
6.3
6.3
6.3
7.6
5.9
6.0
4.8
enable time
14.4
14.3
11.3
11.7
11.1
10.9
9.5
-
-
-
-
10.0
-
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.6
1.8
-
7.7
6.1
0.6
0.7
1.6
1.8
-
5.1
4.6
0.5
0.5
1.6
1.4
-
4.3
4.4
0.5
0.5
1.6
1.0
-
3.4
3.9
5.5
4.5
8.4
8.9
0.5
0.5
1.6
1.5
-
3.1 ns
3.7 ns
5.5 ns
5.2 ns
8.9 ns
8.6 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
5.5
5.5
5.5
7.8
5.7
5.8
enable time
13.9
13.2
10.3
10.6
10.2
9.8
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.5
1.7
-
7.2
5.7
0.5
0.6
1.5
2.0
-
4.7
3.8
4.2
5.2
9.0
8.9
0.5
0.5
1.5
1.5
-
3.9
3.4
4.2
5.1
8.5
8.1
0.5
0.5
1.5
0.6
-
3.0
3.0
4.2
4.2
7.2
7.2
0.5
0.5
1.5
1.1
-
2.6 ns
2.8 ns
4.2 ns
4.8 ns
7.6 ns
6.8 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
4.2
7.3
enable time
13.0
11.4
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.5
1.7
-
7.1
6.1
0.5
0.6
1.5
0.7
-
4.5
3.6
4.7
5.5
9.1
9.2
0.5
0.5
1.5
0.6
-
3.7
3.1
4.7
5.5
8.6
8.4
0.5
0.5
1.5
0.7
-
2.8
2.6
4.7
4.1
6.7
7.5
0.5
0.5
1.5
1.7
-
2.4 ns
2.4 ns
4.7 ns
4.7 ns
7.1 ns
7.1 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
4.7
7.2
enable time
13.3
11.8
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
[2] ten is a calculated value using the formula shown in Section 12.4
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
9 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5; for waveforms see Fig. 3 and Fig. 4. [1] [2]
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ±0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
2.2
2.2
-
9.9
9.9
0.7
0.8
2.2
1.8
-
7.5
8.8
0.6
0.7
2.2
2.0
-
6.8
8.5
0.5
0.6
2.2
1.7
-
6.3
8.0
0.5
0.5
2.2
2.4
-
6.8 ns
7.9 ns
9.7 ns
8.0 ns
15.9 ns
16.5 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
9.7
9.7
9.7
9.7
9.2
7.4
7.6
6.9
enable time
19.1
19.6
16.2
17.2
16.1
16.5
14.9
16.0
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.6
2.0
-
8.8
7.5
0.7
0.8
1.6
1.8
-
6.0
6.0
0.6
0.7
1.6
1.6
-
5.1
5.7
0.5
0.6
1.6
1.2
-
4.1
5.2
0.5
0.5
1.6
1.7
-
3.9 ns
5.0 ns
7.0 ns
6.1 ns
11.1 ns
10.9 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
7.0
7.0
7.0
7.0
8.3
6.5
6.6
5.3
enable time
15.8
15.8
12.5
13.0
12.3
12.7
10.5
11.1
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.6
1.8
-
8.5
6.8
0.6
0.7
1.6
1.8
-
5.7
5.1
0.5
0.5
1.6
1.4
-
4.8
4.9
0.5
0.5
1.6
1.0
-
3.8
4.3
6.1
5.0
9.3
9.9
0.5
0.5
1.6
1.5
-
3.5 ns
4.1 ns
6.1 ns
5.8 ns
9.9 ns
9.6 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
6.1
6.1
6.1
8.6
6.3
6.4
enable time
15.4
14.6
11.4
11.8
11.3
10.9
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.5
1.7
-
8.0
6.3
0.5
0.6
1.5
2.0
-
5.2
4.2
0.5
0.5
1.5
1.5
-
4.3
3.8
4.7
5.7
9.5
9.0
0.5
0.5
1.5
0.6
-
3.3
3.3
4.7
4.7
8.0
8.0
0.5
0.5
1.5
1.1
-
2.9 ns
3.1 ns
4.7 ns
5.3 ns
8.4 ns
7.6 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
4.7
4.7
8.0
5.8
enable time
14.3
12.7
10.0
9.9
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation
delay
A to B
1.0
1.0
1.5
1.7
-
7.9
6.8
0.5
0.6
1.5
0.7
-
5.0
4.0
0.5
0.5
1.5
0.6
-
4.1
3.5
5.2
6.1
9.6
9.3
0.5
0.5
1.5
0.7
-
3.1
2.9
5.2
4.6
7.5
8.3
0.5
0.5
1.5
1.7
-
2.7 ns
2.7 ns
5.2 ns
5.2 ns
7.9 ns
7.9 ns
B to A
disable time
DIR to A
DIR to B
DIR to A
DIR to B
5.2
5.2
7.9
6.1
enable time
14.7
13.1
10.1
10.2
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
[2] ten is a calculated value using the formula shown in Section 12.4
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
10 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
11.1. Waveforms and test circuit
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
nB, nA output
V
M
001aak114
V
OL
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 3. The data input (nA, nB) to output (nB, nA) propagation delay times
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
V
M
OFF-to-HIGH
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 4. 3-state enable and disable times
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
VM
Output[2]
VM
VX
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
VOH - 0.1 V
VOH - 0.15 V
VOH - 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
11 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance;
VEXT = External voltage for measuring switching times.
Fig. 5. Test circuit for measuring switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI [1]
VCCI
VCCI
VCCI
Load
CL
VEXT
Δt/ΔV [2]
≤ 1.0 ns/V
≤ 1.0 ns/V
≤ 1.0 ns/V
RL
tPLH, tPHL
tPZH, tPHZ
GND
tPZL, tPLZ [3]
2VCCO
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
open
open
open
GND
2VCCO
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
12 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
12. Application information
12.1. Unidirectional logic level-shifting application
The circuit given in Fig. 6 is an example of the 74AVCH2T45-Q100 being used in an unidirectional
logic level-shifting application.
V
V
CC2
CC1
74AVCH2T45
V
V
CC(B)
V
V
V
V
CC(A)
1A
CC1
CC1
CC2
CC2
1
2
3
4
8
7
6
5
1B
2A
2B
GND
DIR
system-1
system-2
001aag585
Fig. 6. Unidirectional logic level-shifting application
Table 16. Unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
1A
Function
VCC1
OUT1
OUT2
GND
DIR
Description
supply voltage of system-1 (0.8 V to 3.6 V)
output level depends on VCC1 voltage
output level depends on VCC1 voltage
device GND
2
3
2A
4
GND
DIR
5
the GND (LOW level) determines B port to A port direction
input threshold value depends on VCC2 voltage
input threshold value depends on VCC2 voltage
supply voltage of system-2 (0.8 V to 3.6 V)
6
2B
IN2
7
1B
IN1
8
VCC(B)
VCC2
12.2. Bidirectional logic level-shifting application
Fig. 7 shows the 74AVCH2T45-Q100 being used in a bidirectional logic level-shifting application.
Since the device does not have an output enable (OE) pin, the system designer should take
precautions to avoid bus contention between system-1 and system-2 when changing directions.
V
V
V
V
CC2
CC1
CC1
CC2
74AVCH2T45
V
V
CC(B)
CC(A)
1A
I/O-1
I/O-2
1
2
3
4
8
7
6
5
1B
2A
2B
GND
DIR
DIR CTRL
system-1
system-2
001aag586
Fig. 7. Bidirectional logic level-shifting application
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
13 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then
from system-2 to system-1.
Table 17. Bidirectional logic level-shifting application [1]
State DIR CTRL I/O-1
I/O-2
input
Z
Description
1
2
H
H
output
Z
system-1 data to system-2
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled.
The bus-line state depends on bus hold.
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold.
input
output
system-2 data to system-1
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
12.3. Power-up considerations
The device is designed such that no special power-up sequence is required other than GND being
applied first.
Table 18. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
Unit
0 V
0
0.8 V
0.1
0.1
0.1
0.1
0.1
0.7
2.3
1.2 V
0.1
0.1
0.1
0.1
0.1
0.3
1.4
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.9
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.5
2.5 V
0.1
0.7
0.3
0.1
0.1
0.1
0.1
3.3 V
0.1
2.3
1.4
0.9
0.5
0.1
0.1
0 V
μA
μA
μA
μA
μA
μA
μA
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
12.4. Enable times
The enable times for the 74AVCH2T45-Q100 are calculated from the following formulas:
•
•
ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA)
ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB)
In a bidirectional application, these enable times provide the maximum delay from the time the
DIR bit is switched until an output is expected. For example, if the 74AVCH2T45-Q100 initially is
transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled
before presenting it with an input. After the B port has been disabled, an input signal applied to it
appears on the corresponding A port after the specified propagation delay.
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
14 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
E
v
A
Z
5
8
Q
A
2
A
A
(A )
3
1
pin 1 index
θ
L
p
detail X
1
4
L
e
w
b
p
0
5 mm
scale
Dimensions (mm are the original dimensions)
A
(1)
(2)
(1)
Unit
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
max
mm nom
min
0.15 0.85
0.00 0.60
0.27 0.23 2.1 2.4
0.17 0.08 1.9 2.2
3.2
3.0
0.40 0.21
0.15 0.19
0.4
8°
0°
1
0.12
0.5
0.4
0.2 0.08 0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
sot765-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-06-02
16-05-31
SOT765-1
MO-187
Fig. 8. Package outline SOT765-1 (VSSOP8)
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
15 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
14. Abbreviations
Table 19. Abbreviations
Acronym
Description
CDM
DUT
ESD
HBM
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
15. Revision history
Table 20. Revision history
Document ID
Release date Data sheet status
20221207 Product data sheet
Change notice Supersedes
74AVCH2T45_Q100 v.1
-
-
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
16 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
16. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
17 / 18
Nexperia
74AVCH2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................8
11.1. Waveforms and test circuit.......................................11
12. Application information........................................... 13
12.1. Unidirectional logic level-shifting application............13
12.2. Bidirectional logic level-shifting application..............13
12.3. Power-up considerations......................................... 14
12.4. Enable times............................................................14
13. Package outline........................................................ 15
14. Abbreviations............................................................16
15. Revision history........................................................16
16. Legal information......................................................17
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 7 December 2022
©
74AVCH2T45_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 1 — 7 December 2022
18 / 18
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