74HC161PW_技术文档

74HC161

Presettable synchronous 4-bit binary counter; asynchronous

reset

Rev. 5 — 16 March 2021

Product data sheet

1. General description

The 74HC161 is a synchronous presettable binary counter with an internal look-head carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-

going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.

A LOW at the parallel enable input (PE) disables the counting action and causes the data at the

data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset

takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master

reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP

(thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading

of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable

the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a

duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next

cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP

to TC propagation delay and CEP to CP set-up time, according to the following formula:

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

voltages in excess of V_CC

.

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 6.0 V

•

CMOS low power dissipation

•

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

CMOS input levels

Synchronous counting and loading

2 count enable inputs for n-bit cascading

Asynchronous reset

Positive-edge triggered clock

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Specified from -40 °C to +85 °C and -40 °C to +125 °C

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

Version

74HC161D

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74HC161PW -40 °C to +125 °C

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

4. Functional diagram

1

CTR4

R

9

7

M1

G3

G4

15

10

2

TC

14

13

12

11

3

4

5

6

9

D0

D1

D2

D3

PE

Q0

Q1

Q2

Q3

C2/1,3,4+

14

13

12

11

3

4

5

6

1,2D

CEP CET CP MR

15

4 CT = 15

mna905

1

7

10

2

mna906

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

3

4

5

6

D0 D1 D2 D3

PE

PARALLEL LOAD

CIRCUITRY

9

CET

10

TC

15

CEP

CP

7

2

1

BINARY

COUNTER

MR

Q0 Q1 Q2 Q3

14 13 12 11

mna907

Fig. 3. Functional diagram

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

2 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

D1

D2

D3

D0

CET

CEP

PE

FF0

FF1

FF2

FF3

D

Q

D

Q

D

Q

D

Q

CP

Q

R

D

R

D

R

D

CP

MR

Q0

TC

Q1

Q2

Q3

mna910

Fig. 4. Logic diagram

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

3 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

5. Pinning information

5.1. Pinning

74HC161

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MR

CP

V

CC

TC

Q0

Q1

Q2

Q3

CET

PE

74HC161

D0

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MR

CP

V

CC

TC

Q0

Q1

Q2

Q3

CET

PE

D1

D0

D2

D1

D3

D2

D3

CEP

GND

CEP

GND

aaa-024396

aaa-024397

Fig. 5. Pin configuration SOT109-1 (SO16)

Fig. 6. Pin configuration SOT403-1 (TSSOP16)

5.2. Pin description

Table 2. Pin description

Symbol

Description

MR

1

asynchronous master reset (active LOW)

clock input (LOW-to-HIGH, edge-triggered)

data input

CP

2

D0, D1, D2, D3

3, 4, 5, 6

CEP

7

count enable input

GND

8

ground (0 V)

PE

9

parallel enable input (active LOW)

count enable carry input

flip-flop output

CET

10

Q0, Q1, Q2, Q3

14, 13, 12, 11

TC

15

16

terminal count output

supply voltage

V_CC

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Product data sheet

Rev. 5 — 16 March 2021

4 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q_n= lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care; ↑ = LOW-to-HIGH clock transition.

Operating

modes

Input

MR

L

Output

CP

X

↑

CEP

CET

PE

X

l

Dn

X

l

Qn

L

TC

L

Reset (clear)

Parallel load

X

h

l

X

h

X

l

H

L

H

↑

l

h

H

[1]

L

Count

H

↑

h

X

count

q_n

Hold (do nothing)

H

X

H

X

q_n

[1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)

0

1

2

3

4

5

6

7

15

14

13

12

11

10

9

8

aaa-012187

Fig. 7. State diagram

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

5 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

MR

PE

D0

D1

D2

D3

CP

CEP

CET

Q0

Q1

Q2

Q3

TC

12

13

14

15

0

1

2

count

inhibit

reset

preset

mna909

Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero,

one and two; inhibit.

Fig. 8. Typical timing sequence

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7.0

±20

±25

50

Unit

V

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to V_CC+ 0.5 V

-

mA

°C

I_OK

-

I_O

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

-50

-65

-

storage temperature

total power dissipation

+150

500

[1]

mW

[1] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

6 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

Conditions

Min

Typ

Max

6.0

Unit

V

V_CC

V_I

supply voltage

input voltage

2.0

5.0

0

-

V_CC

+125

625

139

83

V

V_O

output voltage

ambient temperature

-

+25

-

V

T_amb

Δt/ΔV

-40

-

°C

input transition rise and fall rate V_CC= 2.0 V

ns/V

V_CC= 4.5 V

V_CC= 6.0 V

-

1.67

-

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

Min Typ

1.5 1.2

3.15 2.4

-40 °C to +85 °C -40 °C to +125 °C Unit

Max

Min

1.5

3.15

4.2

-

Max

-

Min

1.5

3.15

4.2

-

Max

-

V_IH

HIGH-level

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_I= V_IHor V_IL

-

V

input voltage

-

4.2

3.2

0.8

-

V_IL

LOW-level

-

0.5

1.35

1.8

0.5

1.35

1.8

input voltage

2.1 1.35

-

2.8

1.8

-

V_OH

HIGH-level

output voltage

I_O= -20 μA; V_CC= 2.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4.0 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

5.9

3.98 4.32

5.48 5.81

3.84

5.34

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

V

0.1

0.15 0.26

0.16 0.26

0.33

±1.0

I_I

input leakage V_I= V_CCor GND; V_CC= 6.0 V

current

-

±0.1

8.0

-

±1.0 μA

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

80.0

-

160.0 μA

input

3.5

-

pF

capacitance

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

7 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit see Fig. 14.

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

t_pd

propagation

delay

CP to Qn; see Fig. 9

V_CC= 2.0 V

[1]

-

61

22

19

18

190

38

-

240

48

-

285 ns

V_CC= 4.5 V

57

-

ns

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

32

41

48

CP to TC; see Fig. 9

V_CC= 2.0 V

-

69

25

21

20

215

43

-

270

54

-

325 ns

V_CC= 4.5 V

65

-

ns

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

37

46

55

CET to TC; see Fig. 10

V_CC= 2.0 V

-

33

12

10

150

30

-

190

38

-

225 ns

V_CC= 4.5 V

45

-

ns

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

26

38

31

t_PHL

HIGH to LOW MR to Qn; see Fig. 11

propagation

delay

V_CC= 2.0 V

-

63

23

20

18

210

42

-

265

53

-

315 ns

V_CC= 4.5 V

63

-

ns

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

36

45

54

MR to TC; see Fig. 11

V_CC= 2.0 V

-

63

23

20

18

220

44

-

275

55

-

330 ns

V_CC= 4.5 V

66

-

ns

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

37

47

56

t_t

transition time see Fig. 9 and Fig. 10

V_CC= 2.0 V

[2]

-

19

7

75

15

13

-

95

19

16

-

110 ns

V_CC= 4.5 V

22

19

ns

V_CC= 6.0 V

6

t_W

pulse width

CP; HIGH or LOW; see Fig. 9

V_CC= 2.0 V

80

16

14

22

8

-

100

20

-

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

17

20

MR; LOW; see Fig. 11

V_CC= 2.0 V

80

16

14

19

7

-

100

20

-

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

17

20

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

8 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

t_rec

recovery time MR to CP; see Fig. 11

V_CC= 2.0 V

100

20

19

7

-

125

25

-

150

30

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

6

21

26

t_su

set-up time

Dn to CP; see Fig. 12

V_CC= 2.0 V

80

16

14

25

9

-

100

20

-

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

7

17

20

PE to CP; see Fig. 12

V_CC= 2.0 V

100

20

30

11

9

-

125

25

-

150

30

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

21

26

CEP, CET to CP; see Fig. 13

V_CC= 2.0 V

170

34

47

17

14

-

215

43

-

255

51

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

29

37

43

t_h

hold time

Dn, PE, CEP, CET to CP;

see Fig. 12 and Fig. 13

V_CC= 2.0 V

V_CC= 4.5 V

0

-14

-5

-

0

-

0

-

ns

V_CC= 6.0 V

-4

f_max

maximum

frequency

CP; see Fig. 9

V_CC= 2.0 V

4.6

23

-

13

40

44

48

33

-

3.6

18

-

3.0

15

-

MHz

pF

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

27

-

21

-

18

-

C_PD

power

V_I= GND to V_CC; V_CC= 5 V; [3]

f_i= 1 MHz

dissipation

capacitance

[1] t_pdis the same as t_PHLand t_PLH

.

[2] t_tis the same as t_THLand t_TLH

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PDx V_CC²x f_i× N + ∑(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_Lx V_CC²x f_o) = sum of outputs.

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

9 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

10.1. Waveforms and test circuit

1/f

max

V

I

CP input

V

M

GND

t

W

t

PHL

PLH

V

OH

90 %

Qn, TC

output

V

M

10 %

V

OL

t

TLH

THL

aaa-012353

Measurement points are given in Table 8.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 9. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum

frequency

V

I

CET input

TC output

V

M

GND

t

PLH

PHL

V

OH

90 %

V

M

10 %

V

OL

t

THL

TLH

aaa-012354

Measurement points are given in Table 8.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 10. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition

times

V

I

V

M

MR input

GND

t

rec

t

W

V

I

CP input

V

M

GND

t

PHL

V

OH

Qn, TC output

V

M

V

OL

mna913

Measurement points are given in Table 8.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 11. The master reset (MR) pulse width, master reset to output (Qn, TC) propagation delays, and the master

reset to clock (CP) recovery times

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

10 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

V

I

V

M

PE input

CP input

Dn input

GND

t

su

t

h

V

I

V

M

GND

t

su

V

I

V

M

GND

aaa-012356

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 12. The data input (Dn) and parallel enable input (PE) set-up and hold times

V

I

CEP, CET

input

V

M

GND

t

su

t

h

V

I

CP input

V

M

GND

aaa-012358

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 13. The count enable input (CEP) and count enable carry input (CET) set-up and hold times

Table 8. Measurement points

Input

V_M

Output

V_M

V_I

0.5 × V_CC

GND to V_CC

0.5 × V_CC

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

11 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

I

V

O

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 9.

Test circuit definitions:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator

C_L= Load capacitance including jig and probe capacitance

R_L= Load resistance.

S1 = Test selection switch

Fig. 14. Test circuit for measuring switching times

Table 9. Test data

Input

V_I

Load

S1 position

t_PHL, t_PLH

open

t_r, t_f

C_L

R_L

V_CC

6 ns

15 pF, 50 pF

1 kΩ

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

12 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

11. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 15. Package outline SOT109-1 (SO16)

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74HC161

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Product data sheet

Rev. 5 — 16 March 2021

13 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 16. Package outline SOT403-1 (TSSOP16)

©

74HC161

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 16 March 2021

14 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

12. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

ESD

HBM

MM

13. Revision history

Table 11. Revision history

Document ID

74HC161 v.5

Modifications:

Release date

20210316

Data sheet status

Change notice

Supersedes

Product data sheet

-

74HC161 v.4

•

Section 2 updated.

Section 7: Derating values for P_tottotal power dissipation updated.

Type number 74HC161DB (SOT338-1 / SSOP16) removed.

74HC161 v.4

Modifications:

20181004

Product data sheet

-

74HC161 v.3

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74HC161 v.3

Modifications:

20170104

Product data sheet

-

74HC_HCT161 v.2

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

Type numbers 74HCT161D, 74HCT161DB, 74HCT161PW removed.

74HC_HCT161 v.2

19901201

Product specification

-

©

74HC161

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Product data sheet

Rev. 5 — 16 March 2021

15 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74HC161

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 16 March 2021

16 / 17

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................2

4. Functional diagram.......................................................2

5. Pinning information......................................................4

5.1. Pinning.........................................................................4

5.2. Pin description.............................................................4

6. Functional description................................................. 5

7. Limiting values............................................................. 6

8. Recommended operating conditions..........................7

9. Static characteristics....................................................7

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit...................................... 10

11. Package outline........................................................ 13

12. Abbreviations............................................................15

13. Revision history........................................................15

14. Legal information......................................................16

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 16 March 2021

©

74HC161

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 16 March 2021

17 / 17


型号：	74HC161PW
厂家：	Nexperia
描述：	Presettable synchronous 4-bit binary counter; asynchronous resetProduction 光电二极管输出元件逻辑集成电路触发器
文件：	总17页 (文件大小：274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC161PW [NEXPERIA]

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