74HC191PW_技术文档

74HC191

Presettable synchronous 4-bit binary up/down counter

Rev. 6 — 8 September 2021

Product data sheet

1. General description

The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four

master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and

synchronous count-up and count-down operation. Asynchronous parallel load capability permits

the counter to be preset to any desired value. Information present on the parallel data inputs (D0

to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is

LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the

count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by

the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the

direction of counting as indicated in the function table. The CE input may go LOW when the clock is

in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH.

Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow

indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC).

The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down

mode or reaches '15' in the count-up-mode. The TC output will remain HIGH until a state change

occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a

clock signal because it is subject to decoding spikes. The TC signal is used internally to enable

the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This

feature simplifies the design of multistage counters as shown in Fig. 5 and Fig. 6. In Fig. 5, each

RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the

first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse. The

timing skew between state changes in the first and last stages is represented by the cumulative

delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this

configuration in some applications. Fig. 6 shows a method of causing state changes to occur

simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion

and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state

must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through

to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH

shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the

clock. In Fig. 7, the configuration shown avoids ripple delays and their associated restrictions.

Combining the TC signals from all the preceding stages forms the CE input for a given stage. An

enable must be included in each carry gate in order to inhibit counting. The TC output of a given

stage it not affected by its own CE signal therefore the simple inhibit scheme of Fig. 5 and Fig. 6

does not apply. Inputs include clamp diodes. This enables the use of current limiting resistors to

interface inputs to voltages in excess of V_CC

.

2. Features and benefits

•

Wide supply voltage range from 2.0 to 6.0 V

•

CMOS low power dissipation

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

CMOS input levels

Synchronous reversible counting

Asynchronous parallel load

Count enable control for synchronous expansion

Single up/down control input

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

•

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

Version

74HC191D

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74HC191PW -40 °C to +125 °C

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

4. Functional diagram

15

1

10

9

D0 D1 D2 D3

12

13

PL

RC

TC

13

12

11

5

TC

RC

U/D

CE

PARALLEL LOAD

CIRCUIT

15

1

D0

D1

D2

D3

PL

3

2

6

7

Q0

Q1

Q2

Q3

4

10

9

CP

BINARY

COUNTER

14

11

U/D CE CP

Q0 Q1 Q2 Q3

3

2

6

7

5

4

14

aaa-024376

aaa-024375

Fig. 1. Logic symbol

Fig. 2. Functional diagram

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74HC191

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Product data sheet

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74HC191

Presettable synchronous 4-bit binary up/down counter

5. Pinning information

5.1. Pinning

74HC191

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

D1

Q1

V

CC

74HC191

D0

CP

RC

TC

PL

D2

D3

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

D1

Q1

V

CC

Q0

D0

CP

RC

TC

PL

D2

D3

CE

Q0

U/D

Q2

CE

U/D

Q2

Q3

GND

aaa-024377

aaa-024378

Fig. 3. Pin configuration SOT109-1 (SO16)

Fig. 4. Pin configuration SOT403-1 (TSSOP16)

5.2. Pin description

Table 2. Pin description

Symbol

Description

D0, D1, D2, D3

15, 1, 10, 9

data input

Q0, Q1, Q2, Q3

3, 2, 6, 7

flip-flop output

CE

4

count enable input (active LOW)

up/down input

U/D

GND

PL

5

8

ground (0 V)

11

12

13

14

16

parallel load input (active LOW)

terminal count output

ripple clock output (active LOW)

clock input (LOW-to-HIGH, edge-triggered)

supply voltage

TC

RC

CP

V_CC

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH clock transition;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care.

Operating mode

Input

PL

L

Output

Qn

U/D

X

CE

X

l

CP

X

↑

Dn

L

parallel load

L

X

H

X

H

count up

H

L

count up

count down

no change

count down

Hold (do nothing)

H

l

↑

X

H

X

H

X

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

3 / 18

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74HC191

Presettable synchronous 4-bit binary up/down counter

Table 4. TC and RC Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care;

= TC goes LOW on a LOW-to-HIGH clock transition.

= one LOW level pulse;

Input

U/D

H

Terminal count state

Output

CE

H

CP

X

Q0

H

Q1

H

Q2

H

Q3

H

TC

L

RC

H

L

H

X

H

L

H

L

H

L

X

L

H

DIRECTION

CONTROL

U/D

CE

CP

U/D

RC

ENABLE

CLOCK

CE

CP

CE

CP

aaa-024379

Fig. 5. N-stage ripple counter using ripple clock

DIRECTION

CONTROL

U/D

CE

CP

U/D

CE

CP

U/D

CE

CP

RC

ENABLE

CLOCK

aaa-024380

Fig. 6. Synchronous n-stage counter using ripple carry/borrow

DIRECTION

CONTROL

ENABLE

U/D

CE

CP

U/D

CE

CP

U/D

CE

CP

TC

CLOCK

aaa-024381

Fig. 7. Synchronous n-stage counter with parallel gated carry/borrow

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

4 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

PL

D0

D1

D2

D3

CP

U/D

CE

Q0

Q1

Q2

Q3

TC

RC

13

14

15

0

1

2

1

0

15

14

13

load

count up

inhibit

count down

aaa-024383

Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero,

one and two; inhibit.

Fig. 9. Typical timing sequence

7. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7.0

±20

±25

50

Unit

V

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to V_CC+ 0.5 V

-

mA

°C

I_OK

-

I_O

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

-50

-65

-

storage temperature

total power dissipation

+150

500

[1]

mW

[1] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

6 / 18

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74HC191

Presettable synchronous 4-bit binary up/down counter

8. Recommended operating conditions

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

Conditions

Min

Typ

Max

6.0

Unit

V

V_CC

V_I

supply voltage

input voltage

2.0

5.0

0

-

V_CC

+125

625

139

83

V

V_O

output voltage

ambient temperature

-

+25

-

V

T_amb

Δt/ΔV

-40

-

°C

input transition rise and fall rate V_CC= 2.0 V

ns/V

V_CC= 4.5 V

V_CC= 6.0 V

-

1.67

-

9. Static characteristics

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

Min Typ

1.5 1.2

3.15 2.4

-40 °C to +85 °C -40 °C to +125 °C Unit

Max

Min

1.5

3.15

4.2

-

Max

-

Min

1.5

3.15

4.2

-

Max

-

V_IH

HIGH-level

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_I= V_IHor V_IL

-

V

input voltage

-

4.2

3.2

0.8

-

V_IL

LOW-level

-

0.5

1.35

1.8

0.5

1.35

1.8

input voltage

2.1 1.35

-

2.8

1.8

-

V_OH

HIGH-level

output voltage

I_O= -20 μA; V_CC= 2.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4.0; V_CC= 4.5 V

I_O= -5.2; V_CC= 6.0 V

5.9

3.98 4.32

5.48 5.81

3.84

5.34

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

V

0.1

0.15 0.26

0.16 0.26

0.33

±1.0

I_I

input leakage V_I= V_CCor GND; V_CC= 6.0 V

current

-

±0.1

8.0

-

±1.0 μA

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

80.0

-

160.0 μA

input

3.5

-

pF

capacitance

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

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74HC191

Presettable synchronous 4-bit binary up/down counter

10. Dynamic characteristics

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit see Fig. 18.

Symbol Parameter Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

t_pd

propagation CP to Qn; see Fig. 10

[1]

delay

V_CC= 2.0 V

V_CC= 4.5 V

-

72

26

22

21

220

44

-

275

55

-

330 ns

66

-

ns

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

37

47

56

CP to TC; see Fig. 10

V_CC= 2.0 V

-

83

30

24

255

51

-

320

64

-

395 ns

V_CC= 4.5 V

77

65

ns

V_CC= 6.0 V

43

54

CP to RC; see Fig. 11

V_CC= 2.0 V

-

47

17

14

150

30

-

190

38

-

225 ns

V_CC= 4.5 V

45

38

ns

V_CC= 6.0 V

26

33

CE to RC; see Fig. 11

V_CC= 2.0 V

-

33

12

10

130

26

-

165

33

-

195 ns

V_CC= 4.5 V

39

33

ns

V_CC= 6.0 V

22

28

Dn to Qn; see Fig. 12

V_CC= 2.0 V

-

61

22

18

220

44

-

275

55

-

330 ns

V_CC= 4.5 V

66

56

ns

V_CC= 6.0 V

37

47

PL to Qn; see Fig. 13

V_CC= 2.0 V

-

61

22

18

220

44

-

275

55

-

330 ns

V_CC= 4.5 V

66

56

ns

V_CC= 6.0 V

37

47

U/D to TC; see Fig. 14

V_CC= 2.0 V

-

44

16

13

190

38

-

240

48

-

285 ns

V_CC= 4.5 V

57

48

ns

V_CC= 6.0 V

32

41

U/D to RC; see Fig. 14

V_CC= 2.0 V

-

50

18

14

210

42

-

265

53

-

315 ns

V_CC= 4.5 V

63

54

ns

V_CC= 6.0 V

36

45

t_t

transition

time

see Fig. 15

[2]

V_CC= 2.0 V

-

19

7

75

15

13

-

95

19

16

-

110 ns

V_CC= 4.5 V

22

19

ns

V_CC= 6.0 V

6

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

8 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

Symbol Parameter Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

t_W

pulse width CP; HIGH or LOW; see Fig. 10

V_CC= 2.0 V

V_CC= 4.5 V

125

25

28

10

8

-

155

31

-

195

39

-

ns

V_CC= 6.0 V

21

26

33

PL; LOW; see Fig. 15

V_CC= 2.0 V

100

20

22

8

-

125

25

-

150

30

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

6

21

26

t_rec

recovery

time

PL to CP; see Fig. 15

V_CC= 2.0 V

35

7

8

3

2

-

45

9

-

55

11

9

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

8

t_su

set-up time U/D to CP; see Fig. 16

V_CC= 2.0 V

205

41

50

18

14

-

255

51

-

310

62

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

35

43

53

Dn to PL; see Fig. 17

V_CC= 2.0 V

100

20

19

7

-

125

25

-

150

30

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

17

6

21

26

CE to CP; see Fig. 16

V_CC= 2.0 V

140

28

44

16

13

-

175

35

-

210

42

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

24

30

36

t_h

hold time

U/D to CP; see Fig. 16

V_CC= 2.0 V

0

-39

-14

-11

-

0

-

0

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

Dn to PL; see Fig. 17

V_CC= 2.0 V

0

-11

-4

-

0

-

0

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

-3

CE to CP; see Fig. 16

V_CC= 2.0 V

0

-28

-10

-8

-

0

-

0

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

f_max

maximum

frequency

CP; see Fig. 10

V_CC= 2.0 V

4.0

20

-

11

33

36

39

-

3.2

16

-

2.6

13

-

MHz

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

24

19

15

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

9 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

Symbol Parameter Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

C_PD

power

V_I= GND to V_CC; V_CC= 5 V;

[3]

-

31

-

pF

dissipation f_i= 1 MHz

capacitance

[1] t_pdis the same as t_PHLand t_PLH

.

[2] t_tis the same as t_THLand t_TLH

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PDx V_CC²x f_ix N + ∑(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_Lx V_CC²x f_o) = sum of outputs.

10.1. Waveforms and test circuit

1/f

max

V

I

CP input

V

M

GND

t

W

t

PHL

PLH

V

OH

Qn, TC

output

V

M

V

OL

aaa-024384

Measurement points are given in Table 9.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 10. The clock input (CP) to outputs (Qn, TC) propagation delays, clock pulse width and maximum clock

frequency

V

I

CP, CE input

RC output

V

M

GND

t

PLH

PHL

V

OH

V

M

V

OL

aaa-024385

Measurement points are given in Table 9.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 11. The clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation delays

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74HC191

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Product data sheet

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10 / 18

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74HC191

Presettable synchronous 4-bit binary up/down counter

V

I

Dn input

V

M

GND

t

PLH

PHL

V

OH

V

Qn output

M

V

OL

aaa-024386

Measurement points are given in Table 9.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 12. The input (Dn) to output (Qn) propagation delays

V

l

Dn input

GND

V

l

PL input

GND

V

M

t

PHL

PLH

V

OH

Qn output

V

M

V

OL

aaa-024387

Measurement points are given in Table 9.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 13. The parallel load input (PL) to output (Qn) propagation delays

V

I

U/D input

V

M

GND

t

PHL

PLH

V

OH

V

TC output

RC output

M

V

OL

t

PLH

PHL

V

OH

V

M

V

OL

aaa-024388

Measurement points are given in Table 9.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 14. The up/down count input (U/D) to terminal count and ripple clock output (TC, RC) propagation delays

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

11 / 18

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74HC191

Presettable synchronous 4-bit binary up/down counter

V

I

PL input

V

M

GND

t

W

t

rec

V

I

CP input

V

M

GND

t

PHL

V

OH

90 %

V

M

Qn output

10 %

V

OL

t

THL

TLH

aaa-024389

Measurement points are given in Table 9.

Logic levels V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 15. The parallel load input (PL) to clock (CP) recovery times, parallel load pulse width and output (Qn)

transition times

V

l

CP input

CE, U/D input

V

M

GND

t

su

t

h

V

l

V

M

GND

t

su

t

h

V

l

V

M

GND

aaa-024391

Measurement points are given in Table 9.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 16. The count enable and up/down count inputs (CE, U/D) to clock input (CP) set-up and hold times

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

12 / 18

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74HC191

Presettable synchronous 4-bit binary up/down counter

V

l

Dn input

PL input

V

M

GND

t

su

t

h

V

l

V

M

aaa-024390

GND

Measurement points are given in Table 9.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 17. The parallel load input (PL) to data input (Dn) set-up and hold times

Table 9. Measurement points

Input

V_M

Output

V_M

V_I

0.5 x V_CC

GND to V_CC

0.5 x V_CC

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

I

V

O

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 10.

Test circuit definitions:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator

C_L= Load capacitance including jig and probe capacitance

R_L= Load resistance.

S1 = Test selection switch

Fig. 18. Test circuit for measuring switching times

Table 10. Test data

Input

V_I

Load

S1 position

t_PHL, t_PLH

open

t_r, t_f

C_L

R_L

V_CC

6 ns

15 pF, 50 pF

1 kΩ

©

74HC191

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 September 2021

13 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

11. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 19. Package outline SOT109-1 (SO16)

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

14 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 20. Package outline SOT403-1 (TSSOP16)

©

74HC191

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 September 2021

15 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

12. Abbreviations

Table 11. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

ESD

HBM

MM

13. Revision history

Table 12. Revision history

Document ID

74HC191 v.6

Modifications:

Release date

20210908

Data sheet status

Change notice

Supersedes

Product data sheet

-

74HC191 v.5

•

Type number 74HC191DB (SOT338-1/SSOP16) removed.

Section 2 updated.

74HC191 v.5

Modifications:

20190813

Product data sheet

-

74HC191 v.4

74HC191 v.3

•

Type number 74HC191DB (SOT338-1/SSOP16) added.

Table 5: Derating values for P_tottotal power dissipation updated

74HC191 v.4

Modifications:

20181005

Product data sheet

-

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Type number 74HC191DB (SOT338-1/SSOP16) removed.

74HC191 v.3

Modifications:

20170103

Product data sheet

-

74HC_HCT191 v.2

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

Type numbers 74HCT191D, 74HCT191DB, 74HCT191PW removed.

74HC_HCT191_CNV v.2 19901201

Product specification

-

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74HC191

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Product data sheet

Rev. 6 — 8 September 2021

16 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74HC191

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Product data sheet

Rev. 6 — 8 September 2021

17 / 18

Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................2

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description.............................................................3

6. Functional description................................................. 3

7. Limiting values............................................................. 6

8. Recommended operating conditions..........................7

9. Static characteristics....................................................7

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit...................................... 10

11. Package outline........................................................ 14

12. Abbreviations............................................................16

13. Revision history........................................................16

14. Legal information......................................................17

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 8 September 2021

©

74HC191

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Product data sheet

Rev. 6 — 8 September 2021

18 / 18


型号：	74HC191PW
厂家：	Nexperia
描述：	Presettable synchronous 4-bit binary up/down counterProduction 光电二极管输出元件逻辑集成电路触发器
文件：	总18页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC191PW [NEXPERIA]

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