74HC193D [NEXPERIA]
Presettable synchronous 4-bit binary up/down counterProduction;
| 型号： | 74HC193D |
| 厂家： | 
Nexperia |
| 描述： | Presettable synchronous 4-bit binary up/down counterProduction 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总24页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 7 — 8 September 2021
Product data sheet
1. General description
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down
clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously
with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held
HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will
count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior.
The device can be cleared at any time by the asynchronous master reset input (MR); it may also
be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up
(TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached
the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go
LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The
terminal count outputs can be used as the clock input signals to the next higher order circuit in
a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be
fully synchronous, since there is a slight delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load capability of the circuit. Information
present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs
(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.
A HIGH level on the master reset (MR) input will disable the parallel load gates, override both
clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after
a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a
legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC
.
2. Features and benefits
•
Wide supply voltage range from 2.0 to 6.0 V
•
•
•
•
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
•
•
For 74HC193: CMOS level
For 74HCT193: TTL level
•
•
•
•
•
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standards:
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74HC193D
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT193D
74HC193PW
74HCT193PW
-40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Functional diagram
15
D0
1
10
D2
9
D1
D3
PL
TCU
TCD
11
5
PL
11
D0
15
D1
1
D2
10
D3
9
12
13
CPU
CPD
COUNTER
4
CPU
CPD
5
4
12
13
TCU
TCD
MR
14
FLIP-FLOPS
Q0 Q1 Q2
14
3
2
6
7
Q3
3
2
6
7
001aag405
MR Q0
Q1
Q2
Q3 001aag409
Fig. 1. Functional diagram
Fig. 2. Logic symbol
CTR4
11
5
C3
2+
G1
1-
4
G2
R
14
15
1
3
2
6
7
3D
10
9
13
12
2CT = 0
1CT = 15
001aag410
Fig. 3. IEC logic symbol
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
2 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
D0
D1
D2
D3
PL
CPU
TCU
SD
SD
SD
SD
Q
Q
Q
Q
T
FF1
T
FF2
T
FF3
T
FF4
Q
Q
Q
Q
RD
RD
RD
RD
TCD
CPD
MR
Q0
Q1
Q2
Q3
001aag412
Fig. 4. Logic diagram
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
3 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1. Pinning
74HC193
74HCT193
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
Q1
V
CC
74HC193
74HCT193
D0
Q0
MR
TCD
TCU
PL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
Q1
V
CC
D0
CPD
CPU
Q2
Q0
MR
TCD
TCU
PL
CPD
CPU
Q2
Q3
D2
Q3
D2
GND
D3
GND
D3
001aag406
001aag407
Fig. 5. Pin configuration for SOT109-1 (SO16)
Fig. 6. Pin configuration for SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
data input
D0, D1, D2, D3
15, 1, 10, 9
Q0, Q1, Q2, Q3
3, 2, 6, 7
flip-flop output
CPD
CPU
GND
PL
4
count down clock input; LOW-to-HIGH, edge triggered
count up clock input; LOW-to-HIGH, edge triggered
ground (0 V)
5
8
11
12
13
14
16
asynchronous parallel load input (active LOW)
terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)
asynchronous master reset input (active HIGH)
supply voltage
TCU
TCD
MR
VCC
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
4 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating mode
Reset (clear)
Inputs
Outputs
MR PL
CPU CPD D0
D1
X
X
L
D2
X
X
L
D3
X
X
L
Q0
L
Q1
Q2
L
Q3
L
TCU TCD
H
H
L
L
L
L
L
L
X
X
L
X
X
X
X
L
L
X
X
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L
L
L
H
L
Parallel load
L
L
L
L
H
X
X
H
↑
L
L
L
L
L
L
L
H
H
H
L
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
H
H
H
H
L
H
↑
H
Count up
H
H
count up
H [1] H
H H [2]
Count down
H
count down
[1] TCU = CPU at terminal count up (HHHH)
[2] TCD = CPD at terminal count down (LLLL).
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
5 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
(1)
MR
PL
D0
D1
D2
D3
(2)
CPU
(2)
CPD
Q0
Q1
Q2
Q3
TCU
TCD
0
13
14
15
0
1
2
1
0
15
14
13
COUNT UP
COUNT DOWN
CLEAR PRESET
001aag411
(1) Clear overrides load, data and count inputs.
(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock
input (CPU) must be HIGH.
Sequence:
Clear (reset outputs to zero);
Load (preset) to binary thirteen;
Count up to fourteen, fifteen, terminal count up, zero, one and two;
Count down to one, zero, terminal count down, fifteen, fourteen and thirteen.
Fig. 7. Typical clear, load and count sequence
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
6 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±20
±25
50
Unit
V
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to VCC + 0.5 V
[1]
[1]
-
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
-
IGND
Tstg
Ptot
ground current
-50
storage temperature
total power dissipation
-65
-
+150
500
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC193
74HCT193
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
0
-
VCC
VCC
+125
625
139
83
0
0
-
VCC
VCC
VO
output voltage
-
+25
-
-
+25
-
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
-40
-
+125 °C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
ns/V
-
1.67
-
-
1.67
-
139 ns/V
-
-
-
ns/V
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
7 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
9. Static characteristics
Table 6. Static characteristics type 74HC193
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 °C
VIH
Parameter
Conditions
Min
Typ
Max Unit
HIGH-level input
voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
3.15
4.2
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
V
V
V
V
V
V
-
-
VIL
LOW-level input
voltage
0.5
-
1.35
-
1.8
VOH
HIGH-level output
voltage
-
-
-
-
-
-
-
IO = -20 μA; VCC = 2.0 V
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4.0 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
-
-
0
0
0.1
0.1
V
V
V
V
V
0
0.1
0.15
0.16
-
0.26
0.26
II
input leakage current VI = VCC or GND; VCC = 6.0 V
±0.1 μA
ICC
Ci
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
-
8.0
-
μA
pF
input capacitance
3.5
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
8 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Tamb = -40 °C to +85 °C
VIH HIGH-level input
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
-
-
-
-
-
-
-
-
V
V
V
V
V
V
voltage
3.15
4.2
-
VIL
LOW-level input
voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output
voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4.0 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
5.9
3.84
5.34
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.33
0.33
II
input leakage current VI = VCC or GND; VCC = 6.0 V
±1.0 μA
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
80
μA
Tamb = -40 °C to +125 °C
VIH
HIGH-level input
voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
VCC = 6.0 V
4.2
-
VIL
LOW-level input
voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = -20 μA; VCC = 2.0 V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4.0 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level output
voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
II
input leakage current VI = VCC or GND; VCC = 6.0 V
±1.0 μA
160 μA
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
9 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Table 7. Static characteristics type 74HCT193
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 °C
VIH
Parameter
Conditions
Min
Typ
Max Unit
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
V
V
VIL
LOW-level input
voltage
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
4.5
-
-
V
V
IO = -4.0 mA
3.98
4.32
VOL
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
-
-
0
0.1
V
V
IO = 4.0 mA
0.15
0.26
II
input leakage current VI = VCC or GND; VCC = 5.5 V
-
-
±0.1 μA
ICC
ΔICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
8.0
μA
additional supply
current
per input pin;
VI = VCC - 2.1 V; other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
-
-
-
35
140
65
126
504
234
378
-
μA
μA
μA
μA
pF
pins CPU, CPD
pin PL
pin MR
105
3.5
Ci
input capacitance
Tamb = -40 °C to +85 °C
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
VIL
LOW-level input
voltage
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
-
-
-
-
V
V
IO = -4.0 mA
3.84
VOL
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
-
-
-
-
-
-
0.1
V
V
IO = 4.0 mA
0.33
II
input leakage current VI = VCC or GND; VCC = 5.5 V
±1.0 μA
80 μA
ICC
ΔICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
additional supply
current
per input pin;
VI = VCC - 2.1 V; other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
-
-
-
-
-
-
157.5 μA
630 μA
pins CPU, CPD
pin PL
292.5 μA
472.5 μA
pin MR
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
10 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Tamb = -40 °C to +125 °C
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
VIL
LOW-level input
voltage
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
3.7
-
-
-
-
V
V
IO = -4.0 mA
VOL
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
-
-
-
-
-
-
0.1
0.4
V
V
IO = 4.0 mA
II
input leakage current VI = VCC or GND; VCC = 5.5 V
±1.0 μA
160 μA
ICC
ΔICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
additional supply
current
per input pin;
VI = VCC - 2.1 V; other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
-
-
-
-
-
-
171.5 μA
686 μA
pins CPU, CPD
pin PL
318.5 μA
514.5 μA
pin MR
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
11 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristics
Table 8. Dynamic characteristics type 74HC193
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tpd
propagation
delay
CPU, CPD to Qn; see Fig. 8 [1]
VCC = 2.0 V
-
-
-
-
63 215
-
-
-
270
54
-
-
-
325
65
ns
ns
ns
VCC = 4.5 V
23
18
43
37
VCC = 6.0 V
46
55
CPU to TCU; see Fig. 9
VCC = 2.0 V
-
-
-
39 125
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
14
11
25
21
VCC = 6.0 V
26
32
CPD to TCD; see Fig. 9
VCC = 2.0 V
-
-
-
39 125
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
14
11
25
21
VCC = 6.0 V
26
32
PL to Qn; see Fig. 10
VCC = 2.0 V
-
-
-
69 220
-
-
-
275
55
-
-
-
330
66
ns
ns
ns
VCC = 4.5 V
25
20
44
37
VCC = 6.0 V
47
56
MR to Qn; see Fig. 11
VCC = 2.0 V
-
-
-
58 200
-
-
250
50
-
-
-
300
60
ns
ns
ns
VCC = 4.5 V
21
17
40
34
VCC = 6.0 V
43
51
Dn to Qn; see Fig. 10
VCC = 2.0 V
-
-
-
69 210
-
-
-
265
53
-
-
-
315
63
ns
ns
ns
VCC = 4.5 V
25
20
42
36
VCC = 6.0 V
45
54
PL to TCU, PL to TCD;
see Fig. 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
80 290
-
-
-
365
73
-
-
-
435
87
ns
ns
ns
29
23
58
49
62
74
MR to TCU, MR to TCD;
see Fig. 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
74 285
-
-
-
355
71
-
-
-
430
86
ns
ns
ns
27
22
57
48
60
73
Dn to TCU, Dn to TCD;
see Fig. 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
80 290
-
-
-
365
73
-
-
-
435
87
ns
ns
ns
29
23
58
49
62
74
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74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
12 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tTHL
tTLH
tW
HIGH to LOW see Fig. 11
output
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
transition time
VCC = 4.5 V
VCC = 6.0 V
6
19
LOW to HIGH see Fig. 11
output
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
transition time
VCC = 4.5 V
VCC = 6.0 V
6
19
pulse width
CPU, CPD; HIGH or LOW;
see Fig. 8
VCC = 2.0 V
VCC = 4.5 V
100 22
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
20
17
8
6
VCC = 6.0 V
21
26
MR HIGH; see Fig. 11
VCC = 2.0 V
100 25
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
9
7
VCC = 6.0 V
21
26
PL LOW; see Fig. 10
VCC = 2.0 V
100 19
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
7
6
VCC = 6.0 V
21
26
trec
recovery time PL to CPU, CPD; see Fig. 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
8
3
2
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
MR to CPU, CPD;
see Fig. 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
0
0
0
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
tsu
set-up time
hold time
Dn to PL; see Fig. 12;
CPU = CPD = HIGH
VCC = 2.0 V
VCC = 4.5 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
6
17
20
th
Dn to PL; see Fig. 12
VCC = 2.0 V
0
0
0
-14
-5
-
-
-
0
0
0
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
-4
CPU to CPD, CPD to CPU;
see Fig. 14
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
8
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
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74HC_HCT193
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
13 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
fmax
maximum
frequency
CPU, CPD; see Fig. 8
VCC = 2.0 V
4.0 13.5
-
-
-
-
3.2
16
19
-
-
-
-
-
2.6
13
15
-
-
-
-
-
MHz
MHz
MHz
pF
VCC = 4.5 V
20
24
-
41
49
24
VCC = 6.0 V
CPD
power
dissipation
capacitance
VI = GND to VCC; VCC = 5 V; [2]
fi = 1 MHz
[1] tpd is the same as tPHL and tPLH
.
[2] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC 2 x fo) = sum of outputs.
Table 9. Dynamic characteristics type 74HCT193
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tpd
propagation
delay
CPU, CPD to Qn; see Fig. 8 [1]
VCC = 4.5 V
-
-
-
-
-
-
23
15
15
26
22
27
43
27
27
46
40
46
-
-
-
-
-
-
54
-
-
-
-
-
-
65
ns
ns
ns
ns
ns
ns
CPU to TCU; see Fig. 9
VCC = 4.5 V
34
41
CPD to TCD; see Fig. 9
VCC = 4.5 V
34
41
PL to Qn; see Fig. 10
VCC = 4.5 V
58
69
MR to Qn; see Fig. 11
VCC = 4.5 V
50
60
Dn to Qn; see Fig. 10
VCC = 4.5 V
58
69
PL to TCU, PL to TCD;
see Fig. 13
VCC = 4.5 V
-
-
31
29
55
55
-
-
69
69
-
-
83
83
ns
ns
MR to TCU, MR to TCD;
see Fig. 13
VCC = 4.5 V
Dn to TCU, Dn to TCD;
see Fig. 13
VCC = 4.5 V
-
-
32
7
58
15
-
-
73
19
-
-
87
22
ns
ns
tTHL
HIGH to LOW see Fig. 11
output
VCC = 4.5 V
transition time
tTLH
LOW to HIGH see Fig. 11
output
transition time
VCC = 4.5 V
-
7
15
-
19
-
22
ns
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74HC_HCT193
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
14 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tW
pulse width
CPU, CPD; HIGH or LOW;
see Fig. 8
VCC = 4.5 V
MR HIGH; see Fig. 11
VCC = 4.5 V
25
20
20
10
11
7
-
-
-
-
31
25
25
13
-
-
-
-
38
30
30
15
-
-
-
-
ns
ns
ns
ns
PL LOW; see Fig. 10
VCC = 4.5 V
8
trec
recovery time PL to CPU, CPD; see Fig. 10
VCC = 4.5 V
2
MR to CPU, CPD;
see Fig. 11
VCC = 4.5 V
10
0
-
13
-
15
-
ns
tsu
set-up time
hold time
Dn to PL; see Fig. 12;
CPU = CPD = HIGH
VCC = 4.5 V
Dn to PL; see Fig. 12
VCC = 4.5 V
16
0
8
-
-
20
0
-
-
24
0
-
-
ns
ns
th
-6
CPU to CPD, CPD to CPU;
see Fig. 14
VCC = 4.5 V
CPU, CPD; see Fig. 8
VCC = 4.5 V
16
7
-
20
-
24
-
ns
fmax
maximum
frequency
20
-
43
26
-
-
16
-
-
-
13
-
-
-
MHz
pF
CPD
power
dissipation
capacitance
VI = GND to VCC - 1.5 V;
VCC = 5 V; fi = 1 MHz
[2]
[1] tpd is the same as tPHL and tPLH
.
[2] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC 2 x fo) = sum of outputs.
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74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
15 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
10.1. Waveforms and test circuit
1/f
max
V
I
CPU, CPD
input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
Qn output
M
001aag413
V
OL
Measurement points are given in Table 10.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
V
I
CPU, CPD
input
V
M
GND
t
t
PHL
PLH
V
OH
TCU, TCD
output
V
M
V
001aag414
OL
Measurement points are given in Table 10.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays
V
I
Dn input
V
V
M
M
GND
V
I
PL input
GND
t
rec
t
W
V
I
CPU, CPD
input
V
M
GND
t
t
PHL
PLH
V
OH
Qn output
V
M
V
OL
001aag415
Measurement points are given in Table 10.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 10. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
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74HC_HCT193
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
16 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
V
I
MR input
V
M
GND
t
t
rec
W
V
I
CPU, CPD
input
V
M
GND
t
PHL
V
OH
90 %
V
M
Qn output
10 %
V
OL
t
t
THL
TLH
001aag416
Measurement points are given in Table 10.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 11. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and
output transition times
V
I
V
Dn input
PL input
M
GND
t
t
su
su
t
t
h
h
V
I
V
M
GND
V
OH
Qn output
V
OL
001aag417
Measurement points are given in Table 10.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 12. The data input (Dn) to parallel load input (PL) set-up and hold times
V
I
PL, MR, Dn
input
V
M
GND
t
t
PLH
PHL
V
OH
TCU, TCD
output
V
M
V
OL
001aag418
Measurement points are given in Table 10.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 13. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU, TCD) propagation delays
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74HC_HCT193
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
17 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
V
I
CPU or CPD
input
V
M
GND
t
h
V
I
CPD or CPU
input
V
M
GND
001aag419
Measurement points are given in Table 10.
Fig. 14. The CPU to CPD or CPD to CPU hold times
Table 10. Measurement points
Type
Input
VM
Output
VM
VI
74HC193
0.5 × VCC
1.3 V
GND to VCC
GND to 3 V
0.5 × VCC
1.3 V
74HCT193
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig. 15. Test circuit for measuring switching times
Table 11. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC193
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT193
open
©
74HC_HCT193
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
18 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
11. Application information
data input
D0 D1 D2 D3
CPU
CPD IC1 TCD
PL MR
Q0 Q1 Q2 Q3
D0 D1 D2 D3
CPU
CPD IC2 TCD
PL MR
Q0 Q1 Q2 Q3
up clock
carry
TCU
TCU
down clock
borrow
asynchronous
parallel load
reset
data output
001aag420
Fig. 16. Application for cascaded up/down counter with parallel load
©
74HC_HCT193
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
19 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 17. Package outline SOT109-1 (SO16)
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
20 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 18. Package outline SOT403-1 (TSSOP16)
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
21 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
13. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 13. Revision history
Document ID
Release date
20210908
Data sheet status
Change notice
Supersedes
74HC_HCT193 v.7
Modifications:
Product data sheet
-
74HC_HCT193 v.6
•
•
Section 2 updated.
Type number 74HCT193DB (SOT338-1/SSOP16) removed.
74HC_HCT193 v.6
Modifications:
20210205
Product data sheet
-
74HC_HCT193 v.5
•
•
Type number 74HC193DB (SOT338-1/SSOP16) removed.
Section 7: Derating values for Ptot total power dissipation updated.
74HC_HCT193 v.5
Modifications:
20160129
Product data sheet
-
74HC_HCT193 v.4
•
Type numbers 74HC193N and 74HCT193N (SOT38-4) removed.
74HC_HCT193 v.4
Modifications:
20130624
Product data sheet
-
74HC_HCT193 v.3
•
General description updated.
74HC_HCT193 v.3
Modifications:
20070523
Product data sheet
-
74HC_HCT193_CNV v.2
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Family specification included.
74HC_HCT193_CNV v.2 19970828
Product specification
-
-
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
22 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
23 / 24
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description.............................................................4
6. Functional description................................................. 5
7. Limiting values............................................................. 7
8. Recommended operating conditions..........................7
9. Static characteristics....................................................8
10. Dynamic characteristics.......................................... 12
10.1. Waveforms and test circuit...................................... 16
11. Application information............................................19
12. Package outline........................................................ 20
13. Abbreviations............................................................22
14. Revision history........................................................22
15. Legal information......................................................23
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 8 September 2021
©
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 8 September 2021
24 / 24
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