74HC597D [NEXPERIA]
8-bit shift register with input flip-flopsProduction;
| 型号： | 74HC597D |
| 厂家： | 
Nexperia |
| 描述： | 8-bit shift register with input flip-flopsProduction 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC597; 74HCT597
8-bit shift register with input flip-flops
Rev. 5 — 26 October 2021
Product data sheet
1. General description
The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift
register have positive edge-triggered clocks. The shift register also has direct load (from storage)
and clear inputs. Inputs include clamp diodes that enable the use of current limiting resistors to
interface inputs to voltages in excess of VCC
.
2. Features and benefits
•
Wide supply voltage range from 2.0 V to 6.0 V
•
•
•
CMOS low power dissipation
High noise immunity
Input levels:
•
•
For 74HC597: CMOS level
For 74HCT597: TTL level
•
•
•
•
8-bit parallel storage register inputs
Shift register has direct overriding load and clear
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
•
ESD protection:
•
•
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
•
•
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC597D
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT597D
74HCT597DB
-40 °C to +125 °C
-40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
SOT403-1
74HC597PW
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74HCT597PW
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
4. Functional diagram
STCP
12
MR
10
DS
14
STCP
12
MR
10
DS
14
15
1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
15
1
2
2
3
8-BIT
SHIFT
REGISTER
INPUT
FLIP-FLOPS
3
INPUT
FLIP-
FLOPS
8-BIT
SHIFT
REGISTER
4
4
5
5
6
6
7
9
Q
7
9
Q
13
11
13
11
PL SHCP
PL SHCP
aaa-012057
aaa-012056
Fig. 1. Functional diagram
Fig. 2. Logic symbol
SRG8
R
10
11
13
12
C3/
C2
C1
1
3D
2D
2D
14
15
1
1D
1D
2
3
4
5
6
9
7
aaa-012055
Fig. 3. IEC Logic symbol
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
2 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
MR
SHCP
PL
STCP
DS
D0
C2
S
1D
2D
C1
R
C3 3S
3R
1D
D1
D2
D3
D4
D5
D6
D7
S
C1
R
C3 3S
3R
1D
S
C1
R
C3 3S
1D
S
3R
C1
R
C3
S
3S
3R
1D
C1
R
3S
3R
C3
S
1D
C1
R
C3 3S
3R
1D
S
C1
R
C3 3S
3R
1D
S
Q
C1
R
aaa-012058
Fig. 4. Logic diagram
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
3 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
5. Pinning information
5.1. Pinning
74HC597
74HCT597
74HC597
74HCT597
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
D2
V
CC
D0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
D2
V
CC
D3
DS
D0
D3
DS
D4
PL
D4
PL
D5
STCP
SHCP
MR
Q
D5
STCP
SHCP
MR
Q
D6
D6
D7
D7
GND
GND
aaa-012054
aaa-012939
Fig. 6. Pin configuration SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
Fig. 5. Pin configuration SOT109-1 (SO16)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
GND
8
ground (0 V)
Q
9
serial data output
MR
10
asynchronous master reset input (active LOW)
shift register clock input (LOW-to-HIGH, edge-triggered)
storage register clock input (LOW-to-HIGH, edge-triggered)
parallel load input (active LOW)
serial data input
SHCP
11
STCP
12
PL
13
DS
14
D0, D1, D2, D3, D4, D5, D6, D7
VCC
15, 1, 2, 3, 4, 5, 6, 7
16
parallel data inputs
supply voltage
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
4 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition.
Inputs
Function
STCP
SHCP
PL
X
L
MR
X
↑
X
X
X
X
data loaded to input latches
↑
H
data loaded from inputs to shift register
data transferred from input flip-flops to shift register
no clock edge
X
L
H
L
L
invalid logic, state of shift register is indeterminate
when signals removed
X
X
X
↑
H
H
L
shift register cleared
H
shift register clocked Qn = Qn-1, Q0 = DS
SHCP
DS
MR
PL
STCP
D0
D1
D2
D3
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
L
H
L
D4
D5
D6
H
H
L
D7
Q
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
L
L
L
L
H
H
reset
shift
serial shift
serial shift
serial shift
register
serial shift
load input
register
load input
register
parallel load
shift register
parallel load
shift register
parallel load both
input and shift registers
aaa-012059
Fig. 7. Timing diagram
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
5 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to (VCC + 0.5 V)
-
±20
±20
±25
+50
-
mA
mA
mA
mA
mA
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
storage temperature
total power dissipation
+150 °C
[1]
500
mW
[1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT338-1 (SSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC597
74HCT597
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
0
-
VCC
VCC
+125
625
139
83
0
0
-
VCC
VCC
VO
output voltage
-
+25
-
-
+25
-
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
-40
-
+125 °C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
ns/V
-
1.67
-
-
1.67
-
139 ns/V
-
-
-
ns/V
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
6 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC597
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
3.15 2.4
3.15
3.15
4.2
3.2
0.8
-
4.2
-
4.2
-
VIL
LOW-level input VCC = 2.0 V
voltage
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
output voltage
VI = VIH or VIL
IO = -20 μA; VCC = 2.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
5.9
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81
3.84
5.34
VOL
LOW-level
output voltage
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
±0.1
8.0
-
μA
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
-
-
80.0
-
-
-
160.0 μA
pF
input
3.5
-
capacitance
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
7 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
Symbol Parameter
74HCT597
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level input VCC = 4.5 V to 5.5 V
voltage
0.8
0.8
0.8
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = -20 μA
IO = -4.0 mA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA
0.15 0.26
0.33
±1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
±0.1
±1.0
μA
ICC
ΔICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80.0
-
160.0 μA
additional
VI = VCC - 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; DS input
per input pin; Dn inputs
-
-
-
25
30
90
-
-
-
112.5
135
-
-
-
122.5 μA
108
147
735
μA
μA
per input pin; PL, MR
inputs
150 540
675
per input pin; STCP,
SHCP inputs
-
-
150 540
-
-
675
-
-
-
735
-
μA
pF
CI
input
3.5
-
capacitance
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
8 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 14.
Symbol Parameter Conditions
74HC597
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tpd
propagation SHCP to Q; see Fig. 8
[1]
delay
VCC = 2.0 V
VCC = 4.5 V
-
-
-
-
55
20
17
16
175
35
-
-
-
-
-
220
44
-
-
-
-
-
265
53
-
ns
ns
ns
ns
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
30
37
45
MR to Q; see Fig. 9
VCC = 2.0 V
[1]
[1]
-
-
-
58
21
17
175
35
-
-
-
220
44
-
-
-
265
53
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
30
37
45
STCP to Q; see Fig. 8
VCC = 2.0 V
-
-
-
-
80
29
25
23
250
50
-
-
-
-
-
315
63
-
-
-
-
-
375
75
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
43
54
64
PL to Q; see Fig. 10
VCC = 2.0 V
[1]
[2]
-
-
-
-
69
25
21
20
215
43
-
-
-
-
-
270
54
-
-
-
-
-
325
65
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
37
46
55
tt
transition
time
Q; see Fig. 10
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
9 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
Symbol Parameter Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tW
pulse width STCP HIGH or LOW;
see Fig. 8
VCC = 2.0 V
80
16
14
11
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
17
20
SHCP HIGH or LOW;
see Fig. 8
VCC = 2.0 V
VCC = 4.5 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
4
17
20
MR LOW; see Fig. 9
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
PL LOW; see Fig. 10
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
trec
recovery
time
MR to SHCP; see Fig. 11
VCC = 2.0 V
60
12
10
-3
-1
-1
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tsu
set-up time Dn to STCP; see Fig. 12
VCC = 2.0 V
60
12
10
8
3
2
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
DS to SHCP; see Fig. 12
VCC = 2.0 V
60
12
10
11
4
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
PL to SHCP; see Fig. 13
VCC = 2.0 V
60
12
10
11
4
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
th
hold time
Dn to STCP; see Fig. 12
VCC = 2.0 V
5
5
5
-3
-1
-1
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
PL, DS to SHCP; see Fig. 12
VCC = 2.0 V
5
5
5
-6
-2
-2
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
10 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
Symbol Parameter Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
fmax
maximum
frequency
SHCP; see Fig. 8
VCC = 2.0 V
6.0
30
-
29
87
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4.0
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
96
35
-
104
29
28
-
24
-
CPD
power
CL = 50 pF; f = 1 MHz;
dissipation VI = GND to VCC
capacitance
[3]
[1]
74HCT597
tpd
propagation SHCP to Q; see Fig. 8
delay
VCC = 4.5 V
-
-
23
20
40
-
-
-
50
-
-
-
60
-
ns
ns
VCC = 5.0 V; CL = 15 pF
MR to Q; see Fig. 9
VCC = 4.5 V
[1]
[1]
-
28
49
-
61
-
74
ns
STCP to Q; see Fig. 8
VCC = 4.5 V
-
-
33
29
57
-
-
-
71
-
-
-
86
-
ns
ns
VCC = 5.0 V; CL = 15 pF
PL to Q; see Fig. 10
VCC = 4.5 V
[1]
[2]
-
-
30
26
52
-
-
-
65
-
-
-
78
-
ns
ns
VCC = 5.0 V; CL = 15 pF
Q; see Fig. 10
tt
transition
time
VCC = 4.5 V
-
7
6
15
-
-
19
-
-
22
-
ns
ns
tW
pulse width STCP HIGH or LOW;
see Fig. 8
VCC = 4.5 V
16
20
24
SHCP HIGH or LOW;
see Fig. 8
VCC = 4.5 V
MR LOW; see Fig. 9
VCC = 4.5 V
16
25
20
12
12
12
12
5
7
14
10
-2
5
-
-
-
-
-
-
-
-
-
20
31
25
15
15
15
15
5
-
-
-
-
-
-
-
-
-
24
38
30
18
18
18
18
5
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
PL LOW; see Fig. 10
VCC = 4.5 V
trec
recovery
time
MR to SHCP; see Fig. 11
VCC = 4.5 V
tsu
set-up time Dn to STCP; see Fig. 12
VCC = 4.5 V
DS to SHCP; see Fig. 12
VCC = 4.5 V
2
PL to SHCP; see Fig. 13
VCC = 4.5 V
4
th
hold time
Dn to STCP; see Fig. 12
VCC = 4.5 V
-1
-2
PL, DS to SHCP; see Fig. 12
VCC = 4.5 V
5
5
5
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74HC_HCT597
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
11 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
Symbol Parameter Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
fmax
maximum
frequency
SHCP; see Fig. 8
VCC = 4.5 V
30
-
75
83
32
-
-
-
24
-
-
-
-
20
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
CL = 50 pF; f = 1 MHz;
CPD
power
[3]
-
-
-
dissipation VI = GND to VCC - 1.5 V
capacitance
[1] tpd is the same as tPLH and tPHL
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + ∑(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC 2 × fo) = sum of outputs.
10.1. Waveforms and test circuit
1/f
max
V
I
STCP, SHCP
input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
Q output
V
M
V
OL
aaa-012368
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. SHCP and STCP clock inputs to Q output propagation delays, pulse width and maximum clock frequency
V
I
V
MR input
M
GND
t
W
t
PHL
V
OH
Q output
V
M
V
OL
aaa-012369
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. Input MR to Q output propagation delays and MR pulse width
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74HC_HCT597
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
12 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
1/f
max
V
I
V
PL input
Q output
M
GND
t
W
t
t
PLH
PHL
90 %
V
OH
90 %
V
M
10 %
10 %
V
OL
t
t
TLH
THL
aaa-012371
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 10. Input PL to Q output propagation delays, PL pulse width and output transition times
V
I
V
MR input
M
GND
t
rec
V
I
SHCP input
V
M
GND
aaa-012372
Measurement points are given in Table 8.
Fig. 11. Input MR to shift clock SHCP and storage clock STCP recovery times
V
I
positive
DS, Dn input
V
V
M
M
GND
V
I
negative
DS, Dn input
GND
t
t
h
su
V
I
V
V
M
M
SHCP input
STCP input
GND
V
I
GND
t
t
h
su
aaa-012374
Measurement points are given in Table 8.
Fig. 12. Set-up and hold times for DS, Dn inputs to SHCP, STCP inputs
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74HC_HCT597
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
13 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
V
I
PL input
V
M
GND
V
I
V
M
SHCP input
GND
t
t
h
su
aaa-012375
Measurement points are given in Table 8.
Fig. 13. Set-up and hold times for PL input to SHCP input
Table 8. Measurement points
Type
Input
VM
Output
VM
VI
74HC597
0.5 × VCC
1.3 V
GND to VCC
GND to 3 V
0.5 × VCC
1.3 V
74HCT597
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig. 14. Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC597
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT597
open
GND
VCC
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74HC_HCT597
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
14 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 15. Package outline SOT109-1 (SO16)
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74HC_HCT597
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
15 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
E
v
M
A
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.2
0.13
0.1
0.25
0.65
1.25
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig. 16. Package outline SOT338-1 (SSOP16)
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
16 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 17. Package outline SOT403-1 (TSSOP16)
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
17 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MM
Complementary Metal Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74HC_HCT597 v.5
Modifications:
20211026
Product data sheet
-
74HC_HCT597 v.4
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74HC597DB (SOT338-1/SSOP16) removed.
Type number 74HCT597PW (SOT403-1/TSSOP16) added.
Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
74HC_HCT597 v.4
Modifications:
20160225
Type numbers 74HC597N and 74HCT597N (SOT38-4) removed.
20140415 Product data sheet 74HC_HCT597_CNV v.2
Product data sheet
-
74HC_HCT597 v.3
•
74HC_HCT597 v.3
Modifications:
-
•
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT597_CNV v.2
19901201
Product specification
-
-
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
18 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
19 / 20
Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description.............................................................4
6. Functional description................................................. 5
7. Limiting values............................................................. 6
8. Recommended operating conditions..........................6
9. Static characteristics....................................................7
10. Dynamic characteristics............................................ 9
10.1. Waveforms and test circuit...................................... 12
11. Package outline........................................................ 15
12. Abbreviations............................................................18
13. Revision history........................................................18
14. Legal information......................................................19
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 26 October 2021
©
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 26 October 2021
20 / 20
相关型号：
74HC597D/T3
IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, MINI, PLASTIC, SO-16, Shift Register
NXP
74HC597DB
IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register
NXP
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