74HC73D-Q100 [NEXPERIA]
Dual JK flip-flop with reset; negative-edge triggerProduction;型号: | 74HC73D-Q100 |
厂家: | Nexperia |
描述: | Dual JK flip-flop with reset; negative-edge triggerProduction |
文件: | 总12页 (文件大小:216K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
Rev. 1 — 4 December 2020
Product data sheet
1. General description
The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP)
and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be
stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR)
is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW
and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant
to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
CMOS low-power dissipation
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC73D-Q100
-40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
4. Functional diagram
14 1J
1 1CP
3 1K
1Q 12
1Q 13
J
Q
Q
FF1
CP
K
R
2 1R
14
1J
12
1
C1
3
2
14
7
1J
2J
1Q 12
7 2J
5 2CP
10 2K
2Q
2Q
9
8
1K
R
J
Q
Q
J
Q
Q
13
2Q
9
FF2
FF
R
1
5
1CP
2CP
CP
K
CP
K
7
5
1J
9
8
3
10
1K
2K
1Q 13
2Q
C1
8
10
6
R
1K
R
6 2R
1R 2R
2 6
001aab981
001aab979
001aab980
Fig. 1. Functional diagram
Fig. 2. Logic symbol
Fig. 3. IEC logic symbol
C
C
C
C
K
J
Q
C
C
C
C
R
Q
C
C
CP
001aab982
Fig. 4. Logic diagram (one flip-flop)
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
2 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
5. Pinning information
5.1. Pinning
74HC73
1
2
3
4
5
6
7
14
13
12
11
10
9
1CP
1R
1J
1Q
1Q
GND
2K
1K
V
CC
2CP
2R
2Q
2Q
8
2J
001aab978
Fig. 5. Pin configuration SOT108-1 (SO14)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
1, 5
Description
1CP, 2CP
1R, 2R
1K, 2K
VCC
clock input (HIGH-to-LOW edge-triggered); also referred to as nCP
asynchronous reset input (active LOW); also referred to as nR
synchronous K input; also referred to as nK
positive supply voltage
2, 6
3, 10
4
GND
11
ground (0 V)
1Q, 2Q
1Q, 2Q
1J, 2J
12, 9
13, 8
14, 7
true output; also referred to as nQ
complement output; also referred to as nQ
synchronous J input; also referred to as nJ
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care; ↓ = HIGH-to-LOW clock transition.
Input
nR
L
Output
Operating mode
nCP
nJ
X
h
l
nK
X
h
h
l
nQ
L
nQ
H
q
X
↓
↓
↓
↓
asynchronous reset
toggle
H
q
H
L
H
L
load 0 (reset)
load 1 (set)
H
h
l
H
q
H
l
q
hold (no change)
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
3 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7.0
±20
±20
±25
50
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to VCC + 0.5 V
[1]
[1]
-
mA
mA
mA
mA
mA
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150 °C
500 mW
Tamb = -40 °C to +125 °C
[2]
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
input voltage
0
0
-
V
VO
output voltage
-
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
-
°C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
1.67
-
ns/V
ns/V
ns/V
-
-
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C
-40 °C to
+125 °C
Unit
Min
1.5
3.15
4.2
-
Typ Max
Min
1.5
3.15
4.2
-
Max
Min
Max
-
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
-
1.5
V
V
V
V
V
V
3.15
-
-
-
4.2
-
VIL
LOW-level
input voltage
0.5
1.35
1.8
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
-
-
-
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
4 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C
-40 °C to
+125 °C
Unit
Min
Typ Max
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
5.9
3.98 4.32
5.48 5.81
3.84
5.34
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
II
input leakage VI = VCC or GND; VCC = 6.0 V
current
-
±0.1
4.0
-
±1.0 μA
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
-
-
40.0
-
-
-
80.0 μA
input
3.5
-
pF
capacitance
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 8
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C
-40 °C to
+125 °C
Unit
Min
Typ Max
Min
Max
Min Max
tpd
propagation nCP to nQ; see Fig. 6
[1]
delay
VCC = 2.0 V
-
-
-
-
52
19
15
16
160
32
27
-
-
-
-
-
200
40
34
-
-
-
-
-
240 ns
VCC = 4.5 V
VCC = 6.0 V
48
41
-
ns
ns
ns
VCC = 5.0 V; CL = 15 pF
nCP to nQ; see Fig. 6
VCC = 2.0 V
-
-
-
-
52
19
15
16
160
32
27
-
-
-
200
40
-
-
-
240 ns
VCC = 4.5 V
48
41
ns
ns
ns
VCC = 6.0 V
34
VCC = 5.0 V; CL = 15 pF
nR to nQ, nQ; see Fig. 7
VCC = 2.0 V
-
-
-
-
-
50
18
14
15
145
29
25
-
-
-
180
36
31
-
-
-
-
-
220 ns
VCC = 4.5 V
44
38
-
ns
ns
ns
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
-
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
5 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C
-40 °C to
+125 °C
Unit
Min
Typ Max
Min
Max
Min
Max
tt
transition
time
nQ, nQ; see Fig. 6
VCC = 2.0 V
[2]
-
-
-
19
7
75
15
13
-
-
95
19
16
-
-
-
110 ns
VCC = 4.5 V
22
19
ns
ns
VCC = 6.0 V
6
tW
pulse width
nCP input, HIGH or LOW;
see Fig. 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
22
8
-
-
-
100
20
120
24
-
-
ns
ns
ns
-
-
6
17
20
nR input, HIGH or LOW;
see Fig. 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
22
8
-
-
-
100
20
120
24
-
-
ns
ns
ns
-
-
6
17
20
trec
recovery time nR to nCP; see Fig. 7
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
120
24
-
-
ns
ns
ns
VCC = 4.5 V
-
-
VCC = 6.0 V
6
17
20
tsu
set-up time
hold time
nJ, nK to nCP; see Fig. 6
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
120
24
-
-
ns
ns
ns
VCC = 4.5 V
-
-
VCC = 6.0 V
6
17
20
th
nJ, nK to nCP; see Fig. 6
VCC = 2.0 V
3
3
3
-8
-3
-2
-
-
-
3
3
3
3
3
3
-
-
ns
ns
ns
VCC = 4.5 V
-
-
VCC = 6.0 V
fmax
maximum
frequency
nCP input; see Fig. 6
VCC = 2.0 V
6.0
30
35
-
23
70
83
77
30
-
-
-
-
-
4.8
24
28
4.0
20
24
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
-
-
-
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
CPD
power
per flip-flop; VI = GND to VCC [3]
-
-
-
dissipation
capacitance
[1] tpd is the same as tPHL, tPLH
.
[2] tt is the same as tTHL, tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + ∑(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC 2 × fo) = sum of outputs.
©
74HC73_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
6 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
10.1. Waveforms and test circuit
V
I
nJ, nK
input
V
M
t
GND
t
t
h
h
t
su
su
1/f
max
V
I
V
M
nCP input
GND
t
W
t
t
PLH
PHL
90 %
V
OH
90 %
nQ output
V
M
10 %
10 %
V
OL
t
t
THL
TLH
90 %
V
OH
90 %
nQ output
V
M
10 %
10 %
V
OL
t
t
THL
TLH
t
t
PLH
PHL
001aab983
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width,
the J and K to nCP set-up and hold times, the output transition times and the maximum clock frequency
V
I
V
M
nCP input
GND
t
rec
t
W
V
I
V
M
nR input
GND
t
PHL
V
OH
nQ output
V
OL
t
PLH
V
OH
nQ output
001aab984
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width
and the nR to nCP removal time
Table 8. Measurement points
Input
VI
Output
VM
VM
VCC
0.5VCC
0.5VCC
©
74HC73_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
7 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
I
V
O
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig. 8. Test circuit for measuring switching times
Table 9. Test data
Input
VI
Load
tr, tf
CL
VCC
6 ns
15 pF, 50 pF
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
8 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig. 9. Package outline SOT108-1 (SO14)
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
9 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
DUT
ESD
HBM
MM
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
13. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20201204 Product data sheet
Change notice Supersedes
74HC73_Q100 v.1
-
-
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
10 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
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product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
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14. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
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and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
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customer’s applications and products using Nexperia products in order to
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Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
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given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
11 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 3
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................4
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms and test circuit........................................ 7
11. Package outline.......................................................... 9
12. Abbreviations............................................................10
13. Revision history........................................................10
14. Legal information......................................................11
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 4 December 2020
©
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
12 / 12
相关型号:
74HC73PW-T
IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, FF/Latch
NXP
74HC73U
IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC, DIE, FF/Latch
NXP
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