74HCT109D_技术文档

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

Rev. 5 — 5 August 2021

Product data sheet

1. General description

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and

K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock

input. The J and K inputs control the state changes of the flip-flops as described in the mode

select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH

clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by

connecting the J and K inputs together. This device features reduced input threshold levels to allow

interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current

limiting resistors to interface inputs to voltages in excess of V_CC

.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall

times.

2. Features and benefits

•

J and K inputs for easy D-type flip-flop

•

Toggle flip-flop or "do nothing" mode

Wide supply voltage range:

•

For 74HC109: from 2.0 V to 6.0 V

For 74HCT109: from 4.5 V to 5.5 V

•

CMOS low power dissipation

High noise immunity

Input levels:

•

For 74HC109: CMOS level

For 74HCT109: TTL level

•

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

74HC109 complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

74HCT109 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC109D

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74HCT109D

74HC109PW

74HCT109PW

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

4. Functional diagram

5

11

1SD 2SD

SD

5

2

11

14

S

1Q

2Q

6

2

14

4

1J

2J

1CP

2CP

Q

J

10

1J

6

7

10

9

CP

4

3

1

12

13

15

12

C1

FF

1Q

2Q

7

9

3

13

1K

2K

Q

K

1K

R

1K

R

RD

1RD 2RD

1 15

(a)

(b)

mna858

mna856

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Q

C

K

J

C

S

R

C

CP

aaa-024066

Fig. 3. Logic diagram (one flip-flop)

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74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

2 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

5. Pinning information

5.1. Pinning

74HC109

74HCT109

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1RD

1J

V

CC

74HC109

74HCT109

2RD

2J

1K

1

2

3

4

5

6

7

8

16

15 2RD

14

V

1RD

1J

CC

1CP

1SD

1Q

2K

1K

2J

2CP

2SD

2Q

1CP

1SD

1Q

13 2K

12 2CP

11 2SD

10 2Q

1Q

GND

2Q

GND

9

2Q

aaa-024067

aaa-024068

Fig. 4. Pin configuration SOT109-1 (SO16)

Fig. 5. Pin configuration SOT403-1 (TSSOP16)

5.2. Pin description

Table 2. Pin description

Symbol

1RD, 2RD

1J, 2J

Description

1, 15

2, 14

3, 13

4, 12

5, 11

6, 10

7, 9

8

asynchronous reset input (active LOW)

synchronous input

1K, 2K

synchronous input

1CP, 2CP

1SD, 2SD

1Q, 2Q

GND

clock input (LOW-to-HIGH; edge-triggered)

asynchronous set input (active LOW)

true flip-flop output

complement flip-flop output

ground (0 V)

V_CC

16

supply voltage

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74HC_HCT109

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Product data sheet

Rev. 5 — 5 August 2021

3 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

6. Functional description

Table 3. Function selection

H = HIGH voltage level; h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition;

L = LOW voltage level; l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition;

q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition;

X = don’t care; ↑ = LOW-to-HIGH CP transition

Operating modes

Input

nSD

L

Output

nRD

H

nCP

X

nJ

X

h

l

nK

X

l

nQ

H

L

nQ

L

Asynchronous set

Asynchronous reset

Undetermined

Toggle

H

L

X

H

q

L

X

H

q

H

↑

Load 0 (reset)

Load 1 (set)

H

↑

l

L

H

L

H

↑

h

l

h

H

q

Hold no change

H

↑

q

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+7

Unit

V

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

-0.5 V < V_O< V_CC+ 0.5 V

-

±20

±25

+50

-

mA

°C

I_OK

I_O

-

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

-50

-65

-

storage temperature

total power dissipation

+150

500

[1]

mW

[1] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

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74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

4 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

Conditions

74HC109

74HCT109

Unit

Min

Typ

Max

6.0

Min

Typ

Max

5.5

V_CC

V_I

supply voltage

input voltage

2.0

5.0

4.5

5.0

V

0

-

V_CC

+125

625

139

83

0

-

V_CC

V_O

output voltage

ambient temperature

-

+25

-

+25

-

T_amb

Δt/ΔV

-40

-

-40

-

+125 °C

input transition rise and fall rate V_CC= 2.0 V

-

ns/V

V_CC= 4.5 V

V_CC= 6.0 V

-

1.67

-

1.67

-

139 ns/V

-

ns/V

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

74HC109

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_I= V_IHor V_IL

1.5

1.2

2.4

3.2

0.8

2.1

2.8

-

1.5

-

1.5

-

V

3.15

4.2

-

4.2

-

4.2

-

V_IL

LOW-level

input voltage

-

0.5

1.35

1.8

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_OH

HIGH-level

output voltage

I_O= -20 μA; V_CC= 2.0 V

1.9

4.4

2.0

4.5

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4.0 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

5.9

6.0

5.9

3.98

5.48

4.32

5.81

3.84

5.34

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

±1

V

0

0.1

V

0.15

0.16

-

0.26

±0.1

0.33

±1

V

I_I

input leakage

current

μA

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

4.0

-

40

-

80

-

μA

pF

input

3.5

capacitance

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

5 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

Symbol Parameter

Conditions

25 °C

Typ

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Max

Min

Max

Min

Max

74HCT109

V_IH

V_IL

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

2.0

-

V

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= -20 μA

4.4

4.5

-

4.4

-

4.4

3.7

-

V

I_O= -4.0 mA

3.98

4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 5.5 V

V_I= V_CCor GND; V_CC= 5.5 V

-

0

0.15

-

0.1

-

0.1

0.33

±1

-

0.1

0.4

±1

V

0.26

±0.1

V

I_I

input leakage

current

μA

I_CC

ΔI_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

4.0

-

40

-

80

μA

additional

per input pin; V_I= V_CC- 2.1 V;

supply current other inputs at V_CCor GND;

V_CC= 4.5 V to 5.5 V

nJ, nK, nSD, nRD and

nCP inputs

-

35

126

-

157.5

-

171.5 μA

pF

C_I

input

3.5

-

capacitance

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Fig. 8.

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

74HC109

t_pd

propagation nCP to nQ, nQ; see Fig. 6

[2]

delay

V_CC= 2.0 V

-

50

18

15

14

175

35

-

220

44

-

265

53

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

30

37

45

t_PLH

LOW to HIGH nSD to nQ, see Fig. 7

propagation

delay

V_CC= 2.0 V

-

30

11

12

9

120

24

-

150

30

-

180

36

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

20

26

31

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

6 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_PHL

t_PLH

HIGH to LOW nSD to nQ; see Fig. 7

propagation

delay

V_CC= 2.0 V

-

41

15

12

155

31

-

195

39

-

235

47

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

26

33

40

HIGH to LOW nRD to nQ; see Fig. 7

propagation

delay

V_CC= 2.0 V

-

41

15

12

185

37

-

230

46

-

280

56

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

31

39

48

LOW to HIGH nRD to nQ; see Fig. 7

propagation

delay

V_CC= 2.0 V

-

39

14

12

11

170

34

-

215

43

-

255

51

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

29

37

43

t_t

transition time nQ, nQ; see Fig. 6

V_CC= 2.0 V

[3]

-

19

7

75

15

13

-

95

19

16

-

110

22

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

19

t_W

pulse width

nCP HIGH or LOW;

see Fig. 6

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

80

16

14

19

7

-

100

20

-

120

24

-

ns

6

17

20

nSD, nRD HIGH or LOW;

see Fig. 7

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

80

16

14

5

-

100

20

-

120

24

-

ns

4

17

20

t_rec

recovery time nSD, nRD to nCP; see Fig. 7

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

70

14

12

19

7

-

90

18

15

-

105

21

-

ns

6

18

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

7 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_su

set-up time

nJ and nK to nCP; see Fig. 6

V_CC= 2.0 V

70

14

12

17

6

-

90

18

15

-

105

21

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

5

18

t_h

hold time

nJ and nK to nCP; see Fig. 6

V_CC= 2.0 V

5

0

-

5

-

5

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

f_max

maximum

frequency

nCP; see Fig. 6

V_CC= 2.0 V

6

30

-

22

68

75

81

20

-

5

24

-

4

20

-

MHz

pF

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

35

-

28

-

24

-

C_PD

power

dissipation

capacitance

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC

[4]

[2]

74HCT109

t_pd

propagation nCP to nQ, nQ;see Fig. 6

delay

V_CC= 4.5 V

-

20

17

35

-

44

-

53

-

ns

V_CC= 5 V; C_L= 15 pF

t_PLH

t_PHL

t_PLH

LOW to HIGH nSD to nQ, see Fig. 7

propagation

delay

V_CC= 4.5 V

-

13

14

26

-

33

-

39

-

ns

V_CC= 5 V; C_L= 15 pF

HIGH to LOW nSD to nQ; see Fig. 7

propagation

delay

V_CC= 4.5 V

-

19

14

35

-

44

-

53

-

ns

V_CC= 5 V; C_L= 15 pF

HIGH to LOW nRD to nQ; see Fig. 7

propagation

delay

V_CC= 4.5 V

-

19

15

35

-

44

-

53

-

ns

V_CC= 5 V; C_L= 15 pF

LOW to HIGH nRD to nQ; see Fig. 7

propagation

delay

V_CC= 4.5 V

-

16

15

7

32

-

40

-

48

-

ns

V_CC= 5 V; C_L= 15 pF

t_t

transition time nQ, nQ; V_CC= 4.5 V;

see Fig. 6

[3]

15

19

22

t_W

pulse width

nCP HIGH or LOW;

V_CC= 4.5 V; see Fig. 6

18

16

9

8

-

23

20

-

27

24

-

ns

nSD, nRD HIGH or LOW;

V_CC= 4.5 V; see Fig. 7

t_rec

recovery time nSD, nRD to nCP;

V_CC= 4.5 V; see Fig. 7

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

8 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_su

t_h

set-up time

hold time

nJ and nK to nCP;

V_CC= 4.5 V; see Fig. 6

18

8

-

23

-

27

-

ns

nJ and nK to nCP;

3

-3

-

3

-

3

-

V_CC= 4.5 V; see Fig. 6

f_max

maximum

frequency

nCP; see Fig. 6

V_CC= 4.5 V

27

-

55

61

22

-

22

-

18

-

MHz

pF

V_CC= 5 V; C_L= 15 pF

C_PD

power

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC- 1.5 V

[4]

-

dissipation

capacitance

[1] All typical values are measured at T_amb= 25 °C.

[2] t_pdis the same as t_PLHand t_PHL

[3] t_tis the same as t_THLand t_TLH

.

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of outputs.

10.1. Waveforms and test circuit

V

I

nJ, nK input

V

M

GND

t

h

t

su

t

su

1/f

max

V

I

nCP input

V

M

GND

t

W

t

PLH

PHL

V

OH

90 %

10 %

V

M

nQ output

10 %

V

OL

t

TLH

THL

t

PHL

PLH

V

OH

90 %

10 %

V

M

nQ output

10 %

V

OL

t

TLH

THL

aaa-024069

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 6. Clock propagation delays, output transition time, pulse width, set-up, hold times, and maximum

frequency

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74HC_HCT109

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Product data sheet

Rev. 5 — 5 August 2021

9 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

V

I

V

M

nCP input

nSD input

nRD input

GND

t

rec

V

I

V

M

GND

t

W

V

I

V

M

GND

t

PLH

t

PHL

V

OH

V

nQ output

M

V

OL

V

OH

M

V

OL

t

PLH

PHL

aaa-024070

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 7. Set and reset propagation delays, pulse widths and recovery time

Table 8. Measurement points

Type

Input

V_M

Output

V_M

74HC109

0.5V_CC

1.3 V

0.5V_CC

1.3 V

74HCT109

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74HC_HCT109

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Product data sheet

Rev. 5 — 5 August 2021

10 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

t

W

V

I

90 %

negative

pulse

V

M

10 %

GND

t

r

f

t

f

r

V

I

90 %

positive

pulse

M

10 %

GND

t

W

V

CC

V

I

V

O

G

DUT

R

T

C

L

001aah768

Test data is given in Table 9.

Definitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

Fig. 8. Test circuit for measuring switching times

Table 9. Test data

Type

Input

V_I

Load

Test

t_r, t_f

6 ns

C_L

74HC109

V_CC

3 V

15 pF, 50 pF

t_PLH, t_PHL

74HCT109

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

11 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

11. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 9. Package outline SOT109-1 (SO16)

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

12 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 10. Package outline SOT403-1 (TSSOP16)

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

13 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

CMOS

DUT

ESD

HBM

MM

Complementary Metal Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20210805 Product data sheet

Change notice Supersedes

- 74HC_HCT109 v.4

74HC_HCT109 v.5

Modifications:

•

Type number 74HC109PW (SOT403-1/TSSOP16) added.

Type numbers 74HC109DB and 74HCT109DB (SOT338-1/SSOP16) removed.

Section 1 and Section 2 updated.

74HC_HCT109 v.4

Modifications:

20200401

Product data sheet

-

74HC_HCT109 v.3

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Table 4: Derating values for P_tottotal power dissipation updated.

74HC_HCT109 v.3

Modifications:

20160801

Product data sheet

-

74HC_HCT109_CNV v.2

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate.

74HC_HCT109_CNV v.2

19971125

Product specification

-

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

14 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

15 / 16

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description.............................................................3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................5

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 9

11. Package outline........................................................ 12

12. Abbreviations............................................................14

13. Revision history........................................................14

14. Legal information......................................................15

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 5 August 2021

©

74HC_HCT109

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 5 August 2021

16 / 16


型号：	74HCT109D
厂家：	Nexperia
描述：	Dual JK flip-flop with set and reset; positive-edge-triggerProduction 光电二极管逻辑集成电路触发器
文件：	总16页 (文件大小：266K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HCT109D [NEXPERIA]

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