74HCT164BQ-Q100 [NEXPERIA]
8-bit serial-in, parallel-out shift register;型号: | 74HCT164BQ-Q100 |
厂家: | Nexperia |
描述: | 8-bit serial-in, parallel-out shift register 逻辑集成电路 触发器 |
文件: | 总18页 (文件大小:725K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
Rev. 1 — 16 August 2013
Product data sheet
1. General description
The 74HC164-Q100; 74HCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The
device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to
Q7). Data is entered serially through DSA or DSB and either input can be used as an
active HIGH enable for data entry through the other input. Data is shifted on the
LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR)
clears the register and forces all outputs LOW, independently of other inputs. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC164-Q100: CMOS level
For 74HCT164-Q100: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC164D-Q100
40 C to +125 C
40 C to +125 C
40 C to +125 C
SO14
plastic small outline package; 14 leads; body
width 3.9 mm
SOT108-1
74HCT164D-Q100
74HC164PW-Q100
74HCT164PW-Q100
74HC164BQ-Q100
74HCT164BQ-Q100
TSSOP14
DHVQFN14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14
terminals; body 2.5 3 0.85 mm
4. Functional diagram
SRG8
8
C1/
9
R
1
3
&
1D
2
4
5
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DSA
1
6
4
2
DSB
5
10
11
12
13
6
10
CP
8
9
11
12
MR
13
001aac423
001aac424
Fig 1. Logic symbol
Fig 2. IEC logic symbol
1
2
DSA
DSB
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
8
9
CP
MR
3
4
5
6
10 11 12 13
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
Fig 3. Logic diagram
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
2 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
DSA
DSB
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac616
Fig 4. Functional diagram
5. Pinning information
5.1 Pinning
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ꢃꢁ
ꢉ
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4ꢁ
4ꢀ
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ꢆ
ꢄ
ꢂ
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ꢅ
ꢇ
ꢆ
ꢄ
ꢂ
ꢀ
ꢃꢆ
4ꢂ
4ꢄ
4ꢆ
05
'6$
'6%
4ꢁ
9
&&
ꢃꢇ
ꢃꢅ
ꢃꢃ
ꢃꢁ
ꢉ
4ꢀ
4ꢂ
4ꢄ
4ꢆ
05
&3
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4ꢃ
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7UDQVSDUHQWꢌWRSꢌYLHZ
DDDꢀꢁꢁꢂꢃꢄꢄ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO14 and TSSOP14
Fig 6. Pin configuration DHVQFN14
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
3 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
5.2 Pin description
Table 2.
Symbol
DSA
Pin description
Pin
1
Description
data input
data input
DSB
2
Q0 to Q7
GND
3, 4, 5, 6, 10, 11, 12, 13
output
7
ground (0 V)
CP
8
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
MR
9
VCC
14
6. Functional description
Table 3.
Function table[1]
Operating
modes
Input
MR
Output
CP
X
DSA
DSB
Q0
L
Q1 to Q7
L to L
Reset (clear)
Shift
L
X
l
X
l
H
H
H
H
L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
l
h
l
L
h
h
L
h
H
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
4 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
-
storage temperature
total power dissipation
+150
500
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC164-Q100
74HCT164-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
+25
40
+25
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
5 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC164-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
8.0
-
A
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
-
-
80
-
-
-
160
-
A
input
3.5
pF
capacitance
74HCT164-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.15 0.26
0.1
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
A
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
6 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8
-
80
-
160
A
A
ICC
additional
per input pin;
-
100
360
-
-
450
-
-
-
490
-
supply current VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
-
3.5
-
pF
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC164-Q100
[1]
tpd
propagation
delay
CP to Qn; see Figure 7
VCC = 2.0 V
-
-
-
-
41 170
-
-
-
-
215
43
-
-
-
-
-
255
51
-
ns
ns
ns
ns
VCC = 4.5 V
15
12
12
34
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
29
37
43
tPHL
HIGH to LOW MR to Qn; see Figure 8
propagation
delay
VCC = 2.0 V
-
-
-
-
39 140
-
-
-
-
175
35
-
-
-
-
-
210
42
-
ns
ns
ns
ns
VCC = 4.5 V
14
11
11
28
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
24
30
36
[2]
tt
transition time see Figure 7
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
CP HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
4
17
20
MR LOW; see Figure 8
VCC = 2.0 V
60
12
10
17
6
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
7 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
trec
recovery time MR to CP; see Figure 8
VCC = 2.0 V
60
12
10
17
6
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
tsu
set-up time
hold time
DSA, and DSB to CP;
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
60
12
10
8
3
2
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
th
DSA, and DSB to CP;
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
+4
+4
+4
6
2
2
-
-
-
4
4
4
-
-
-
4
4
4
-
-
-
ns
ns
ns
VCC = 6.0 V
fmax
maximum
frequency
for Cp, see Figure 7
VCC = 2.0 V
6
30
-
23
71
78
85
40
-
-
-
-
-
5
24
-
-
-
-
-
-
4
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
35
-
28
-
24
-
[3]
[1]
CPD
power
per package;
VI = GND to VCC
dissipation
capacitance
74HCT164-Q100
tpd
propagation
delay
CP to Qn; see Figure 7
VCC = 4.5 V
-
-
17
14
36
-
-
-
45
-
-
-
54
-
ns
ns
VCC = 5.0 V; CL = 15 pF
tPHL
HIGH to LOW MR to Qn; see Figure 8
propagation
delay
VCC = 4.5 V
-
-
19
16
38
-
-
-
48
-
-
-
57
-
ns
ns
VCC = 5.0 V; CL = 15 pF
[2]
tt
transition time see Figure 7
VCC = 4.5 V
-
7
15
-
19
-
22
ns
tW
pulse width
CP HIGH or LOW;
see Figure 7
VCC = 4.5 V
18
18
16
7
10
7
-
-
-
23
23
20
-
-
-
27
27
24
-
-
-
ns
ns
ns
MR LOW; see Figure 8
VCC = 4.5 V
trec
recovery time MR to CP; see Figure 8
VCC = 4.5 V
tsu
set-up time
DSA, and DSB to CP;
see Figure 9
VCC = 4.5 V
12
6
-
15
-
18
-
ns
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
8 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
th
hold time
DSA, and DSB to CP;
see Figure 9
VCC = 4.5 V
+4
2
-
4
-
4
-
ns
fmax
maximum
frequency
for Cp, see Figure 7
VCC = 4.5 V
27
-
55
61
40
-
-
-
22
-
-
-
-
18
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
-
-
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
1/f
max
V
I
CP input
V
t
M
GND
t
W
t
PHL
PLH
V
OH
V
Y
V
Qn output
M
V
X
V
OL
t
t
THL
TLH
001aal392
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC164-Q100
74HCT164-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
9 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
V
I
V
M
MR input
GND
t
f
rec
W
V
I
CP input
V
M
GND
t
PHL
V
OH
V
Qn output
M
V
OL
001aac427
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) removal time
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
001aac428
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Waveforms showing the data set-up and hold times for Dn inputs
74HC_HCT164_Q100
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
10 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 10. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74HC164-Q100
74HCT164-Q100
VCC
3.0 V
6.0 ns
6.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
11 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 11. Package outline SOT108-1 (SO14)
74HC_HCT164_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
12 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
13 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 13. Package outline SOT762-1 (DHVQFN14)
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
14 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
12. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
ESD
HBM
MIL
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date
20130816
Data sheet status
Change notice
Supersedes
74HC_HCT164_Q100 v.1
Product data sheet
-
-
74HC_HCT164_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
15 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
14.2 Definitions
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
14.3 Disclaimers
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
16 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 16 August 2013
17 of 18
74HC164-Q100; 74HCT164-Q100
Nexperia
8-bit serial-in, parallel-out shift register
16. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 16 August 2013
相关型号:
74HCT164D14
Serial In Parallel Out, HCT Series, 8-Bit, Right Direction, True Output, CMOS, PDIP14, GREEN, PLASTIC, DIP-14
DIODES
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