74HCT165PW [NEXPERIA]
8-bit parallel-in/serial out shift registerProduction;型号: | 74HCT165PW |
厂家: | Nexperia |
描述: | 8-bit parallel-in/serial out shift registerProduction 光电二极管 逻辑集成电路 触发器 |
文件: | 总18页 (文件大小:290K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 7 — 1 September 2021
Product data sheet
1. General description
The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device
features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary
serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is
loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at
DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of
the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This
enables the device to be used in HIGH-to-LOW level shifting applications.
2. Features and benefits
•
Wide supply voltage range from 2.0 to 6.0 V
•
•
•
•
•
•
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Asynchronous 8-bit parallel load
Synchronous serial input
Input levels:
•
•
For 74HC165: CMOS level
For 74HCT165: TTL level
•
•
Complies with JEDEC standards:
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
•
•
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
•
Parallel-to-serial data conversion
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC165D
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT403-1
SOT763-1
74HCT165D
74HC165PW
74HCT165PW
74HC165BQ
74HCT165BQ
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
SRG8
1
C2[LOAD]
G1[SHIFT]
15
≥ 1
10
C3/
1
2
DS
11
D0
10
11
12
13
14
3
3D
2D
2D
12
D1
13
D2
14
D3
3
D4
4
D5
5
9
7
D6
D7
PL
Q7
Q7
4
6
1
5
9
7
CP CE
15
6
2
mna985
mna986
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1
PL
10 DS
9
7
Q7
Q7
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
2
CP
CE
15
mna992
Fig. 3. Functional diagram
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
2 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
6. Pinning information
6.1. Pinning
74HC165
74HCT165
terminal 1
index area
74HC165
74HCT165
2
3
4
5
6
7
15
14
13
12
11
10
CP
CE
D3
D2
D1
D0
DS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PL
CP
V
CC
D4
D5
D6
D7
Q7
CE
D3
D2
D1
D0
DS
Q7
D4
(1)
GND
D5
D6
001aah565
D7
Transparent top view
Q7
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
GND
001aah564
Fig. 4. Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16)
Fig. 5. Pin configuration SOT763-1 (DHVQFN16)
6.2. Pin description
Table 2. Pin description
Symbol
PL
Pin
Description
1
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
CP
2
Q7
7
GND
Q7
8
9
serial output from the last stage
serial data input
DS
10
D0 to D7
CE
11, 12, 13, 14, 3, 4, 5, 6
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
15
16
VCC
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
3 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
7. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating modes
Inputs
Qn registers
D0 to D7 Q0
Outputs
PL
L
CE
X
X
L
CP
X
X
↑
DS
X
X
l
Q1 to Q6 Q7
Q7
H
parallel load
L
L
L to L
L
L
H
X
X
X
X
X
X
H
L
H to H
H
L
serial shift
H
H
H
H
H
H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
q6
q6
q6
q6
q7
q7
q6
q6
q6
q6
q7
q7
L
↑
h
H
L
↑
L
l
↑
L
h
H
q0
q0
hold "do nothing"
H
X
X
H
X
X
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
serial shift
mna993
load
Fig. 6. Timing diagram
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
4 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
Min
Max
+7
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
-0.5 V < VO < VCC + 0.5 V
[1]
[1]
-
±20
±20
±25
50
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC165
74HCT165
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
0
-
VCC
VCC
+125
625
139
83
0
0
-
VCC
VCC
VO
output voltage
-
-
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
-
-40
-
-
+125 °C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
1.67
-
-
1.67
-
-
ns/V
-
-
139 ns/V
-
-
-
ns/V
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
74HC165
VIH
HIGH-level input VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
voltage
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level input VCC = 2.0 V
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
voltage
VCC = 4.5 V
VCC = 6.0 V
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
5 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Max
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
2.0
4.5
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4.0 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
5.9
6.0
5.9
3.98
5.48
4.32
5.81
3.84
5.34
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
0
0
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0
0.1
0.1
0.15
0.16
-
0.26
0.26
±0.1
0.33
0.33
±1
II
input leakage
current
±1 μA
ICC
CI
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
8.0
-
-
-
80
-
-
-
160 μA
input
3.5
-
pF
capacitance
74HCT165
VIH
HIGH-level input VCC = 4.5 V to 5.5 V
voltage
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level input VCC = 4.5 V to 5.5 V
voltage
0.8
0.8
0.8
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = -20 μA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = -4.0 mA
3.98
4.32
3.84
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 μA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
0
0.16
-
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
V
V
0.26
±0.1
II
input leakage
current
±1 μA
ICC
ΔICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160 μA
additional supply per input pin; VI = VCC - 2.1 V;
current
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs
-
-
-
35
65
126
234
-
-
-
-
157.5
292.5
-
-
-
-
171.5 μA
318.5 μA
CP, CE, and PL inputs
CI
input
3.5
-
pF
capacitance
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
6 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V);
CL = 50 pF unless otherwise specified; for test circuit, see Fig. 12
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Max
Min
Max
Min
Max
74HC165
tpd
propagation
delay
CP or CE to Q7, Q7; see Fig. 7 [1]
VCC = 2.0 V
-
-
-
-
52
19
15
16
165
33
28
-
-
-
-
-
205
41
35
-
-
-
-
-
250 ns
VCC = 4.5 V
50 ns
43 ns
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Fig. 8
VCC = 2.0 V
-
ns
-
-
-
-
50
18
14
15
165
33
28
-
-
-
-
-
205
41
35
-
-
-
-
-
250 ns
50 ns
43 ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Fig. 9
VCC = 2.0 V
-
ns
-
-
-
-
36
13
10
11
120
24
20
-
-
-
-
-
150
30
26
-
-
-
-
-
180 ns
36 ns
31 ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
-
ns
tt
transition time Q7, Q7 output; see Fig. 7
[2]
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110 ns
22 ns
19 ns
6
tW
pulse width
CP input HIGH or LOW;
see Fig. 7
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
PL input LOW; see Fig. 8
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
trec
recovery time PL to CP, CE; see Fig. 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
22
8
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
17
6
21
26
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
7 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Max
Min
Max
Min
Max
tsu
set-up time
DS to CP, CE; see Fig. 10
VCC = 2.0 V
80
16
14
11
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
17
20
CE to CP and CP to CE;
see Fig. 10
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
Dn to PL; see Fig. 11
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
th
hold time
DS to CP, CE and Dn to PL;
see Fig. 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
5
5
5
2
2
2
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
CE to CP and CP to CE;
see Fig. 10
VCC = 2.0 V
5
5
5
-17
-6
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
-5
fmax
maximum
frequency
CP input; see Fig. 7
VCC = 2.0 V
6
30
35
-
17
51
61
56
35
-
-
-
-
-
5
24
28
-
-
-
-
-
-
4
20
24
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
per package; VI = GND to VCC [3]
CPD
power
-
-
-
dissipation
capacitance
74HCT165
tpd
propagation
delay
CE, CP to Q7, Q7; see Fig. 7 [1]
VCC = 4.5 V
-
-
17
14
34
-
-
-
43
-
-
-
51 ns
ns
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Fig. 8
VCC = 4.5 V
-
-
-
20
17
40
-
-
-
50
-
-
-
60 ns
ns
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Fig. 9
VCC = 4.5 V
-
-
-
14
11
28
-
-
-
35
-
-
-
42 ns
ns
VCC = 5.0 V; CL = 15 pF
-
©
74HC_HCT165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 1 September 2021
8 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
-
Max
Min
Max
Min
Max
tt
transition time Q7, Q7 output; see Fig. 7
VCC = 4.5 V
[2]
7
6
9
8
2
15
-
-
19
-
-
22 ns
tW
pulse width
CP input; see Fig. 7
VCC = 4.5 V
16
20
20
20
20
25
25
25
24
30
30
30
-
-
-
-
ns
ns
ns
ns
PL input; see Fig. 8
VCC = 4.5 V
-
-
trec
recovery time PL to CP, CE; see Fig. 8
VCC = 4.5 V
-
-
tsu
set-up time
DS to CP, CE; see Fig. 10
VCC = 4.5 V
-
-
CE to CP and CP to CE;
see Fig. 10
VCC = 4.5 V
Dn to PL; see Fig. 11
VCC = 4.5 V
20
20
7
-
-
25
25
-
-
30
30
-
-
ns
ns
10
th
hold time
DS to CP, CE and Dn to PL;
see Fig. 10
VCC = 4.5 V
7
0
-1
-7
-
-
9
0
-
-
11
0
-
-
ns
ns
CE to CP and CP to CE;
see Fig. 10
VCC = 4.5 V
fmax
maximum
frequency
CP input; see Fig. 7
VCC = 4.5 V
26
-
44
48
35
-
-
-
21
-
-
-
-
17
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
CPD
power
per package;
[3]
-
-
-
dissipation
capacitance
VI = GND to VCC - 1.5 V
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi + Σ (CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ (CL × VCC 2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
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74HC_HCT165
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Rev. 7 — 1 September 2021
9 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
11.1. Waveforms and test circuit
1/f
max
V
I
CP or CE input
V
M
GND
t
W
t
t
PHL
90 %
PLH
V
OH
90 %
V
Q7 or Q7 output
M
10 %
10 %
TLH
V
OL
t
t
THL
mna987
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
V
I
V
PL input
M
GND
t
t
rec
W
V
I
CE, CP input
V
M
GND
t
PHL
V
OH
V
Q7 or Q7 output
M
V
OL
mna988
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel
load to clock (CP) and clock enable (CE) recovery time
V
I
V
D7 input
M
GND
t
t
t
PLH
PHL
PLH
V
OH
V
V
Q7 output
Q7 output
M
M
V
OL
t
PHL
V
OH
V
OL
mna989
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
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Product data sheet
Rev. 7 — 1 September 2021
10 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
(1)
V
V
I
CP, CE input
M
GND
t
t
h
h
t
t
su
su
V
I
V
DS input
M
GND
t
su
t
W
V
I
V
CP, CE input
M
GND
mna990
(1) CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs,
from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable
input (CE)
V
I
V
V
M
Dn input
GND
M
t
su
t
t
t
h
h
su
V
I
PL input
GND
V
V
M
M
mna991
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8. Measurement points
Type
Input
VI
Output
VM
VM
74HC165
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT165
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74HC_HCT165
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Product data sheet
Rev. 7 — 1 September 2021
11 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig. 12. Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC165
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT165
open
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Product data sheet
Rev. 7 — 1 September 2021
12 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 13. Package outline SOT109-1 (SO16)
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74HC_HCT165
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Product data sheet
Rev. 7 — 1 September 2021
13 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 14. Package outline SOT403-1 (TSSOP16)
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74HC_HCT165
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Product data sheet
Rev. 7 — 1 September 2021
14 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
h
e
e
y
D
D
E
L
v
w
y
1
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig. 15. Package outline SOT763-1 (DHVQFN16)
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Product data sheet
Rev. 7 — 1 September 2021
15 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20210901 Product data sheet
Section 2 updated.
Type numbers 74HC165DB and 74HCT165DB (SOT338-1/SSOP16) removed.
Product data sheet 74HC_HCT165 v.5
Table 4: Derating values for Ptot total power dissipation updated.
20170821 Product data sheet 74HC_HCT165 v.4
Table 7: Hold time for 74HC165 has been updated.
Change notice Supersedes
74HC_HCT165 v.7
Modifications:
-
74HC_HCT165 v.6
•
•
74HC_HCT165 v.6
Modifications:
20200423
-
•
74HC_HCT165 v.5
Modifications:
-
•
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT165 v.4
Modifications:
20151228
Type numbers 74HC165N and 74HCT165N (SOT38-4) removed.
20080314 Product data sheet 74HC_HCT165_CNV v.2
Product data sheet
-
74HC_HCT165 v.3
•
74HC_HCT165 v.3
Modifications:
-
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Package SOT763-1 (DHVQFN16) added to Section 4 and Section 12.
Family data added, see Section 10
74HC_HCT165_CNV v.2
December
1990
Product specification
-
-
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74HC_HCT165
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Product data sheet
Rev. 7 — 1 September 2021
16 / 18
Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
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Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
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accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
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74HC_HCT165
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Product data sheet
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Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 4
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................5
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit.......................................10
12. Package outline........................................................ 13
13. Abbreviations............................................................16
14. Revision history........................................................16
15. Legal information......................................................17
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 1 September 2021
©
74HC_HCT165
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Product data sheet
Rev. 7 — 1 September 2021
18 / 18
相关型号:
74HCT165PW-Q100
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74HCT165PW-Q100,118
Parallel In Serial Out, HCT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16
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74HCT165PW-T
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