74HCT1G02GV-Q100 [NEXPERIA]
2-input NOR gateProduction;型号: | 74HCT1G02GV-Q100 |
厂家: | Nexperia |
描述: | 2-input NOR gateProduction 光电二极管 逻辑集成电路 |
文件: | 总10页 (文件大小:200K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC1G02-Q100;
74HCT1G02-Q100
2-input NOR gate
Rev. 2 — 21 January 2022
Product data sheet
1. General description
The 74HC1G02-Q100; 74HCT1G02-Q100 is a single 2-input NOR gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
Symmetrical output impedance
High noise immunity
Balanced propagation delays
Input levels:
•
•
For 74HC1G02-Q100: CMOS level
For 74HCT1G02-Q100: TTL level
•
•
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
-40 °C to +125 °C
Name
Description
Version
74HC1G02GW-Q100
74HCT1G02GW-Q100
74HC1G02GV-Q100
74HCT1G02GV-Q100
TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
-40 °C to +125 °C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
4. Marking
Table 2. Marking codes
Type number
Marking[1]
HB
74HC1G02GW-Q100
74HCT1G02GW-Q100
74HC1G02GV-Q100
74HCT1G02GV-Q100
TB
H02
T02
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
1
2
B
A
4
Y
≥ 1
4
Y
A
mna103
mna104
mna105
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
6. Pinning information
6.1. Pinning
74HC1G02
74HCT1G02
1
2
3
5
4
B
A
V
CC
GND
Y
001aaf085
Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
data input
B
A
2
data input
GND
Y
3
ground (0 V)
data output
supply voltage
4
VCC
5
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
2 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level
Inputs
Output
A
L
B
L
Y
H
L
L
L
L
H
L
H
H
H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±20
Unit
V
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
-0.5 V < VO < VCC + 0.5 V
[1]
[1]
[1]
[1]
-
mA
mA
IOK
-
-
IO
±12.5 mA
ICC
supply current
-
25
-
mA
mA
°C
IGND
Tstg
Ptot
ground current
-25
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT753 (SC-74A) package: Ptot derates linearly with 3.8 mW/K above 85 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC1G02-Q100
74HCT1G02-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
VI
supply voltage
input voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
4.5
5.0
5.5
VCC
VCC
V
V
V
0
0
-
0
0
-
VO
output voltage
ambient temperature
-
-
Tamb
Δt/ΔV
-40
-
+25
-40
-
+25
+125 °C
input transition rise and VCC = 2.0 V
fall rate
-
-
-
-
-
-
-
ns/V
VCC = 4.5 V
-
-
139 ns/V
VCC = 6.0 V
-
-
-
ns/V
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
3 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
10. Static characteristics
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C.
Symbol
Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
74HC1G02-Q100
VIH HIGH-level input
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
V
V
V
V
V
V
voltage
3.15
3.15
4.2
-
4.2
-
VIL
LOW-level input
voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output
voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
2.0
4.5
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -2.0 mA; VCC = 4.5 V
IO = -2.6 mA; VCC = 6.0 V
5.9
6.0
4.13
5.63
4.32
5.81
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 2.0 mA; VCC = 4.5 V
IO = 2.6 mA; VCC = 6.0 V
-
-
-
-
-
-
-
0
0.1
0.1
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
20
V
0
V
0
0.15
0.16
-
0.1
V
0.33
0.33
1.0
V
V
II
input leakage current VI = VCC or GND; VCC = 6.0 V
μA
μA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
10
CI
input capacitance
-
1.5
-
-
-
pF
74HCT1G02-Q100
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
V
V
VIL
LOW-level input
voltage
0.8
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = -20 μA; VCC = 4.5 V
IO = -2.0 mA; VCC = 4.5 V
VI = VIH or VIL
4.4
4.5
-
-
4.4
3.7
-
-
V
V
4.13
4.32
VOL
LOW-level output
voltage
IO = 20 μA; VCC = 4.5 V
IO = 2.0 mA; VCC = 4.5 V
-
-
-
-
0
0.1
0.33
1.0
-
-
-
-
0.1
0.4
1.0
20
V
0.15
V
II
input leakage current VI = VCC or GND; VCC = 5.5 V
-
-
μA
μA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
10
ΔICC
CI
additional supply
current
per input; VCC = 4.5 V to 5.5 V;
VI = VCC - 2.1 V; IO = 0 A
-
-
-
500
-
-
-
850
-
μA
pF
input capacitance
1.5
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
4 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
GND = 0 V; tr = tf ≤ 6.0 ns; All typical values are measured at Tamb = 25 °C. For test circuit see Fig. 6
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
74HC1G02-Q100
tpd
propagation delay A and B to Y; see Fig. 5
VCC = 2.0 V; CL = 50 pF
[1]
-
-
-
-
-
25
9
115
23
-
-
-
-
-
-
135
27
-
ns
ns
ns
ns
pF
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
7
VCC = 6.0 V; CL = 50 pF
8
20
-
23
-
CPD
power dissipation VI = GND to VCC
capacitance
[2]
[1]
18
74HCT1G02-Q100
tpd
propagation delay A and B to Y; see Fig. 5
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
-
-
-
11
9
24
-
-
-
-
27
-
ns
ns
pF
CPD
power dissipation VI = GND to VCC - 1.5 V
capacitance
[2]
19
-
-
[1] tpd is the same as tPLH and tPHL
.
[2] CPD is used to determine the dynamic power dissipation PD (μW).
PD = CPD × VCC 2 × fi + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
Σ(CL × VCC 2 × fo) = sum of outputs
11.1. Waveforms and test circuit
V
A, B input
Y output
M
V
CC
V
V
O
I
PULSE
GENERATOR
t
t
PHL
PLH
DUT
C
L
R
T
V
M
mna101
mna106
Test data is given in Table 8.
For 74HC1G02-Q100:
CL = Load capacitance including jig and probe
capacitance.
VM = 0.5xVCC; VI = GND to VCC
For 74HCT1G02-Q100:
RT = Termination resistance should be equal to
output impedance Zo of the pulse generator.
VM = 1.3 V; VI = GND to 3.0 V
Fig. 5. Input to output propagation delays
Fig. 6. Test circuit for measuring switching times
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
5 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
B
E
A
X
c
(5x)
y
H
E
v
M
A
e
1
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(5x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot353-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT353-1
SC-88A
MO-203
Fig. 7. Package outline SOT353-1 (TSSOP5)
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
6 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
b
e
w
M B
p
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
1
b
c
D
e
H
L
Q
v
w
y
E
p
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig. 8. Package outline SOT753 (SC-74A)
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
7 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
13. Abbreviations
Table 9. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 10. Revision history
Document ID
Release date
20220121
Data sheet status
Change notice Supersedes
74HC_HCT1G02_Q100 v.2
Modifications
Product data sheet
-
74HC_HCT1G02_Q100 v.1
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Table 5: Derating values for Ptot total power dissipation updated.
Fig. 7: Package outline drawing for SOT353-1 (TSSOP5) has changed.
74HC_HCT1G02_Q100 v.1
20120807
Product data sheet
-
-
©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
8 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
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data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
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©
74HC_HCT1G02_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
9 / 10
Nexperia
74HC1G02-Q100; 74HCT1G02-Q100
2-input NOR gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................2
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 5
12. Package outline.......................................................... 6
13. Abbreviations..............................................................8
14. Revision history..........................................................8
15. Legal information........................................................9
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 21 January 2022
©
74HC_HCT1G02_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 21 January 2022
10 / 10
相关型号:
74HCT1G02GW-G
IC HCT SERIES, 2-INPUT NOR GATE, PDSO5, 1.25MM, PLASTIC, MO-203, SOT353-1, SC-88A, 5 PIN, Gate
NXP
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