74HCT259D-Q100 [NEXPERIA]
8-bit addressable latchProduction;
| 型号： | 74HCT259D-Q100 |
| 厂家： | 
Nexperia |
| 描述： | 8-bit addressable latchProduction 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总17页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Rev. 2 — 2 September 2020
Product data sheet
1. General description
The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four
modes of operation. In the addressable latch mode, data on the D input is written into the latch
addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed
latches will retain their previous states. In memory mode, all latches retain their previous states and
are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs
are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
Wide supply voltage range from 2.0 V to 6.0 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
•
•
•
•
•
•
•
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Input levels:
•
•
For 74HC259-Q100: CMOS level
For 74HCT259-Q100: TTL level
•
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
•
•
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC259D-Q100
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT259D-Q100
74HC259PW-Q100
74HCT259PW-Q100
74HC259BQ-Q100
74HCT259BQ-Q100
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
SOT763-1
DHVQFN16 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 × 3.5 × 0.85 mm
4. Functional diagram
13
Z9
15
G8
14
G10
9,10D
1
DX
4
C10
8R
14
LE
0
1
2
3
0
2
5
6
4
5
0
7
1
2
3
4
5
6
7
Q0
G
13
D
Q1
Q2
Q3
Q4
Q5
Q6
Q7
6
7
7
9
1
2
3
9
A0
A1
A2
10
11
12
10
11
12
MR
15
mna573
mna572
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Q0
Q1
Q2
Q3
Q4
Q5
4
5
A0
A1
A2
1
2
3
6
1-of-8
DECODER
7
8 LATCHES
9
14 LE
10
15
13
Q6 11
12
MR
D
Q7
mna571
Fig. 3. Functional diagram
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
2 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
5. Pinning information
5.1. Pinning
74HC259
74HCT259
terminal 1
index area
2
3
4
5
6
7
15
14
13
12
11
10
A1
A2
Q0
Q1
Q2
Q3
MR
LE
D
74HC259
74HCT259
Q7
Q6
Q5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
V
CC
(1)
GND
MR
LE
D
A2
Q0
001aaj445
Q1
Q7
Q6
Q5
Q4
Q2
Transparent top view
Q3
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
GND
001aaj444
Fig. 4. Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16)
Fig. 5. Pin configuration SOT763-1 (DHVQFN16)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
A0, A1, A2
1, 2, 3
address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
4, 5, 6, 7, 9, 10, 11, 12
latch output
GND
D
8
ground (0 V)
13
14
15
16
data input
LE
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
MR
VCC
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
3 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Operating mode
Input
Output
A0 A1 A2 Q0
MR LE
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
d
Q1
Q2
L
Q3
L
Q4
L
Q5
L
Q6
L
Q7
L
Reset (clear)
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
X
L
X
L
L
L
Demultiplexer
(active HIGH 8-channel)
decoder (when D = H)
L
Q = d L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
q0
Q = d L
L
L
L
L
L
L
H
H
L
L
L
Q = d L
L
L
L
L
L
H
L
L
L
L
Q = d L
L
L
L
L
H
H
H
H
X
L
L
L
L
Q = d L
L
L
L
H
L
L
L
L
L
L
Q = d L
L
L
H
H
X
L
L
L
L
L
L
Q = d L
L
H
X
L
L
L
L
L
L
L
Q = d
Memory (no action)
Addressable latch
H
H
H
H
H
H
H
H
H
q1
q2
q2
q3
q3
q3
q4
q4
q4
q4
q5
q5
q5
q5
q5
q6
q6
q6
q6
q6
q6
q7
q7
q7
q7
q7
q7
q7
Q = d q1
H
L
L
L
q0
q0
q0
q0
q0
q0
q0
Q = d q2
H
H
L
L
q1
q1
q1
q1
q1
q1
Q = d q3
H
L
L
q2
q2
q2
q2
q2
Q = d q4
H
H
H
H
q3
q3
q3
q3
Q = d q5
H
L
L
q4
q4
q4
Q = d q6
H
H
q5
q5
Q = d q7
q6 Q = d
H
Table 4. Operating mode select table
H = HIGH voltage level; L = LOW voltage level.
LE
L
MR
H
Mode
Addressable latch mode
Memory mode
H
L
H
L
Demultiplexer mode
Reset mode
H
L
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
4 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7.0
±20
±20
±25
+70
-
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to VCC + 0.5 V
[1]
[1]
-
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-70
-65
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.
8. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC259-Q100
74HCT259-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
VI
supply voltage
input voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
4.5
5.0
5.5
VCC
VCC
V
V
V
0
0
-
0
0
-
VO
output voltage
ambient temperature
-
-
Tamb
Δt/ΔV
-40
-
-
-40
-
-
+125 °C
input transition rise and fall rate VCC = 2.0 V
-
1.67
-
-
1.67
-
-
ns/V
VCC = 4.5 V
VCC = 6.0 V
-
-
139 ns/V
-
-
-
ns/V
9. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC259-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
3.15 2.4
3.15
3.15
4.2
3.2
0.8
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
2.1 1.35
2.8 1.8
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
5 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Symbol Parameter
Conditions
25 °C
Min Typ Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4.0 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
5.9
3.98 4.32
5.48 5.81
3.84
5.34
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1
V
V
II
input leakage VI = VCC or GND; VCC = 6.0 V
current
-
±0.1
8.0
-
μA
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
-
-
80
-
-
-
160
-
μA
pF
input
3.5
capacitance
74HCT259-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = -4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
0
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
V
0.15 0.26
V
II
input leakage VI = VCC or GND; VCC = 5.5 V
current
-
±0.1
μA
ICC
ΔICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
μA
additional
VI = VCC - 2.1 V; IO = 0 A;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pin An, LE
pin D
-
-
-
-
150 540
120 432
-
-
-
-
675
540
338
-
-
-
-
-
735
588
368
-
μA
μA
μA
pF
pin MR
75
270
-
CI
input
3.5
capacitance
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
6 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 12.
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
74HC259-Q100
tpd
propagation
delay
D to Qn; see Fig. 6
VCC = 2.0 V
[2]
[2]
[2]
-
-
-
-
58
21
18
17
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
31
39
48
An to Qn; see Fig. 7
VCC = 2.0 V
-
-
-
-
58
21
17
17
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
31
39
48
LE to Qn; see Fig. 8
VCC = 2.0 V
-
-
-
-
55
20
17
16
170
34
-
-
-
-
-
215
43
-
-
-
-
-
255
51
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
29
37
43
tPHL
HIGH to LOW MR to Qn; see Fig. 9
propagation
delay
VCC = 2.0 V
-
-
-
-
50
18
15
14
155
31
-
-
-
-
-
195
39
-
-
-
-
-
235
47
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
transition time see Fig. 8
26
33
40
tt
[3]
VCC = 2.0 V
VCC = 4.5 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
119
22
ns
ns
ns
VCC = 6.0 V
6
19
tW
pulse width
LE HIGH or LOW; see Fig. 8
VCC = 2.0 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
18
MR LOW; see Fig. 9
VCC = 2.0 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
18
tsu
set-up time
D, An to LE;
see Fig. 10 and Fig. 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
7 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
th
hold time
D to LE; see Fig. 10
and Fig. 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
-19
-6
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
-5
An to LE; see Fig. 10
and Fig. 11
VCC = 2.0 V
2
2
2
-
-11
-4
-
-
-
-
2
2
2
-
-
-
-
-
2
2
2
-
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
-3
CPD
power
fi = 1 MHz; VI = GND to VCC [4]
19
dissipation
capacitance
74HCT259-Q100
tpd
propagation
delay
D to Qn; see Fig. 6
VCC = 4.5 V
[2]
[2]
[2]
-
-
23
20
39
-
-
-
49
-
-
-
59
-
ns
ns
VCC = 5.0 V; CL = 15 pF
An to Qn; see Fig. 7
VCC = 4.5 V
-
-
25
20
41
-
51
-
62
-
ns
ns
VCC = 5.0 V; CL = 15 pF
LE to Qn; see Fig. 8
VCC = 4.5 V
-
-
-
-
22
20
38
-
-
-
48
-
-
-
57
-
ns
ns
VCC = 5.0 V; CL = 15 pF
tPHL
HIGH to LOW MR to Qn; see Fig. 9
propagation
delay
VCC = 4.5 V
-
-
23
20
39
-
-
-
49
-
-
-
59
-
ns
ns
VCC = 5.0 V; CL = 15 pF
tt
transition time see Fig. 8
VCC = 4.5 V
[3]
-
7
15
-
-
19
-
-
22
-
ns
ns
ns
tW
pulse width
LE HIGH or LOW; see Fig. 8
VCC = 4.5 V
19
18
11
10
24
23
29
27
MR LOW; see Fig. 9
VCC = 4.5 V
-
-
-
tsu
set-up time
hold time
D, An to LE;
see Fig. 10 and Fig. 11
VCC = 4.5 V
17
0
10
-8
-4
-
-
-
21
0
-
-
-
26
0
-
-
-
ns
ns
ns
th
D to LE; see Fig. 10
and Fig. 11
VCC = 4.5 V
An to LE; see Fig. 10
and Fig. 11
VCC = 4.5 V
0
0
0
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74HC_HCT259_Q100
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Product data sheet
Rev. 2 — 2 September 2020
8 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
19
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
CPD
power
fi = 1 MHz;
[4]
-
-
-
-
-
-
pF
dissipation
capacitance
VI = GND to VCC - 1.5 V
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
[3] tt is the same as tTHL and tTLH
.
.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC 2 x fo) = sum of the outputs.
10.1. Waveforms and test circuit
V
CC
D input
V
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah123
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. Data input to output propagation delays
V
CC
V
M
An input
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah122
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. Address input to output propagation delays
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74HC_HCT259_Q100
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Product data sheet
Rev. 2 — 2 September 2020
9 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
V
CC
D input
GND
V
CC
V
M
LE input
GND
t
W
t
t
PLH
PHL
V
OH
V
Y
V
Qn output
M
V
X
V
OL
t
t
TLH
THL
001aaj446
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. Enable input to output propagation delays and pulse width
V
CC
MR input
V
M
GND
t
W
t
PHL
V
OH
V
Qn output
M
V
OL
001aah124
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. Master reset input to output propagation delays
V
CC
LE input
V
M
GND
t
t
su
su
t
t
h
h
V
CC
V
D input
M
GND
V
OH
V
Qn output
Q = D
Q = D
M
V
OL
001aah125
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 10. Data input to latch enable input set-up and hold times
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74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
10 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
V
CC
An input
LE input
V
ADDRESS STABLE
M
GND
t
t
h
su
V
CC
V
M
GND
001aah126
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 11. Address input to latch enable input set-up and hold times
Table 9. Measurement points
Type
Input
VM
Output
VM
VX
VY
74HC259-Q100
74HCT259-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig. 12. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC259-Q100
74HCT259-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
open
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74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
11 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 13. Package outline SOT109-1 (SO16)
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74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
12 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 14. Package outline SOT403-1 (TSSOP16)
©
74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
13 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
h
e
e
y
D
D
E
L
v
w
y
1
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig. 15. Package outline SOT763-1 (DHVQFN16)
©
74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
14 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
12. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT259_Q100 v.2 20200902
Product data sheet
-
74HC_HCT259_Q100 v.1
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Table 5: Derating values for Ptot total power dissipation have been updated.
74HC_HCT259_Q100 v.1 20120730
Product data sheet
-
-
©
74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
15 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
14. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74HC_HCT259_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
16 / 17
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 9
11. Package outline........................................................ 12
12. Abbreviations............................................................15
13. Revision history........................................................15
14. Legal information......................................................16
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 2 September 2020
©
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 2 September 2020
17 / 17
相关型号：
74HCT259D-T
IC HCT SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT-109, SOP-16, FF/Latch
NXP
74HCT259DB-T
IC HCT SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, 5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16, FF/Latch
NXP
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