74HCT2G02DC-Q100 [NEXPERIA]

Dual 2-input NOR gateProduction;


型号：	74HCT2G02DC-Q100
厂家：	Nexperia
描述：	Dual 2-input NOR gateProduction
文件：	总12页 (文件大小：210K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC2G02-Q100;

74HCT2G02-Q100

Dual 2-input NOR gate

Rev. 2 — 26 July 2018

Product data sheet

1. General description

The 74HC2G02-Q100; 74HCT2G02-Q100 is a dual 2-input NOR gate. Inputs include clamp

diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of

V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 2.0 V to 6.0 V

Input levels:

•

For 74HC2G02-Q100: CMOS level

For 74HCT2G02-Q100: TTL level

•

Symmetrical output impedance

High noise immunity

Complies with JEDEC standard no. 7A (4.5 V to 5.5 V)

Low power dissipation

Balanced propagation delays

Multiple package options

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC2G02DP-Q100

74HCT2G02DP-Q100

74HC2G02DC-Q100

74HCT2G02DC-Q100

-40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package;

8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

-40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package;

8 leads; body width 2.3 mm

SOT765-1

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

4. Marking

Table 2. Marking code

Type number

Marking code [1]

74HC2G02DP-Q100

74HCT2G02DP-Q100

74HC2G02DC-Q100

74HCT2G02DC-Q100

H02

T02

H02

T02

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

001aah780

001aah781

mna105

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

6. Pinning information

6.1. Pinning

74HC2G02-Q100

74HCT2G02-Q100

GND

aaa-009412

Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)

6.2. Pin description

Table 3. Pin description

Symbol

1A, 2A

1B, 2B

GND

1, 5

2, 6

Description

data input

ground (0 V)

data output

supply voltage

1Y, 2Y

V_CC

7, 3

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

2 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level.

Input

Output

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+7.0

±20

Unit

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to (V_CC+ 0.5 V)

[1]

°C

I_OK

I_O

I_CC

I_GND

T_stg

P_D

supply current

ground current

-50

-65

storage temperature

dynamic power dissipation

+150

300

T_amb= -40 °C to +125 °C

[2]

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP8 package: above 55 °C the value of P_totderates linearly with 2.5 mW/K.

For VSSOP8 package: above 110 °C the value of P_totderates linearly with 8 mW/K.

9. Recommended operating conditions

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

74HC2G02-Q100

74HCT2G02-Q100

Unit

Min

Typ

Max

Min

Typ

Max

5.5

V_CC

V_I

supply voltage

input voltage

2.0

5.0

6.0

V_CC

+125

625

139

4.5

5.0

V_CC

V_O

output voltage

ambient temperature

+25

T_amb

Δt/ΔV

-40

+125 °C

input transition

rise and fall rate

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

139

ns/V

1.67

ns/V

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

3 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

10. Static characteristics

Table 7. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to +85 °C

Typ [1]

-40 °C to +125 °C Unit

Min

Max

Min

Max

74HC2G02-Q100

V_IH

HIGH-level input V_CC= 2.0 V

1.5

1.2

2.4

3.2

0.8

2.1

2.8

1.5

voltage

V_CC= 4.5 V

3.15

V_CC= 6.0 V

4.2

V_IL

LOW-level input V_CC= 2.0 V

0.5

1.35

1.8

0.5

1.35

1.8

voltage

V_CC= 4.5 V

V_CC= 6.0 V

V_OH

HIGH-level output V_I= V_IHor V_IL

voltage

I_O= -20 μA; V_CC= 2.0 V

1.9

4.4

2.0

4.5

1.9

4.4

5.9

3.7

5.2

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4.0 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

5.9

6.0

4.13

5.63

4.32

5.81

V_OL

LOW-level output V_I= V_IHor V_IL

voltage

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

0.1

0.4

±1.0

0.1

0.15

0.16

0.33

±1.0

I_I

input leakage

current

μA

I_CC

C_I

supply current

per input pin; V_I= V_CCor GND;

I_O= 0 A; V_CC= 6.0 V

μA

input capacitance

1.5

74HCT2G02-Q100

V_IH

HIGH-level input V_CC= 4.5 V to 5.5 V

voltage

2.0

1.6

1.2

2.0

V_IL

LOW-level input V_CC= 4.5 V to 5.5 V

voltage

0.8

V_OH

HIGH-level output V_I= V_IHor V_IL

voltage

I_O= -20 μA; V_CC= 4.5 V

4.4

4.5

4.4

3.7

I_O= -4.0 mA; V_CC= 4.5 V

LOW-level output V_I= V_IHor V_IL

4.13

4.32

V_OL

voltage

I_O= 20 μA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 4.5 V

0.1

0.4

0.15

0.33

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

4 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C Unit

Min

Typ [1]

Max

Min

Max

I_I

input leakage

current

V_I= V_CCor GND; V_CC= 5.5 V

±1.0

μA

I_CC

ΔI_CC

C_I

supply current

V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

375

410

additional supply per input; V_CC= 4.5 V to 5.5 V;

current

V_I= V_CC- 2.1 V; I_O= 0 A

input capacitance

1.5

[1] All typical values are measured at T_amb= 25 °C.

11. Dynamic characteristics

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 6.

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C Unit

Min

Typ [1]

Max

Min

Max

74HC2G02-Q100

t_pd

propagation delay nA and nB to nY; see Fig. 5

[2]

[3]

V_CC= 2.0 V

110

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

t_t

transition time

see Fig. 5

V_CC= 2.0 V

125

V_CC= 4.5 V

V_CC= 6.0 V

C_PD

power dissipation V_I= GND to V_CC

capacitance

[4]

[2]

74HCT2G02-Q100

t_pd

propagation delay nA and nB to nY; see Fig. 5

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 4.5 V; see Fig. 5

t_t

transition time

[3]

[4]

C_PD

power dissipation V_I= GND to V_CC- 1.5 V

capacitance

[1] All typical values are measured at T_amb= 25 °C.

[2] t_pdis the same as t_PLHand t_PHL

[3] t_tis the same as t_TLHand t_THL

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of outputs.

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

5 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

11.1. Waveforms and test circuit

nA, nB input

GND

PHL

PLH

90%

nY output

10%

001aae759

TLH

THL

Measurement points are given in Table 9.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 5. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY)

Table 9. Measurement points

Type

Input

V_M

Output

V_M

74HC2G02-Q100

74HCT2G02-Q100

0.5 × V_CC

1.3 V

0.5 × V_CC

1.3 V

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

6 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

open

DUT

001aad983

Test data is given in Table 10.

Definitions for test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Type

Input

Load

S1 position

t_PHL, t_PLH

open

V_I

t_r, t_f

C_L

R_L

74HC2G02-Q100

74HCT2G02-Q100

GND to V_CC

GND to 3 V

≤ 6 ns

15 pF, 50 pF

1 kΩ

open

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

7 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

12. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

4.1

3.9

0.47

0.33

0.70

0.35

8°

0°

1.1

0.65

0.5

0.2

0.13

0.1

0.25

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

- - -

Fig. 7. Package outline SOT505-2 (TSSOP8)

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

8 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

(A )

pin 1 index

detail X

5 mm

scale

Dimensions (mm are the original dimensions)

(1)

(2)

(1)

Unit

max.

max

mm nom

min

0.15 0.85

0.00 0.60

0.27 0.23 2.1 2.4

0.17 0.08 1.9 2.2

3.2

3.0

0.40 0.21

0.15 0.19

0.4

8°

0°

0.12

0.5

0.4

0.2 0.08 0.1

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

sot765-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

07-06-02

16-05-31

SOT765-1

MO-187

Fig. 8. Package outline SOT765-1 (VSSOP8)

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

9 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

13. Abbreviations

Table 11. Abbreviations

Acronym

Description

CMOS

DUT

ESD

HBM

MIL

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Military

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 12. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74HC_HCT2G02_Q100 v.2 20180726

Product data sheet

74HC_HCT2G02_Q100 v.1

Modifications:

•

The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74HC_HCT2G02_Q100 v.1 20131111

Product data sheet

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

10 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

equipment, nor in applications where failure or malfunction of an Nexperia

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. Nexperia and its suppliers accept

no liability for inclusion and/or use of Nexperia products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

15. Legal information

Data sheet status

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Document status Product

Definition

[1][2]

status [3]

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

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Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

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and shall have no liability for the consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

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Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

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has been qualified for use in automotive applications. Unless otherwise

agreed in writing, the product is not designed, authorized or warranted to

be suitable for use in life support, life-critical or safety-critical systems or

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

11 / 12

Nexperia

74HC2G02-Q100; 74HCT2G02-Q100

Dual 2-input NOR gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Marking..........................................................................2

5. Functional diagram.......................................................2

6. Pinning information......................................................2

6.1. Pinning.........................................................................2

6.2. Pin description.............................................................2

7. Functional description................................................. 3

8. Limiting values............................................................. 3

9. Recommended operating conditions..........................3

10. Static characteristics..................................................4

11. Dynamic characteristics.............................................5

11.1. Waveforms and test circuit........................................ 6

12. Package outline.......................................................... 8

13. Abbreviations............................................................10

14. Revision history........................................................10

15. Legal information......................................................11

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 26 July 2018

74HC_HCT2G02_Q100

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Product data sheet

Rev. 2 — 26 July 2018

12 / 12

74HCT2G02DC-Q100 [NEXPERIA]

相关型号：

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74HCT2G02GD

74HCT2G02GD,125

74HCT2G04

74HCT2G04GV

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