74HCT573BQ [NEXPERIA]
Octal D-type transparent latch; 3-stateProduction;
| 型号： | 74HCT573BQ |
| 厂家： | 
Nexperia |
| 描述： | Octal D-type transparent latch; 3-stateProduction |
| 文件： | 总16页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 8 — 10 September 2021
Product data sheet
1. General description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device
features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs
enter the latches. In this condition the latches are transparent, a latch output will change each time
its corresponding D-input changes. When LE is LOW the latches store the information that was
present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC
.
2. Features and benefits
•
Wide supply voltage range from 2.0 to 6.0 V
•
•
•
CMOS low power dissipation
High noise immunity
Input levels:
•
•
For 74HC573: CMOS level
For 74HCT573: TTL level
•
•
•
•
•
•
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
•
•
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC573D
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HCT573D
74HC573PW
74HCT573PW
74HC573BQ
74HCT573BQ
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
SOT764-1
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
4. Functional diagram
2
3
4
5
6
7
8
9
19
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
18
17
16
15
14
13
12
LATCH
1 to 8
3-STATE
OUTPUTS
LE
11
1
OE
mna809
Fig. 1. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae075
Fig. 2. Logic diagram
11
C1
1
EN1
1
2
19
1D
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
3
4
5
6
7
18
17
16
15
14
Q1
Q2
Q3
Q4
Q5
Q6
Q7
8
9
13
12
LE
11
mna807
mna808
Fig. 3. Logic symbol
Fig. 4. IEC logic symbol
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
2 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1. Pinning
74HC573
74HCT573
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
74HC573
74HCT573
1
2
20
19
18
17
16
15
14
13
12
11
OE
D0
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
(1)
GND
3
D1
4
D2
5
D3
6
D4
001aae077
7
D5
8
D6
Transparent top view
9
D7
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
10
GND
001aae076
Fig. 5. Pin configuration SOT163-1 (SO20) and
SOT360-1 (TSSOP20)
Fig. 6. Pin configuration SOT764-1 (DHVQFN20)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
OE
1
3-state output enable input (active LOW)
data input
D0, D1, D2, D3, D4, D5, D6, D7
2, 3, 4, 5, 6, 7, 8, 9
GND
10
11
ground (0 V)
LE
latch enable input (active HIGH)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
VCC
19, 18, 17, 16, 15, 14, 13, 12
20
3-state latch output
supply voltage
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
3 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
Operating mode
Control
Input
Internal latches Output
Qn
OE
LE
Dn
L
H
l
Enable and read register
(transparent mode)
L
H
L
L
H
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Z
Latch register and disable outputs H
h
H
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to (VCC + 0.5 V)
-
±20
±20
±35
+70
-
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-70
-65
-
storage temperature
total power dissipation
+150
500
[1]
mW
[1] For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C.
For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C.
For SOT764-1 (DHVQFN20) package: Ptot derates linearly with 12.9 mW/K above 111 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC573
74HCT573
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
2.0
5.0
4.5
5.0
V
V
V
0
0
-
VCC
VCC
+125
625
139
83
0
0
-
VCC
VCC
VO
output voltage
ambient temperature
-
+25
-
-
+25
-
Tamb
Δt/ΔV
-40
-
-40
-
+125 °C
input transition rise and fall VCC = 2.0 V
rate
-
139
-
ns/V
VCC = 4.5 V
-
1.67
-
-
1.67
-
ns/V
ns/V
VCC = 6.0 V
-
-
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
4 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
74HC573
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
3.15
3.15
3.15
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VOH
HIGH-level
output voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -6.0 mA; VCC = 4.5 V
IO = -7.8 mA; VCC = 6.0 V
5.9
3.98 4.32
5.48 5.81
3.84
5.34
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
II
input leakage VI = VCC or GND; VCC = 6.0 V
current
-
±0.1
±0.5
8.0
-
±1.0 μA
±10.0 μA
160 μA
pF
IOZ
ICC
CI
OFF-state
output current VO = VCC or GND
VI = VIH or VIL; VCC = 6.0 V;
-
-
-
-
-
-
±5.0
80
-
-
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
input
3.5
capacitance
74HCT573
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = -6 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
0
0.1
-
-
0.1
-
-
0.1
0.4
V
V
IO = 6.0 mA
0.16 0.26
0.33
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
5 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
±1.0 μA
II
input leakage VI = VCC or GND; VCC = 5.5 V
current
-
-
±0.1
-
-
-
±1.0
±5.0
80
-
-
-
IOZ
ICC
ΔICC
OFF-state
output current VO = VCC or GND
VI = VIH or VIL; VCC = 5.5 V;
-
-
-
-
±0.5
8.0
±10 μA
160 μA
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
VI = VCC - 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
per input pin; Dn inputs
per input pin; LE input
per input pin; OE input
-
-
-
-
35
65
126
234
450
-
-
-
-
-
158
293
563
-
-
-
-
-
172 μA
319 μA
613 μA
125
3.5
CI
input
-
pF
capacitance
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 11.
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
74HC573
tpd
propagation
delay
Dn to Qn; see Fig. 7
VCC = 2.0 V
[1]
[1]
-
-
-
-
47
17
14
14
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225 ns
45 ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
-
26
33
38 ns
LE to Qn; see Fig. 8
VCC = 2.0 V
-
-
-
-
50
18
15
14
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225 ns
45 ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
-
ns
26
33
38 ns
ten
enable time
disable time
OE to Qn; see Fig. 9
VCC = 2.0 V
[2]
[3]
-
-
-
44
16
13
140
28
-
-
-
175
35
-
-
-
210 ns
42 ns
36 ns
VCC = 4.5 V
VCC = 6.0 V
24
30
tdis
OE to Qn; see Fig. 9
VCC = 2.0 V
-
-
-
55
20
16
150
30
-
-
-
190
38
-
-
-
225 ns
45 ns
38 ns
VCC = 4.5 V
VCC = 6.0 V
26
33
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
6 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Max
Min
Max
Min
Max
tt
transition time Qn; see Fig. 7
VCC = 2.0 V
[4]
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90 ns
VCC = 4.5 V
18 ns
15 ns
VCC = 6.0 V
4
tW
tsu
th
pulse width
set-up time
hold time
LE HIGH; see Fig. 8
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
Dn to LE; see Fig. 10
VCC = 2.0 V
50
10
9
11
4
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
Dn to LE; see Fig. 10
VCC = 2.0 V
5
5
5
-
3
1
-
-
-
-
5
5
5
-
-
-
-
-
5
5
5
-
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
1
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[5]
26
74HCT573
tpd
propagation
delay
Dn to Qn; see Fig. 7
VCC = 4.5 V
[1]
[1]
-
-
20
17
35
-
-
-
44
-
-
-
53 ns
ns
VCC = 5 V; CL = 15 pF
LE to Qn; see Fig. 8
VCC = 4.5 V
-
-
-
18
15
35
-
-
-
44
-
-
-
53 ns
ns
VCC = 5 V; CL = 15 pF
OE to Qn; see Fig. 9
VCC = 4.5 V
-
ten
tdis
tt
enable time
disable time
[2]
[3]
[4]
-
-
17
18
5
30
30
12
-
-
-
38
38
15
-
-
-
45 ns
45 ns
18 ns
OE to Qn; see Fig. 9
VCC = 4.5 V
transition time Qn; see Fig. 7
VCC = 4.5 V
-
-
-
tW
pulse width
LE HIGH; see Fig. 8
VCC = 4.5 V
16
5
20
24
-
ns
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
7 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Max
Min
Max
Min
Max
tsu
set-up time
hold time
Dn to LE; see Fig. 10
VCC = 4.5 V
13
7
-
16
-
20
-
ns
th
Dn to LE; see Fig. 10
VCC = 4.5 V
9
-
4
-
-
11
-
-
-
15
-
-
-
ns
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC - 1.5 V
[5]
26
pF
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of outputs.
10.1. Waveforms and test circuit
Dn input
V
M
t
t
PHL
PLH
90 %
V
Qn output
M
10 %
TLH
t
t
THL
001aae082
Measurement points are given in Table 8.
Fig. 7. Propagation delay data input (Dn) to output (Qn) and output transition time
LE input
V
M
t
W
t
t
PHL
PLH
90 %
V
Qn output
M
10 %
t
t
TLH
THL
001aae083
Measurement points are given in Table 8.
Fig. 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output
transition time
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
8 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
V
I
OE input
V
M
GND
t
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. Enable and disable times
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 10. Set-up and hold times for data input (Dn) to latch input (LE)
Table 8. Measurement points
Type
Input
VM
Output
VM
74HC573
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT573
©
74HC_HCT573
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
9 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig. 11. Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
Load
CL
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC573
VCC
3 V
15 pF, 50 pF 1 kΩ
15 pF, 50 pF 1 kΩ
74HCT573
open
GND
VCC
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
10 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
11. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig. 12. Package outline SOT163-1 (SO20)
©
74HC_HCT573
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
11 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig. 13. Package outline SOT360-1 (TSSOP20)
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
12 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
terminal 1
index area
e
C
1
v
w
C
C
A B
y
y
e
b
C
1
2
9
L
1
10
E
e
h
20
11
19
12
X
D
h
0
2.5
5 mm
scale
Dimensions (mm are the original dimensions)
(1) (1)
(1)
Unit
A
A
b
c
D
D
h
E
E
e
e
1
L
v
w
y
y
1
1
h
max 1.00 0.05 0.30
4.6 3.15 2.6 1.15
0.5
nom
min
mm
0.90 0.02 0.25 0.2 4.5 3.00 2.5 1.00 0.5 3.5 0.4 0.1 0.05 0.05 0.1
0.80 0.00 0.18 4.4 2.85 2.4 0.85 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot764-1_po
Issue date
References
Outline
version
European
projection
IEC
- - -
JEDEC
JEITA
- - -
03-01-27
14-12-12
SOT764-1
MO-241
Fig. 14. Package outline SOT764-1 (DHVQFN20)
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
13 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MM
Complementary Metal Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74HC_HCT573 v.8
Modifications:
20210910
Product data sheet
-
74HC_HCT573 v.7
•
•
•
Type numbers 74HC573DB and 74HCT573DB (SO339-1/SSOP20) removed.
Section 2 updated.
Section 7: Derating values for Ptot have been updated.
74HC_HCT573 v.7
Modifications:
20160304
Type numbers 74HC573N and 74HCT573N (SOT146-1) removed.
20150126 Product data sheet 74HC_HCT573 v.5
Table 7: Power dissipation capacitance condition for 74HCT573 is corrected.
Product data sheet
-
74HC_HCT573 v.6
•
74HC_HCT573 v.6
Modifications:
-
•
74HC_HCT573 v.5
Modifications:
20120815
Alternative descriptive title corrected (errata).
20120806 Product data sheet
Product data sheet
-
74HC_HCT573 v.4
•
74HC_HCT573 v.4
Modifications:
-
74HC_HCT573 v.3
•
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT573 v.3
20060117
19901201
Product data sheet
Product specification
-
-
74HC_HCT573_CNV v.2
-
74HC_HCT573_CNV v.2
©
74HC_HCT573
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
14 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
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with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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sold subject to the general terms and conditions of commercial sale, as
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concluded only the terms and conditions of the respective agreement shall
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customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
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Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
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Non-automotive qualified products — Unless this data sheet expressly
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In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
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and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
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product specifications.
Notwithstanding any damages that customer might incur for any reason
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for the products described herein shall be limited in accordance with the
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Suitability for use — Nexperia products are not designed, authorized or
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of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
15 / 16
Nexperia
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................4
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 6
10.1. Waveforms and test circuit........................................ 8
11. Package outline........................................................ 11
12. Abbreviations............................................................14
13. Revision history........................................................14
14. Legal information......................................................15
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 10 September 2021
©
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 10 September 2021
16 / 16
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