74LV02APW [NEXPERIA]

Quad 2-input NOR gateProduction;


型号：	74LV02APW
厂家：	Nexperia
描述：	Quad 2-input NOR gateProduction
文件：	总10页 (文件大小：187K)
中文：	中文翻译
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74LV02A

Quad 2-input NOR gate

Rev. 1 — 19 December 2018

Product data sheet

1. General description

The 74LV02A is a quad 2-input NOR gate.

Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed

voltage environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 5.5 V

•

Maximum t_pdof 10 ns at 5 V

Typical V_OL(p)< 0.8 V at V_CC= 3.3 V, T_amb= 25 °C

Typical V_OH(v)> 2.3 V at V_CC= 3.3 V, T_amb= 25 °C

Supports mixed-mode voltage operation on all ports

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 250 mA per JESD 78 Class II

ESD protection:

•

MM: MM JESD22-A115-B exceeds 200 V

HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV

•

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LV02APW

-40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

Nexperia

74LV02A

Quad 2-input NOR gate

4. Functional diagram

mna216

mna217

mna215

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74LV02A

GND

aaa-029452

Fig. 4. Pin configuration SOT402-1 (TSSOP14)

5.2. Pin description

Table 2. Pin description

Symbol

Description

data input

1A, 2A, 3A, 4A

1B, 2B, 3B, 4B

1Y, 2Y, 3Y, 4Y

GND

2, 5, 8, 11

3, 6, 9, 12

1, 4, 10, 13

data input

data output

ground (0 V)

supply voltage

V_CC

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

2 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

Input

Output

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

Max

+7.0

Unit

V_CC

V_I

supply voltage

input voltage

output voltage

[1]

+7.0

V_O

output HIGH or LOW state

[2]

[3]

V_CC+ 0.5

output power-down

V_I< 0 V

[2]

-0.5

-20

-50

+7.0

I_IK

input clamping current

output clamping current

output current

°C

I_OK

I_O

V_O< 0 V

V_O= 0 V to V_CC

±35

I_CC

I_GND

T_stg

P_tot

supply current

ground current

-70

-65

storage temperature

total power dissipation

+150

500

T_amb= -40 °C to +125 °C

[4]

[1] If the input current ratings are observed, the minimum input voltage ratings may be exceeded.

[2] If the output current ratings are observed, the output voltage ratings may be exceeded.

[3] This value is limited to 7 V maximum.

[4] For SOT402-1 package: above 116 °C, the value of P_totderates linearly at 7.3 mW/K.

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

3 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

2.0

Typ

Max

5.5

Unit

V_CC

V_I

supply voltage

input voltage

output voltage

5.0

5.5

V_O

output HIGH or LOW state

output power-down

V_CC

5.5

T_amb

ambient temperature

-40

+25

+125

200

100

°C

Δt/ΔV

input transition rise and fall rate

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

ns/V

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 2 V

1.5

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 2 V

0.7V_CC

V_IL

LOW-level

input voltage

0.5

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_I= V_IHor V_IL

0.3V_CC

V_OH

HIGH-level

output voltage

V_CC= 2.0 V to 5.5 V;

I_O= -50 μA

V_CC-0.1

V_CC= 2.3 V; I_O= -2 mA

V_CC= 3.0 V; I_O= -6 mA

V_CC= 4.5 V; I_O= -12 mA

V_I= V_IHor V_IL

2.48

3.8

2.48

3.8

2.48

3.8

V_OL

LOW-level

output voltage

V_CC= 2.0 V to 5.5 V;

I_O= 50 μA

0.1

V_CC= 2.3 V; I_O= 2 mA

V_CC= 3.0 V; I_O= 6 mA

V_CC= 4.5 V; I_O= 12 mA

V_Ior V_O= GND to 5.5 V;

0.4

0.44

0.55

0.5

0.4

0.44

0.55

0.4

0.44

0.55

I_OFF

I_I

power-off

μA

leakage current V_CC= 0 V

input leakage

current

V_I= V_CCor GND;

V_CC= 0 V to 5.5 V

±0.1

±1

μA

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

4 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6.

Symbol Parameter Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_pd

propagation nA, nB to nY; see Fig. 5

[2]

delay

V_CC= 2.3 V to 2.7 V

C_L= 15 pF

5.6 12.4

7.8 16.1

17.5 ns

21.5 ns

C_L= 50 pF

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

4.3

7.9

9.5

11.5 ns

C_L= 50 pF

6.0 11.4

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

3.3

4.8

5.5

7.5

6.5

8.5

C_L= 50 pF

C_I

input

V_I= V_CCor GND; V_CC= 3.3 V

capacitance

C_O

C_PD

output

capacitance

V_O= V_CCor GND; V_CC= 3.3 V

5.6

power

per buffer; C_L= 50 pF;

[3]

dissipation f = 10 MHz; V_I= GND to V_CC

capacitance

V_CC= 3.3 V

9.2

9.5

V_CC= 5.0 V

[1] Typical values are measured at T_amb= 25 °C and V_CC= 2.5 V, 3.3 V, and 5 V respectively, unless otherwise specified.

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PD× V_CC²× f_i× N + ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_L× V_CC²× f_o) = sum of outputs.

Table 8. Noise characteristics at T_amb= 25 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6.

Symbol Parameter

Conditions

Min

Typ

0.2

-0.1

3.1

Max

Unit

V_OL(p)

V_OL(v)

V_OH(v)

V_IH(AC)

V_IL(AC)

LOW-level output voltage (peak)

V_CC= 3.3 V; C_L= 50 pF

-0.8

0.8

LOW-level output voltage (valley)

HIGH-level output voltage (valley)

AC HIGH-level input voltage

AC LOW-level input voltage

2.31

0.99

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

5 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

10.1. Waveforms and test circuit

nA, nB input

GND

PHL

PLH

nY output

mna213

Measurement points are given in Table 9.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 5. Input (nA, nB) to output (nY) propagation delays

Table 9. Measurement points

Input

V_M

Output

V_M

0.5V_CC

90 %

negative

pulse

10 %

GND

90 %

positive

pulse

10 %

GND

DUT

001aah768

Test data is given in Table 10.

Definitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator

C_L= Load capacitance including jig and probe capacitance

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Input

Load

Test

V_I

t_r, t_f

C_L

GND to V_CC

3.0 ns

15 pF, 50 pF

t_PLH, t_PHL

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

6 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

11. Package outline

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig. 7. Package outline SOT402-1 (TSSOP14)

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

7 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

12. Abbreviations

Table 11. Abbreviations

Acronym

CDM

DUT

Description

Charge Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

To Be Determined

HBM

TBD

13. Revision history

Table 12. Revision history

Document ID

Release date

20181219

Data sheet status

Change notice

Supersedes

74LV02A v.1

Product data sheet

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

8 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

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suppliers accept no liability for inclusion and/or use of Nexperia products in

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14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

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Data sheet status

Document status Product

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Applications — Applications that are described herein for any of these

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or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

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data sheet

Development

This document contains data from

the objective specification for

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and products using Nexperia products, and Nexperia accepts no liability for

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Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

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data sheet

This document contains the product

specification.

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Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

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74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

9 / 10

Nexperia

74LV02A

Quad 2-input NOR gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................2

5.1. Pinning.........................................................................2

5.2. Pin description.............................................................2

6. Functional description................................................. 3

7. Limiting values............................................................. 3

8. Recommended operating conditions..........................4

9. Static characteristics....................................................4

10. Dynamic characteristics............................................ 5

10.1. Waveforms and test circuit........................................ 6

11. Package outline.......................................................... 7

12. Abbreviations..............................................................8

13. Revision history..........................................................8

14. Legal information........................................................9

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 19 December 2018

74LV02A

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Product data sheet

Rev. 1 — 19 December 2018

10 / 10

74LV02APW [NEXPERIA]

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