74LVC00AD [NEXPERIA]

Quad 2-input NAND gateProduction;


型号：	74LVC00AD
厂家：	Nexperia
描述：	Quad 2-input NAND gateProduction 光电二极管逻辑集成电路
文件：	总12页 (文件大小：230K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC00A

Quad 2-input NAND gate

Rev. 9 — 17 September 2021

Product data sheet

1. General description

The 74LVC00A is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices.

This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

2. Features and benefits

•

Overvoltage tolerant inputs to 5.5 V

•

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low-power consumption

Direct interface with TTL levels

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC00AD

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LVC00APW -40 °C to +125 °C

74LVC00ABQ -40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

SOT762-1

DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

Nexperia

74LVC00A

Quad 2-input NAND gate

4. Functional diagram

10 3B

12 4A

13 4B

4Y 11

mna212

mna246

mna211

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74LVC00A

terminal 1

index area

74LVC00A

(1)

GND

001aac939

Transparent top view

GND

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

001aac938

Fig. 4. Pin configuration for SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

1A to 4A

1B to 4B

1Y to 4Y

GND

Description

data input

1, 4, 9, 12

2, 5, 10, 13

3, 6, 8,11

data input

data output

ground (0 V)

supply voltage

V_CC

74LVC00A

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Product data sheet

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Nexperia

74LVC00A

Quad 2-input NAND gate

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level; X = don’t care

Input

Output

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

-0.5

-50

-0.5

Max

+6.5

Unit

supply voltage

input clamping current

input voltage

V_I< 0 V

V_I

[1]

[2]

+6.5

±50

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

output in HIGH or LOW-state

V_O= 0 V to V_CC

V_O

-0.5

V_CC+ 0.5 V

I_O

output current

±50

100

I_CC

supply current

°C

I_GND

P_tot

T_stg

ground current

-100

total power dissipation

storage temperature

T_amb= -40 °C to +125 °C

[3]

500

+150

-65

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SOT108-1 (SO14) package: P_totderates linearly with 10.1 mW/K above 100 °C.

For SOT402-1 (TSSOP14) package: P_totderates linearly with 7.3 mW/K above 81 °C.

For SOT762-1 (DHVQFN14) package: P_totderates linearly with 9.6 mW/K above 98 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol

Parameter

Conditions

Min

1.65

1.2

Typ

Max Unit

V_CC

supply voltage

3.6

functional

V_I

input voltage

5.5

V_CC

V_O

output voltage

output HIGH or LOW state

T_amb

Δt/ΔV

ambient temperature

-40

+125 °C

input transition rise and fall rate V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

ns/V

74LVC00A

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Product data sheet

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74LVC00A

Quad 2-input NAND gate

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

0.65V_CC

1.7

2.0

V_IL

LOW-level

input voltage

0.12

0.35V_CC

0.7

0.12

0.35V_CC

0.7

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.8

V_OH

HIGH-level

output voltage

I_O= -100 μA;

V_CC- 0.2

V_CC- 0.3

V_CC= 1.65 V to 3.6 V

I_O= -4 mA; V_CC= 1.65 V

I_O= -8 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.7 V

I_O= -18 mA; V_CC= 3.0 V

I_O= -24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

1.05

1.65

2.05

2.25

2.0

V_OL

LOW-level

output voltage

I_O= 100 μA;

0.2

0.3

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

0.45

0.6

0.65

0.8

0.4

0.6

0.55

±5

0.8

I_I

input leakage V_CC= 3.6 V; V_I= 5.5 V or GND

current

±0.1

±20

μA

I_CC

ΔI_CC

supply current V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

0.1

μA

additional

per input pin;

500

5000

supply current V_CC= 2.7 V to 3.6 V;

V_I= V_CC- 0.6 V; I_O= 0 A

C_I

input

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

4.0

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 °C.

74LVC00A

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Product data sheet

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Nexperia

74LVC00A

Quad 2-input NAND gate

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

t_pd

propagation delay nA, nB to nY; see Fig. 6

V_CC= 1.2 V

[2]

3.8

2.2

2.3

2.0

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

0.3

1.0

0.5

8.4

4.8

5.1

4.3

1.0

0.3

1.0

0.5

9.7

5.7

5.9

5.1

1.5

V_CC= 3.0 V to 3.6 V

t_sk(o)

C_PD

output skew time

V_CC= 3.0 V to 3.6 V

[3]

power dissipation

capacitance

per gate; V_I= GND to V_CC[4]

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

5.6

8.9

V_CC= 3.0 V to 3.6 V

11.8

[1] Typical values are measured at T_amb= 25 °C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PDx V_CC²x f_ix N + Σ(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

Σ(C_Lx V_CC²x f_o) = sum of the outputs

10.1. Waveforms and test circuit

nA, nB input

GND

PHL

PLH

nY output

mna213

V_M= 1.5 V at V_CC≥ 2.7 V.

V_M= 0.5 x V_CCat V_CC< 2.7 V.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 6. The input (nA, nB) to output (nY) propagation delays

74LVC00A

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Product data sheet

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Nexperia

74LVC00A

Quad 2-input NAND gate

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

PULSE

GENERATOR

DUT

001aaf615

Test data is given in Table 8. Definitions for test circuit:

R_L= Load resistance

C_L= Load capacitance including jig and probe capacitance

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator

Fig. 7. Test circuit for measuring switching times

Table 8. Test data

Supply voltage

Input

V_I

Load

C_L

t_r, t_f

R_L

1.2 V

V_CC

2.7 V

≤ 2 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

74LVC00A

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Product data sheet

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Nexperia

74LVC00A

Quad 2-input NAND gate

11. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

(A )

pin 1 index

detail X

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.75

1.27

0.05

1.05

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig. 8. Package outline SOT108-1 (SO14)

74LVC00A

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Product data sheet

Rev. 9 — 17 September 2021

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Nexperia

74LVC00A

Quad 2-input NAND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig. 9. Package outline SOT402-1 (TSSOP14)

74LVC00A

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Product data sheet

Rev. 9 — 17 September 2021

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Nexperia

74LVC00A

Quad 2-input NAND gate

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

detail X

terminal 1

index area

terminal 1

index area

C A

4 mm

scale

Dimensions (mm are the original dimensions)

(1) (1)

(1)

Unit

max

nom

min

0.05 0.30

0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5

0.00 0.18 2.9 1.35 2.4 0.85

3.1 1.65 2.6 1.15

0.5

0.4 0.1 0.05 0.05 0.1

0.2 0.3

Note

sot762-1_po

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

15-04-10

15-05-05

SOT762-1

MO-241

Fig. 10. Package outline SOT762-1 (DHVQFN14)

74LVC00A

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Product data sheet

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Nexperia

74LVC00A

Quad 2-input NAND gate

12. Abbreviations

Table 9. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged Device Model

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 10. Revision history

Document ID

74LVC00A v.9

Modifications:

Release date

20210917

Data sheet status

Change notice

Supersedes

Product data sheet

74LVC00A v.8

•

Type number 74LVC00ADB (SOT337-1/SSOP14) removed.

Section 1 updated.

74LVC00A v.8

Modifications:

20200824

Product data sheet

74LVC00A v.7

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Table 4: Derating values for P_tottotal power dissipation have been updated.

Package outline drawing of SOT762-1 (Fig. 10) updated.

74LVC00A v.7

Modifications:

20120425

Table 2: Errata in pin description corrected.

20120106 Product data sheet

Product data sheet

74LVC00A v.6

•

74LVC00A v.6

Modifications:

74LVC00A v.5

•

The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.

74LVC00A v.5

74LVC00A v.4

74LVC00A v.3

74LVC00A v.2

74LVC00A v.1

20030904

20030507

20020305

19980428

19970811

Product specification

74LVC00A v.4

74LVC00A v.3

74LVC00A v.2

74LVC00A v.1

74LVC00A

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Product data sheet

Rev. 9 — 17 September 2021

10 / 12

Nexperia

74LVC00A

Quad 2-input NAND gate

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

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sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

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customer.

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data sheet shall define the specification of the product as agreed between

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Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

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Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

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or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

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In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

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Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

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specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74LVC00A

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Product data sheet

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Nexperia

74LVC00A

Quad 2-input NAND gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................2

5.1. Pinning.........................................................................2

5.2. Pin description.............................................................2

6. Functional description................................................. 3

7. Limiting values............................................................. 3

8. Recommended operating conditions..........................3

9. Static characteristics....................................................4

10. Dynamic characteristics............................................ 5

10.1. Waveforms and test circuit........................................ 5

11. Package outline.......................................................... 7

12. Abbreviations............................................................10

13. Revision history........................................................10

14. Legal information......................................................11

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 17 September 2021

74LVC00A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 17 September 2021

12 / 12

74LVC00AD [NEXPERIA]

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