74LVC132ABQ-Q100 [NEXPERIA]
Quad 2-input NAND Schmitt triggerProduction;型号: | 74LVC132ABQ-Q100 |
厂家: | Nexperia |
描述: | Quad 2-input NAND Schmitt triggerProduction 逻辑集成电路 |
文件: | 总14页 (文件大小:241K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
Rev. 2 — 6 July 2020
Product data sheet
1. General description
The 74LVC132A-Q100 provides four 2-input NAND gates with Schmitt trigger inputs. It can
transform slowly changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference between
the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environment.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant inputs for interfacing with 5 V logic
CMOS low-power consumption
Direct interface with TTL levels
Unlimited input rise and fall times
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
•
•
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
3. Applications
•
•
•
Wave and pulse shapers for highly noisy environments
Astable multivibrator
Monostable multivibrator.
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC132AD-Q100
-40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
SOT402-1
SOT762-1
74LVC132APW-Q100 -40 °C to +125 °C
74LVC132ABQ-Q100 -40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 × 3 × 0.85 mm
5. Functional diagram
1
3
&
&
&
1
2
1A
1B
2
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
9
9
3A
8
10 3B
10
A
B
12 4A
13 4B
12
13
4Y 11
Y
11
&
mna212
mna246
001aac532
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram (one gate)
6. Pinning information
6.1. Pinning
74LVC132A-Q100
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1B
4B
4A
4Y
3B
3A
1Y
2A
2B
2Y
74LVC132A-Q100
GND(1)
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
2A
aaa-006926
2B
Transparent top view
2Y
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
GND
8
aaa-006925
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
Fig. 5. Pin configuration SOT762-1 (DHVQFN14)
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
2 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
data input
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
data input
data output
ground (0 V)
supply voltage
VCC
14
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
nA
L
nB
L
nY
H
L
H
L
H
H
H
H
H
L
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-0.5
-50
-
Max
+6.5
+6.5
Unit
V
VCC
VI
supply voltage
input voltage
[1]
[2]
V
VO
IIK
output voltage
VCC + 0.5 V
input clamping current
output clamping current
output current
VI < 0 V
-
mA
IOK
IO
VO > VCC or VO < 0 V
VO = 0 V to VCC
±50
±50
100
-
mA
mA
mA
mA
°C
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[3]
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
3 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
1.2
0
Typ
Max
3.6
-
Unit
V
VCC
supply voltage
-
-
-
-
-
functional
V
VI
input voltage
5.5
VCC
V
VO
output voltage
0
V
Tamb
ambient temperature
-40
+125 °C
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = -40 °C to +85 °C
VOH
HIGH-level output
voltage
VI = VT+ or VT-
IO = -100 μA; VCC = 1.65 V to 3.6 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -18 mA; VCC = 3.0 V
IO = -24 mA; VCC = 3.0 V
VI = VT+ or VT-
VCC - 0.2
VCC - 0.45
VCC - 0.5
VCC - 0.5
VCC - 0.6
VCC - 0.8
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VOL
LOW-level output
voltage
IO = 100 μA; VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
0.2
0.45
0.6
0.4
0.55
±5
V
-
V
-
-
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 5.5 V or GND
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
V
-
V
II
input leakage current
supply current
±0.1
0.1
5
μA
μA
μA
ICC
ΔICC
10
additional supply
current
per input pin; VCC = 2.7 V to 3.6 V;
VI = VCC - 0.6 V; IO = 0 A
500
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND to VCC
-
4.0
-
pF
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
4 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = -40 °C to +125 °C
VOH
HIGH-level output
voltage
VI = VT+ or VT-
IO = -100 μA; VCC = 1.65 V to 3.6 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -18 mA; VCC = 3.0 V
IO = -24 mA; VCC = 3.0 V
VI = VT+ or VT-
VCC - 0.3
VCC - 0.6
VCC - 0.65
VCC - 0.65
VCC - 0.75
VCC - 1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VOL
LOW-level output
voltage
IO = 100 μA; VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
±20
40
V
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 5.5 V or GND
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
V
V
II
input leakage current
supply current
μA
μA
mA
ICC
ΔICC
additional supply
current
per input pin; VCC = 2.7 V to 3.6 V;
VI = VCC - 0.6 V; IO = 0 A
5
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tpd
propagation delay nA, nB to nY; see Fig. 6
VCC = 1.2 V
[2]
-
18.0
7.2
4.0
3.8
3.4
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
2.0
1.5
1.5
1.5
-
12.8
7.6
7.6
6.4
1.0
2.0
1.5
1.5
1.5
-
16.0
9.6
9.6
8.0
1.5
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tsk(o)
CPD
output skew time
[3]
[4]
power dissipation per buffer; VI = GND to VCC
capacitance
VCC = 1.65 V to 1.95 V
-
-
-
10.5
10.8
11.4
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
N = number of inputs switching;
CL = output load capacitance in pF;
VCC = supply voltage in V;
Σ(CL × VCC 2 × fo) = sum of outputs.
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
5 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
11.1. Waveforms and test circuit
V
I
V
t
nA, nB input
GND
M
t
PHL
PLH
V
OH
V
nY output
M
mna213
V
OL
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. The input (nA, nB) to output (nY) propagation delays
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aaf615
Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig. 7. Test circuit for measuring switching times
Table 8. Test data
Supply voltage
Input
VI
Load
CL
tr, tf
RL
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
6 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
12. Transfer characteristics
Table 9. Transfer characteristics
Voltages are referenced to GND (ground = 0 V); see Fig. 8.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
0.2
0.4
0.6
0.8
0.9
1.1
1.2
1.2
0.12
0.15
0.25
0.4
0.4
0.8
0.8
0.8
0.1
0.2
0.2
0.3
0.3
0.3
0.3
0.3
Max
1.0
1.3
1.5
1.7
1.7
2
Min
0.2
0.4
0.6
0.8
0.9
1.1
1.2
1.2
0.12
0.15
0.25
0.4
0.4
0.8
0.8
0.8
0.1
0.2
0.2
0.3
0.3
0.3
0.3
0.3
Max
1.0
1.3
1.5
1.7
1.7
2
VT+
VT-
VH
positive-going threshold VCC = 1.2 V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
voltage
VCC = 1.65 V
VCC = 1.95 V
VCC = 2.3 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3 V
2
2
VCC = 3.6 V
2
2
negative-going threshold VCC = 1.2 V
0.75
0.85
0.95
1.1
1.2
1.4
1.5
1.5
1.0
1.15
1.25
1.3
1.3
1.1
1.2
1.2
0.75
0.85
0.95
1.1
1.2
1.4
1.5
1.5
1.0
1.15
1.25
1.3
1.3
1.1
1.2
1.2
voltage
VCC = 1.65 V
VCC = 1.95 V
VCC = 2.3 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3 V
VCC = 3.6 V
hysteresis voltage
(VT+ - VT-)
VCC = 1.2 V
VCC = 1.65 V
VCC = 1.95 V
VCC = 2.3 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 3 V
VCC = 3.6 V
[1]
[1] Typical transfer characteristic is displayed in Fig. 9.
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
7 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
12.1. Waveforms transfer characteristics
V
V
T+
O
V
I
V
H
V
T-
V
O
V
I
V
H
mna208
V
V
T+
T-
mna207
VT- at 20 % and VT+ at 70 %
Fig. 8. Definition of VT+, VT- and VH
mna582
5
I
CC
(mA)
4
3
2
1
0
0
0.6
1.2
1.8
2.4
3
V (V)
I
VCC = 3.3 V.
Fig. 9. Typical transfer characteristic
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
8 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
13. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig. 10. Package outline SOT108-1 (SO14)
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
9 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig. 11. Package outline SOT402-1 (TSSOP14)
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
10 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
E
D
A
A
1
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
v
w
C
C
A B
y
y
C
1
e
b
2
6
L
1
7
8
E
h
e
14
k
13
9
D
h
X
k
0
2
4 mm
w
scale
Dimensions (mm are the original dimensions)
(1) (1)
(1)
Unit
A
A
b
c
D
D
h
E
E
e
e
k
L
v
y
y
1
1
h
1
max
nom
min
1
0.05 0.30
0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5
0.00 0.18 2.9 1.35 2.4 0.85
3.1 1.65 2.6 1.15
0.5
0.4 0.1 0.05 0.05 0.1
0.2 0.3
mm
2
Note
sot762-1_po
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
15-04-10
15-05-05
SOT762-1
MO-241
Fig. 12. Package outline SOT762-1 (DHVQFN14)
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
11 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
14. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74LVC132A_Q100 v.2
Modifications:
20200706
Product data sheet
-
74LVC132A_Q100 v.1
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
Fig. 12: Package outline drawing SOT762-1 (DHVQFN14) updated.
74LVC132A_Q100 v.1
20130404
Product data sheet
-
-
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
12 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
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[1][2]
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©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
13 / 14
Nexperia
74LVC132A-Q100
Quad 2-input NAND Schmitt trigger
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 6
12. Transfer characteristics............................................. 7
12.1. Waveforms transfer characteristics............................8
13. Package outline.......................................................... 9
14. Abbreviations............................................................12
15. Revision history........................................................12
16. Legal information......................................................13
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 6 July 2020
©
74LVC132A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 6 July 2020
14 / 14
相关型号:
74LVC132AD-Q100
LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
NXP
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