74LVC163D_技术文档

74LVC163

Presettable synchronous 4-bit binary counter; synchronous

reset

Rev. 7 — 19 April 2021

Product data sheet

1. General description

The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead

carry and can be used for high-speed counting. Synchronous operation is provided by having all

flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins

Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel

enable input (pin PE) disables the counting action and causes the data at the data inputs (pins

D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the

set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at

count enable inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all

four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition

on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met).

This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset

feature enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin

CEP and CET) must be HIGH in count. The CET input is fed forward to enable the terminal count

output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration

approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next

cascaded stage.

The maximum clock frequency for the cascaded counters is determined by t_PHL(propagation delay

CP to TC) and t_su(set-up time CEP to CP) according to the formula:

.

2. Features and benefits

•

Wide supply voltage range from 1.2 V to 3.6 V

•

Inputs accept voltages up to 5.5 V

CMOS low power consumption

Direct interface with TTL levels

Synchronous reset

Synchronous counting and loading

Two count enable inputs for n-bit cascading

Positive edge-triggered clock

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

Specified from -40 °C to +85 °C and -40 °C to 125 °C

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC163D

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74LVC163PW -40 °C to +125 °C

74LVC163BQ -40 °C to +125 °C

TSSOP16

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

SOT763-1

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

4. Functional diagram

1

CTR4

R

9

7

M1

G3

G4

15

10

2

TC

14

13

12

11

3

4

5

6

9

D0

D1

D2

D3

PE

Q0

Q1

Q2

Q3

C2/1,3,4+

14

13

12

11

3

4

5

6

1,2D

CEP CET CP MR

15

4 CT = 15

mna905

1

7

10

2

mna906

Fig. 1. Logic diagram

Fig. 2. IEC logic symbol

3

4

5

6

D0 D1 D2 D3

PE

PARALLEL LOAD

CIRCUITRY

0

1

2

3

4

5

6

7

8

9

CET

10

15

14

13

12

TC

15

CEP

CP

7

2

1

BINARY

COUNTER

MR

Q0 Q1 Q2 Q3

14 13 12 11

11

10

9

mna907

mna908

Fig. 3. Functional diagram

Fig. 4. State diagram

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74LVC163

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Product data sheet

Rev. 7 — 19 April 2021

2 / 18

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74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

MR

PE

D0

D1

D2

D3

CP

CEP

CET

Q0

Q1

Q2

Q3

TC

12

13

14

15

0

1

2

RESET PRESET

COUNT

INHIBIT

mgu760

Typical timing sequence: Reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero,

one and two; inhibit.

Fig. 5. Timing sequence

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Product data sheet

Rev. 7 — 19 April 2021

3 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

D0

D1

D2

D3

CET

CEP

PE

MR

FF

1

FF

2

FF

3

FF

4

D

Q

D

Q

D

Q

D

Q

CP

Q0

Q1

Q2

Q3

TC

aaa-012189

Fig. 6. Logic diagram

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74LVC163

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Product data sheet

Rev. 7 — 19 April 2021

4 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

5. Pinning information

5.1. Pinning

74LVC163

terminal 1

index area

2

3

4

5

6

7

15

14

13

12

11

10

CP

D0

TC

Q0

Q1

Q2

Q3

CET

D1

74LVC163

D2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MR

CP

V

CC

D3

(1)

GND

TC

Q0

Q1

Q2

Q3

CET

PE

CEP

D0

D1

001aaa740

D2

D3

Transparent top view

CEP

GND

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

001aaa770

Fig. 7. Pin configuration for SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

Fig. 8. Pin configuration for SOT763-1 (DHVQFN16)

5.2. Pin description

Table 2. Pin description

Symbol

Description

MR

1

synchronous master reset (active LOW)

clock input (LOW-to-HIGH, edge-triggered)

data input

CP

2

D0, D1, D2, D3

3, 4, 5, 6

CEP

7

count enable input

GND

8

ground (0)

PE

9

parallel enable input (active LOW)

count enable carry input

flip-flop output

CET

10

Q0, Q1, Q2, Q3

14, 13, 12, 11

TC

15

16

terminal count output

supply voltage

V_CC

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Product data sheet

Rev. 7 — 19 April 2021

5 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

6. Functional description

Table 3. Functional table

* = the TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH);

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care; ↑ = LOW-to-HIGH clock transition.

Operating

modes

Input

Output

MR

l

CP

↑

CEP

CET

PE

X

l

Dn

X

l

Qn

L

TC

L

*

Reset (clear)

Parallel load

X

h

l

X

h

X

l

h

↑

L

h

↑

l

h

H

Count

h

↑

h

X

count

q_n

*

Hold (do nothing)

h

X

*

h

X

q_n

L

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

-0.5

-50

-0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

V_I

[1]

[2]

+6.5

±50

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

V_O= 0 V to V_CC

mA

V

V_O

-0.5

-

V_CC+ 0.5

±50

I_O

output current

mA

°C

I_CC

supply current

-

100

I_GND

T_stg

P_tot

ground current

-100

-65

-

storage temperature

total power dissipation

+150

500

T_amb= -40 °C to +125 °C

[3]

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

For SOT763-1 (DHVQFN16) package: P_totderates linearly with 11.2 mW/K above 106 °C.

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74LVC163

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Product data sheet

Rev. 7 — 19 April 2021

6 / 18

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74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

V

V_CC

supply voltage

-

functional

V

V_I

input voltage

5.5

V_CC

V

V_O

output voltage

0

V

T_amb

Δt/ΔV

ambient temperature

input transition rise and fall rate

in free air

-40

0

+125 °C

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

20

10

ns/V

0

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

-

1.08

-

V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

0.65 x V_CC

-

0.65 x V_CC

-

1.7

-

1.7

-

2.0

-

0.12

2.0

-

0.12

V_IL

LOW-level

input voltage

-

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35 x V_CC

0.7

0.35 x V_CC

0.7

0.8

V_OH

HIGH-level

output voltage

I_O= -100 μA;

V_CC- 0.2

-

V_CC- 0.3

-

V

V_CC= 1.65 V to 3.6 V

I_O= -4 mA; V_CC= 1.65 V

I_O= -8 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.7 V

I_O= -18 mA; V_CC= 3.0 V

I_O= -24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output voltage

I_O= 100 μA;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

-

0.45

0.6

-

0.65

0.8

V

-

V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

V_CC= 3.6 V; V_I= 5.5 V or GND

-

0.4

0.6

V

0.55

±5

0.8

V

I_I

input leakage

current

±0.1

±20

μA

I_CC

supply current V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.1

10

-

40

μA

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Product data sheet

Rev. 7 — 19 April 2021

7 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

ΔI_CC

additional

per input pin;

-

5

500

-

5000

μA

supply current V_CC= 2.7 V to 3.6 V;

V_I= V_CC- 0.6 V; I_O= 0 A

C_I

input

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

-

5.0

-

pF

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 °C.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 14.

Symbol Parameter

Conditions

-40 °C to +85 °C

Min Typ[1] Max

-40 °C to +125 °C Unit

Min

Max

t_pd

propagation delay CP to Qn; see Fig. 9

V_CC= 1.2 V

[2]

-

18

7.4

4.2

4.0

3.8

-

ns

V_CC= 1.65 V to 1.95 V

1.5

2.6

1.5

14.5

8.1

7.3

1.5

2.6

1.5

16.7

9.4

9.5

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

CP to TC; see Fig. 9

V_CC= 1.2 V

-

23

8.5

4.8

4.6

4.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.9

3.0

1.5

15.7

8.8

8.1

7.9

1.9

3.0

1.5

18.1

10.2

10.5

10.0

V_CC= 3.0 V to 3.6 V

CET to TC; see Fig. 10

V_CC= 1.2 V

-

16

6.3

3.6

3.9

3.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

2.3

1.5

12.7

7.1

6.9

6.4

1.5

2.3

1.5

14.6

8.2

9.0

8.0

V_CC= 3.0 V to 3.6 V

CP HIGH or LOW; see Fig. 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_W

pulse width

6.0

5.0

4.0

-

6.0

5.0

4.0

-

ns

-

V_CC= 3.0 V to 3.6 V

1.2

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Product data sheet

Rev. 7 — 19 April 2021

8 / 18

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74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

Symbol Parameter

Conditions

-40 °C to +85 °C

Min Typ[1] Max

-40 °C to +125 °C Unit

Min

Max

t_su

set-up time

Dn to CP; see Fig. 12

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

5.0

4.0

3.0

2.5

-

5.0

4.0

3.0

2.5

-

ns

-

V_CC= 3.0 V to 3.6 V

1.0

MR, PE to CP; see Fig. 11 and

Fig. 12

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

4.5

4.0

3.5

3.0

-

4.5

4.0

3.5

3.0

-

ns

-

V_CC= 3.0 V to 3.6 V

CEP, CET to CP; see Fig. 13

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.2

8.5

6.5

5.5

5.0

-

8.5

6.5

5.5

5.0

-

ns

-

V_CC= 3.0 V to 3.6 V

2.1

t_h

hold time

Dn, PE, CEP, CET to CP;

see Fig. 12 and Fig. 13

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

0.0

0.5

-

2.0

0.0

0.5

-

ns

-

V_CC= 3.0 V to 3.6 V

see Fig. 9

0.0

f_max

maximum

frequency

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

100

125

150

-

80

100

120

-

ns

-

ns

-

200

-

MHz

ns

V_CC= 3.0 V to 3.6 V

-

t_sk(o)

C_PD

output skew time V_CC= 3.0 V to 3.6 V

[3]

[4]

1.0

1.5

power dissipation per input; V_I= GND to V_CC

capacitance

V_CC= 1.65 V to 1.95 V

-

9.8

-

pF

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

13.4

16.6

[1] Typical values are measured at T_amb= 25 °C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PDx V_CC²x f_ix N + Σ(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in V

N = number of inputs switching

Σ(C_Lx V_CC²x f_o) = sum of outputs

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74LVC163

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Product data sheet

Rev. 7 — 19 April 2021

9 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

10.1. Waveforms and test circuit

1/f

max

V

I

CP input

V

M

GND

t

W

t

PHL

PLH

V

OH

V

M

Qn, TC output

V

OL

mgu762

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 9. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency

V

I

CET input

GND

V

M

V

M

t

PLH

PHL

V

OH

V

M

TC output

M

V

OL

mgu763

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 10. Input (CET) to output (TC) propagation delays

V

I

V

M

MR input

GND

M

t

h

t

su

V

I

CP input

V

M

GND

mgu764

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 11. The master reset (MR) set-up and hold times

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Product data sheet

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10 / 18

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74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

V

I

PE input

CP input

Dn input

V

M

GND

t

su

t

h

V

I

V

M

GND

t

su

t

h

V

I

V

M

GND

mgu765

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 12. Set-up and hold times for the input (Dn) and parallel enable input (PE)

V

I

V

M

CEP, CET input

M

GND

t

h

su

h

su

V

I

CP input

V

M

GND

mgu766

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 13. CEP and CET set-up and hold times

Table 8. Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

1.2 V

V_CC

2.7 V

0.5 x V_CC

1.5 V

0.5 x V_CC

1.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

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Product data sheet

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11 / 18

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74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

O

I

PULSE

GENERATOR

DUT

R

T

C

L

R

L

001aaf615

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

Fig. 14. Test circuit for measuring switching times

Table 9. Test data

Supply voltage

Input

V_I

Load

C_L

t_r, t_f

R_L

1.2 V

V_CC

2.7 V

≤ 2 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

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Product data sheet

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12 / 18

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74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

11. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 15. Package outline SOT109-1 (SO16)

©

74LVC163

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 19 April 2021

13 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 16. Package outline SOT403-1 (TSSOP16)

©

74LVC163

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Product data sheet

Rev. 7 — 19 April 2021

14 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

1

b

c

E

h

e

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig. 17. Package outline SOT763-1 (DHVQFN16)

©

74LVC163

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 19 April 2021

15 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

12. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

74LVC163 v.7

Modifications:

Release date

20210419

Data sheet status

Change notice

Supersedes

Product data sheet

-

74LVC163 v.6

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Type number 74LVC163DB (SOT338-1/SSOP16) removed.

Section 7: Derating values for P_tottotal power dissipation have been updated.

74LVC163 v.6

Modifications:

20121120

Product data sheet

-

74LVC163 v.5

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage

ranges.

74LVC163 v.5

74LVC163 v.4

74LVC163 v.3

74LVC163 v.2

74LVC163 v.1

20040505

20030602

20030509

19980520

19960823

Product specification

-

74LVC163 v.4

74LVC163 v.3

74LVC163 v.2

74LVC163 v.1

-

©

74LVC163

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 19 April 2021

16 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

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Product data sheet

Rev. 7 — 19 April 2021

17 / 18

Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................2

4. Functional diagram.......................................................2

5. Pinning information......................................................5

5.1. Pinning.........................................................................5

5.2. Pin description.............................................................5

6. Functional description................................................. 6

7. Limiting values............................................................. 6

8. Recommended operating conditions..........................7

9. Static characteristics....................................................7

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit...................................... 10

11. Package outline........................................................ 13

12. Abbreviations............................................................16

13. Revision history........................................................16

14. Legal information......................................................17

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 19 April 2021

©

74LVC163

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 19 April 2021

18 / 18


型号：	74LVC163D
厂家：	Nexperia
描述：	Presettable synchronous 4-bit binary counter; synchronous resetProduction 光电二极管逻辑集成电路
文件：	总18页 (文件大小：290K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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