74LVC1G32GW-Q100 [NEXPERIA]
Single 2-input OR gateProduction;型号: | 74LVC1G32GW-Q100 |
厂家: | Nexperia |
描述: | Single 2-input OR gateProduction 光电二极管 逻辑集成电路 |
文件: | 总12页 (文件大小:212K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC1G32-Q100
Single 2-input OR gate
Rev. 6 — 18 January 2022
Product data sheet
1. General description
The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or
5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V
environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and
fall times. This device is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through the
device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
IOFF circuitry provides partial Power-down mode operation
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Complies with JEDEC standard:
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
•
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G32GW-Q100 -40 °C to +125 °C
TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G32GV-Q100 -40 °C to +125 °C
74LVC1G32GM-Q100 -40 °C to +125 °C
SC-74A
XSON6
plastic surface-mounted package; 5 leads
SOT753
SOT886
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
4. Marking
Table 2. Marking
Type number
Marking code [1]
74LVC1G32GW-Q100
74LVC1G32GV-Q100
74LVC1G32GM-Q100
VG
V32
VG
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
1
2
B
A
≥1
4
Y
4
Y
A
mna164
mna165
mna166
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
6. Pinning information
6.1. Pinning
74LVC1G32
74LVC1G32
B
A
1
2
3
6
5
4
V
CC
1
2
3
5
4
B
A
V
CC
n.c.
Y
GND
GND
Y
001aab641
Transparent top view
001aab640
Fig. 4. Pin configuration SOT353-1 (TSSOP5) and
SOT753 (SC-74A)
Fig. 5. Pin configuration SOT886 (XSON6)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
Description
TSSOP5 and SC-74A
XSON6
B
1
2
3
4
-
1
2
3
4
5
6
data input
A
data input
GND
Y
ground (0 V)
data output
not connected
supply voltage
n.c.
VCC
5
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74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
2 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
A
L
B
L
Y
L
L
H
L
H
H
H
H
H
H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+6.5
±50
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1]
[1]
-0.5
-0.5
-
VCC + 0.5
+6.5
±50
Power-down mode; VCC = 0 V
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
mW
°C
ICC
IGND
Ptot
Tstg
supply current
-
100
ground current
-100
-
-
total power dissipation
storage temperature
Tamb = -40 °C to +125 °C
[2]
250
-65
+150
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT753 (SC-74A) package: Ptot derates linearly with 3.8 mW/K above 85 °C.
For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
1.65
-
-
-
-
-
-
-
0
0
5.5
V
VO
Active mode
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
-
+125
20
°C
ns/V
ns/V
Δt/ΔV
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
10
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74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
3 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
Typ [1]
-40 °C to +125 °C
Unit
Min
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
0.65 × VCC
-
V
V
V
V
V
V
V
V
1.7
-
1.7
-
2.0
-
2.0
-
0.7 × VCC
-
0.7 × VCC
-
VIL
LOW-level input VCC = 1.65 V to 1.95 V
voltage
-
-
-
-
0.35 × VCC
0.7
-
-
-
-
0.35 × VCC
0.7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.8
0.8
0.3 × VCC
0.3 × VCC
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -100 μA;
VCC - 0.1
-
-
VCC - 0.1
-
V
VCC = 1.65 V to 5.5 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -24 mA; VCC = 3.0 V
IO = -32 mA; VCC = 4.5 V
VI = VIH or VIL
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output voltage
IO = 100 μA;
-
-
0.10
-
0.10
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
-
0.45
0.30
0.40
0.55
0.55
±1
-
-
-
-
-
-
0.70
0.45
0.60
0.80
0.80
±1
V
-
V
-
V
-
-
V
V
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
±0.1
μA
IOFF
ICC
ΔICC
CI
power-off
leakage current
VCC = 0 V; VI or VO = 5.5 V
-
-
-
-
±0.1
0.1
5
±2
4
-
-
-
-
±2
4
μA
μA
μA
pF
supply current VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
additional
per pin; VCC = 2.3 V to 5.5 V;
500
-
500
-
supply current VI = VCC - 0.6 V; IO = 0 A
input
VCC = 3.3 V; VI = GND to VCC
5
capacitance
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
4 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tpd
propagation delay
A, B to Y; see Fig. 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[2]
1.0
0.5
0.5
0.5
0.5
-
3.1
2.1
2.5
2.1
1.7
16
8.0
5.5
5.5
4.5
4.0
-
1.0
0.5
0.5
0.5
0.5
-
10.5
7.0
7.0
6.0
5.5
-
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation
capacitance
VI = GND to VCC; VCC = 3.3 V [3]
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = (CPD × VCC 2 × fi × N) + (CL × VCC 2 × fo) where:
VCC = supply voltage in V;
fi = input frequency in MHz;
N = number of inputs switching;
CL = output load capacitance in pF;
fo = output frequency in MHz.
11.1. Waveforms and test circuit
V
I
V
A, B input
GND
M
t
t
PHL
PLH
V
OH
V
Y output
M
mna615
V
OL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. The input A, B to output Y propagation delays
Table 9. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
5 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance; should be equal to the output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Fig. 7. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
6 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
B
E
A
X
c
(5x)
y
H
E
v
M
A
e
1
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(5x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot353-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT353-1
SC-88A
MO-203
Fig. 8. Package outline SOT353-1 (TSSOP5)
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
7 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
b
e
w
M B
p
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
1
b
c
D
e
H
L
Q
v
w
y
E
p
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig. 9. Package outline SOT753 (SC-74A)
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
8 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
e
1
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
b
D
E
e
e
L
L
1
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.30 0.35
0.27 0.32
nom
min
0.20 1.45 1.00 0.6
0.17 1.40 0.95
mm
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Fig. 10. Package outline SOT886 (XSON6)
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
9 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
20220118 Product data sheet
Fig. 8: Package outline drawing SOT353-1 (TSSOP5) has changed.
20210518 Product data sheet 74LVC1G32_Q100 v.4
Section 1 and Section 2 updated.
Table 5: Derating values for Ptot total power dissipation updated.
Change notice Supersedes
74LVC1G32_Q100 v.6
Modifications:
- 74LVC1G32_Q100 v.5
•
74LVC1G32_Q100 v.5
Modifications:
-
•
•
74LVC1G32_Q100 v.4
Modifications:
20190125
Added type number 74LVC1G32GM-Q100 (SOT886)
20180817 Product data sheet
Product data sheet
-
74LVC1G32_Q100 v.3
•
74LVC1G32_Q100 v.3
Modifications:
-
74LVC1G32_Q100 v.2
•
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74LVC1G32_Q100 v.2
Modifications:
20161209
Table 7: The maximum limits for leakage current and supply current have changed.
20120807 Product data sheet
Product data sheet
-
74LVC1G32_Q100 v.1
•
74LVC1G32_Q100 v.1
-
-
©
74LVC1G32_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
10 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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Definition
[1][2]
status [3]
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data sheet
Development
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the objective specification for
product development.
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data sheet
Qualification
Production
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the preliminary specification.
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Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
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[2] The term 'short data sheet' is explained in section "Definitions".
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
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Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74LVC1G32_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
11 / 12
Nexperia
74LVC1G32-Q100
Single 2-input OR gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................2
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 5
12. Package outline.......................................................... 7
13. Abbreviations............................................................10
14. Revision history........................................................10
15. Legal information......................................................11
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 18 January 2022
©
74LVC1G32_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 6 — 18 January 2022
12 / 12
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