74LVC1G86GW-Q100 [NEXPERIA]

2-input EXCLUSIVE-OR gate;
74LVC1G86GW-Q100
型号: 74LVC1G86GW-Q100
厂家: Nexperia    Nexperia
描述:

2-input EXCLUSIVE-OR gate

光电二极管 逻辑集成电路 石英晶振
文件: 总13页 (文件大小:183K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
Rev. 3 — 7 March 2017  
Product data sheet  
1 General description  
The 74LVC1G86-Q100 provides the 2-input EXCLUSIVE-OR function.  
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of  
these devices in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial Power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the  
device when it is powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2 Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2 000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
3 Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature  
range  
Name  
Description  
Version  
74LVC1G86GW-Q100 -40 °C to +125 °C  
TSSOP5 plastic thin shrink small outline package; 5 leads;  
body width 1.25 mm  
SOT353-1  
SOT753  
74LVC1G86GV-Q100  
-40 °C to +125 °C  
SC-74A plastic surface-mounted package; 5 leads  
4 Marking  
Table 2. Marking codes  
Type number  
Marking [1]  
VH  
74LVC1G86GW-Q100  
74LVC1G86GV-Q100  
V86  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
5 Functional diagram  
B
B
A
Y
1
2
Y
1
2
4
= 1  
4
A
mna038  
mna039  
mna040  
Figure 1. Logic symbol  
Figure 2. IEC logic symbol  
Figure 3. Logic diagram  
6 Pinning information  
6.1 Pinning  
74LVC1G86-Q100  
1
2
3
5
B
A
V
Y
CC  
4
GND  
aaa-009532  
Figure 4. Pin configuration SOT353-1 and SOT753  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
2 / 13  
 
 
 
 
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
6.2 Pin description  
Table 3. Pin description  
Symbol  
Pin  
1
Description  
data input  
B
A
2
data input  
GND  
Y
3
ground (0 V)  
data output  
supply voltage  
4
VCC  
5
7 Functional description  
Table 4. Function table [1]  
Input  
Output  
A
L
B
L
Y
L
L
H
L
H
H
L
H
H
H
[1] H = HIGH voltage level;  
L = LOW voltage level  
8 Limiting values  
Table 5. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
-0.5  
-50  
-0.5  
-
Max  
+6.5  
-
Unit  
V
VCC  
IIK  
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
[1]  
VI  
+6.5  
±50  
IOK  
VO  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
Active mode  
mA  
V
[1] [2]  
[1] [2]  
-0.5  
-0.5  
-
VCC + 0.5  
+6.5  
±50  
Power-down mode  
VO = 0 V to VCC  
V
IO  
output current  
mA  
mA  
mA  
mW  
°C  
ICC  
IGND  
Ptot  
Tstg  
supply current  
-
+100  
-
ground current  
-100  
-
[3]  
total power dissipation  
storage temperature  
Tamb = -40 °C to +125 °C  
250  
-65  
+150  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
3 / 13  
 
 
 
 
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
9 Recommended operating conditions  
Table 6. Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
5.5  
Unit  
V
VCC  
VI  
supply voltage  
input voltage  
output voltage  
1.65  
-
-
-
-
-
-
-
0
0
5.5  
V
VO  
Active mode  
VCC  
5.5  
V
VCC = 0 V; Power-down mode  
0
V
Tamb  
ambient temperature  
-40  
-
+125  
20  
°C  
Δt/ΔV  
input transition rise and fall rate VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
ns/V  
ns/V  
-
10  
10 Static characteristics  
Table 7. Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
-40 °C to +125 °C Unit  
Min  
Typ [1]  
Max  
Min  
Max  
VIH  
HIGH-level input VCC = 1.65 V to 1.95 V  
0.65VCC  
-
-
-
-
-
-
-
-
-
0.65VCC  
-
V
V
V
V
V
V
V
V
voltage  
VCC = 2.3 V to 2.7 V  
1.7  
-
1.7  
-
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
2.0  
-
-
2.0  
-
-
0.7VCC  
0.7VCC  
VIL  
LOW-level input VCC = 1.65 V to 1.95 V  
-
-
-
-
0.35VCC  
0.7  
-
-
-
-
0.35VCC  
0.7  
voltage  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.8  
0.8  
0.3VCC  
0.3VCC  
VOH  
HIGH-level  
VI = VIH or VIL  
output voltage  
IO = -100 μA;  
VCC - 0.1  
-
-
VCC - 0.1  
-
V
VCC = 1.65 V to 5.5 V  
IO = -4 mA; VCC = 1.65 V  
IO = -8 mA; VCC = 2.3 V  
IO = -12 mA; VCC = 2.7 V  
IO = -24 mA; VCC = 3.0 V  
IO = -32 mA; VCC = 4.5 V  
1.2  
1.9  
2.2  
2.3  
3.8  
-
-
-
-
-
-
-
-
-
-
0.95  
1.7  
1.9  
2.0  
3.4  
-
-
-
-
-
V
V
V
V
V
VOL  
LOW-level output VI = VIH or VIL  
voltage  
IO = 100 μA;  
-
-
0.10  
-
0.10  
V
VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
-
-
-
-
-
-
0.45  
0.30  
0.40  
-
-
-
0.70  
0.45  
0.60  
V
V
V
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
4 / 13  
 
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
-40 °C to +125 °C Unit  
Min  
Typ [1]  
Max  
0.55  
0.55  
±1  
Min  
Max  
0.80  
0.80  
±1  
IO = 24 mA; VCC = 3.0 V  
-
-
-
-
-
-
-
-
V
IO = 32 mA; VCC = 4.5 V  
V
II  
input leakage  
current  
VI = 5.5 V or GND;  
VCC = 0 V to 5.5 V  
±0.1  
μA  
IOFF  
ICC  
power-off  
leakage current  
VCC = 0 V; VI or VO = 5.5 V  
-
-
-
±0.1  
0.1  
5
±2  
4
-
-
-
±2  
4
μA  
μA  
μA  
supply current  
VI = 5.5 V or GND; IO = 0 A;  
VCC = 1.65 V to 5.5 V  
ΔICC  
additional supply per pin; VCC = 2.3 V to 5.5 V;  
500  
500  
current  
VI = VCC - 0.6 V; IO = 0 A  
CI  
input  
VCC = 3.3 V; VI = GND to VCC  
-
5
-
-
-
pF  
capacitance  
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.  
11 Dynamic characteristics  
Table 8. Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
Min  
Typ [1] Max  
-40 °C to +125 °C Unit  
Min  
Max  
[2]  
tpd  
propagation delay  
A, B to Y; see Figure 5  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
0.5  
0.5  
0.5  
0.5  
3.7  
2.5  
2.8  
2.3  
1.9  
9.9  
5.5  
5.8  
5.0  
4.0  
1.0  
0.5  
0.5  
0.5  
0.5  
13.0  
7.0  
7.5  
6.5  
5.5  
ns  
ns  
ns  
ns  
ns  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VI = GND to VCC  
VCC = 3.3 V  
[3]  
CPD  
power dissipation  
capacitance  
-
25  
-
-
-
pF  
[1] All typical values are measured at nominal VCC  
.
[2] tpd is the same as tPLH and tPHL  
[3] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
5 / 13  
 
 
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
11.1 Waveforms and test circuit  
V
M
A, B input  
t
t
PHL  
PLH  
V
Y output  
M
mna041  
Measurement points are given in Table 9.  
VOL and VOH are typical output voltage levels that occur with the output.  
Figure 5. The input A and B to output Y propagation delay times  
Table 9. Measurement points  
Supply voltage  
VCC  
Input  
VM  
Output  
VM  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5VCC  
0.5VCC  
1.5 V  
0.5VCC  
0.5VCC  
1.5 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
1.5 V  
0.5VCC  
0.5VCC  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
6 / 13  
 
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
V
EXT  
V
CC  
R
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
mna616  
Test data is given in Table 10.  
Definitions test circuit:  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
CL = Load capacitance including jig and probe capacitance.  
RL = Load resistance.  
VEXT = External voltage for measuring switching times.  
Figure 6. Test circuit for measuring switching times  
Table 10. Test data  
Supply voltage Input  
Load  
VEXT  
VCC  
VI  
tr = tf  
CL  
RL  
tPLH, tPHL  
open  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
≤ 2.0 ns  
≤ 2.0 ns  
≤ 2.5 ns  
≤ 2.5 ns  
≤ 2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
open  
open  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
open  
open  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
7 / 13  
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
12 Package outline  
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm  
SOT353-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )  
3
A
1
θ
L
L
p
1
3
e
w
M
b
p
detail X  
e
1
0
1.5  
3 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT  
θ
v
w
y
Z
1
2
3
p
E
max.  
0.1  
0
1.0  
0.8  
0.30  
0.15  
0.25  
0.08  
2.25  
1.85  
1.35  
1.15  
2.25  
2.0  
0.46  
0.21  
0.60  
0.15  
7°  
0°  
mm  
1.1  
0.65  
1.3  
0.425  
0.3  
0.1  
0.1  
0.15  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-09-01  
03-02-19  
SOT353-1  
MO-203  
SC-88A  
Figure 7. Package outline SOT353-1 (TSSOP5)  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
8 / 13  
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
Plastic surface-mounted package; 5 leads  
SOT753  
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X  
b
e
w
M B  
p
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
1
b
c
D
e
H
L
Q
v
w
y
E
p
p
E
0.100  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
02-04-16  
06-03-16  
SOT753  
SC-74A  
Figure 8. Package outline SOT753 (SC-74A)  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
9 / 13  
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
13 Abbreviations  
Table 11. Abbreviations  
Acronym  
Description  
CMOS  
DUT  
ESD  
HBM  
MIL  
Complementary Metal-Oxide Semiconductor  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Military  
MM  
Machine Model  
TTL  
Transistor-Transistor Logic  
14 Revision history  
Table 12. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
74LVC1G86_Q100 v.3  
Modifications:  
20170307  
Product data sheet  
-
74LVC1G86_Q100 v.2  
The format of this data sheet has been redesigned to comply with the identity guidelines of  
Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
74LVC1G86_Q100 v.2  
Modifications:  
20161212  
Table 7: The maximum limits for leakage current and supply current have changed.  
20131115 Product data sheet  
Product data sheet  
-
74LVC1G86_Q100 v.1  
74LVC1G86_Q100 v.1  
-
-
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
10 / 13  
 
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
15 Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Definition  
Objective [short] data sheet  
Development  
This document contains data from the objective specification for product  
development.  
Preliminary [short] data sheet  
Product [short] data sheet  
Qualification  
Production  
This document contains data from the preliminary specification.  
This document contains the product specification.  
[1] Please consult the most recently issued document before initiating or completing a design.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple  
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.  
or warranty that such applications will be suitable for the specified use  
without further testing or modification. Customers are responsible for the  
15.2 Definitions  
design and operation of their applications and products using Nexperia  
products, and Nexperia accepts no liability for any assistance with  
Draft — The document is a draft version only. The content is still under  
applications or customer product design. It is customer’s sole responsibility  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any representations or  
customer’s applications and products planned, as well as for the planned  
warranties as to the accuracy or completeness of information included herein  
application and use of customer’s third party customer(s). Customers should  
and shall have no liability for the consequences of use of such information.  
provide appropriate design and operating safeguards to minimize the risks  
to determine whether the Nexperia product is suitable and fit for the  
associated with their applications and products. Nexperia does not accept  
Short data sheet — A short data sheet is an extract from a full data sheet  
any liability related to any default, damage, costs or problem which is based  
with the same product type number(s) and title. A short data sheet is  
on any weakness or default in the customer’s applications or products, or  
intended for quick reference only and should not be relied upon to contain  
the application or use by customer’s third party customer(s). Customer is  
detailed and full information. For detailed and full information see the  
responsible for doing all necessary testing for the customer’s applications  
relevant full data sheet, which is available on request via the local Nexperia  
and products using Nexperia products in order to avoid a default of the  
sales office. In case of any inconsistency or conflict with the short data sheet,  
applications and the products or of the application or use by customer’s third  
the full data sheet shall prevail.  
party customer(s). Nexperia does not accept any liability in this respect.  
Product specification — The information and data provided in a Product  
Limiting values — Stress above one or more limiting values (as defined in  
data sheet shall define the specification of the product as agreed between  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
Nexperia and its customer, unless Nexperia and customer have explicitly  
damage to the device. Limiting values are stress ratings only and (proper)  
agreed otherwise in writing. In no event however, shall an agreement be  
operation of the device at these or any other conditions above those  
valid in which the Nexperia product is deemed to offer functions and qualities  
beyond those described in the Product data sheet.  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
15.3 Disclaimers  
Terms and conditions of commercial sale — Nexperia products are  
sold subject to the general terms and conditions of commercial sale, as  
Limited warranty and liability — Information in this document is believed  
published at http://www.nexperia.com/profile/terms, unless otherwise agreed  
to be accurate and reliable. However, Nexperia does not give any  
in a valid written individual agreement. In case an individual agreement is  
representations or warranties, expressed or implied, as to the accuracy  
concluded only the terms and conditions of the respective agreement shall  
or completeness of such information and shall have no liability for the  
apply. Nexperia hereby expressly objects to applying the customer’s general  
consequences of use of such information. Nexperia takes no responsibility  
terms and conditions with regard to the purchase of Nexperia products by  
for the content in this document if provided by an information source outside  
customer.  
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation -  
lost profits, lost savings, business interruption, costs related to the removal  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or  
or replacement of any products or rework charges) whether or not such  
the grant, conveyance or implication of any license under any copyrights,  
damages are based on tort (including negligence), warranty, breach of  
patents or other industrial or intellectual property rights.  
contract or any other legal theory. Notwithstanding any damages that  
customer might incur for any reason whatsoever, Nexperia's aggregate and  
Suitability for use in automotive applications — This Nexperia product  
cumulative liability towards customer for the products described herein shall  
has been qualified for use in automotive applications. Unless otherwise  
be limited in accordance with the Terms and conditions of commercial sale of  
agreed in writing, the product is not designed, authorized or warranted to  
Nexperia.  
be suitable for use in life support, life-critical or safety-critical systems or  
equipment, nor in applications where failure or malfunction of an Nexperia  
product can reasonably be expected to result in personal injury, death or  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
severe property or environmental damage. Nexperia and its suppliers accept  
specifications and product descriptions, at any time and without notice. This  
no liability for inclusion and/or use of Nexperia products in such equipment or  
document supersedes and replaces all information supplied prior to the  
applications and therefore such inclusion and/or use is at the customer's own  
publication hereof.  
risk.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
11 / 13  
 
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
74LVC1G86_Q100  
All information provided in this document is subject to legal disclaimers.  
© Nexperia B.V. 2017. All rights reserved.  
Product data sheet  
Rev. 3 — 7 March 2017  
12 / 13  
Nexperia  
74LVC1G86-Q100  
2-input EXCLUSIVE-OR gate  
Contents  
1
General description ............................................ 1  
2
3
4
5
Features and benefits .........................................1  
Ordering information .......................................... 2  
Marking .................................................................2  
Functional diagram .............................................2  
Pinning information ............................................ 2  
Pinning ...............................................................2  
Pin description ...................................................3  
Functional description ........................................3  
Limiting values ....................................................3  
Recommended operating conditions ................4  
Static characteristics ..........................................4  
Dynamic characteristics .....................................5  
Waveforms and test circuit ................................6  
Package outline ...................................................8  
Abbreviations .................................................... 10  
Revision history ................................................ 10  
Legal information ..............................................11  
6
6.1  
6.2  
7
8
9
10  
11  
11.1  
12  
13  
14  
15  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section 'Legal information'.  
© Nexperia B.V. 2017.  
All rights reserved.  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 7 March 2017  
Document identifier: 74LVC1G86_Q100  

相关型号:

74LVC1G86GW-Q100H

74LVC1G86-Q100 - 2-input EXCLUSIVE-OR gate TSSOP 5-Pin
NXP

74LVC1G86GX

2-input EXCLUSIVE-OR gateProduction
NEXPERIA

74LVC1G86SE

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86SE-7

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86W5

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86W5-7

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86Z-7

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86_12

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G97

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES

74LVC1G97DW

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES

74LVC1G97DW-7

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES

74LVC1G97FW4

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES