74LVC1G97GW-Q100 [NEXPERIA]
Low-power configurable multiple function gateProduction;
| 型号： | 74LVC1G97GW-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Low-power configurable multiple function gateProduction 逻辑集成电路 |
| 文件： | 总14页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G97-Q100
Low-power configurable multiple function gate
Rev. 2 — 24 January 2022
Product data sheet
1. General description
The 74LVC1G97-Q100 is a configurable multiple function gate with Schmitt-trigger inputs. The
device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR,
inverter and buffer; using the 3-bit input. All inputs can be connected to VCC or GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
•
•
±24 mA output drive (VCC = 3.0 V)
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM ANSI/ESDA/Jedec JS-001 exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
•
•
•
•
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC1G97GW-Q100 -40 °C to +125 °C
TSSOP6
plastic thin shrink small outline package;
6 leads; body width 1.25 mm
SOT363-2
4. Marking
Table 2. Marking
Type number
Marking code[1]
74LVC1G97GW-Q100
YV
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
A
4
Y
1
B
6
C
001aad998
Fig. 1. Logic symbol
6. Pinning information
6.1. Pinning
74LVC1G97
1
2
3
6
5
4
B
GND
A
C
V
Y
CC
001aan190
Fig. 2. Pin configuration SOT363-2 (TSSOP6)
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 24 January 2022
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Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
data input
B
GND
A
2
ground (0 V)
data input
3
Y
4
data output
supply voltage
data input
VCC
C
5
6
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
C
L
B
L
A
L
Y
L
L
L
H
L
L
L
H
H
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
L
H
H
H
H
7.1. Logic configurations
Table 5. Function selection table
Logic function
Figure
2-input MUX
see Fig. 3
see Fig. 4
see Fig. 5
see Fig. 5
see Fig. 6
see Fig. 6
see Fig. 7
see Fig. 8
see Fig. 9
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 24 January 2022
3 / 14
Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
V
V
CC
CC
B
A
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
B
A
C
A
C
Y
Y
A
001aae002
001aae003
Fig. 3. 2-input MUX
Fig. 4. 2-input AND gate
V
V
CC
CC
A
C
B
Y
C
Y
Y
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
A
C
B
Y
C
A
001aae004
001aae005
Fig. 5. 2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
Fig. 6. 2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
V
V
CC
CC
B
1
2
3
6
5
4
C
1
2
3
6
5
4
C
B
C
Y
C
Y
Y
Y
001aae006
001aae007
Fig. 7. 2-input OR gate
Fig. 8. Inverter
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aae008
Fig. 9. Buffer
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74LVC1G97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 24 January 2022
4 / 14
Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+6.5
±50
+6.5
+6.5
±50
+100
-
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1]
[1]
-0.5
-0.5
-
Power-down mode; VCC = 0 V
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT363-2 (TSSOP6) package: Ptot derates linearly with 3.7 mW/K above 83 °C.
9. Recommended operating conditions
Table 7. Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
0
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
-
-
-
-
-
5.5
V
VO
Active mode
0
VCC
5.5
V
VCC = 0 V; Power-down mode
0
V
Tamb
ambient temperature
-40
+125
°C
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74LVC1G97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
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5 / 14
Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
10. Static characteristics
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
Typ[1]
-40 °C to +125 °C Unit
Min
Max
Min
Max
VOL
LOW-level output
VI = VCC or GND
voltage
IO = 100 μA;
-
-
0.1
-
0.1
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = VCC or GND
-
-
-
-
-
-
-
-
-
-
0.45
0.3
-
-
-
-
-
0.7
0.45
0.6
V
V
V
V
V
0.4
0.55
0.55
0.8
0.8
VOH
HIGH-level output
voltage
IO = -100 μA;
VCC - 0.1
-
-
VCC - 0.1
-
V
VCC = 1.65 V to 5.5 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -24 mA; VCC = 3.0 V
IO = -32 mA; VCC = 4.5 V
1.2
1.9
2.2
2.3
3.8
-
-
-
-
0.95
1.7
1.9
2.0
3.4
-
-
-
V
-
V
-
-
-
V
-
-
-
-
V
-
-
V
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
±0.1
±1
±1
μA
IOFF
ICC
ΔICC
CI
power-off leakage
current
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
±0.1
0.1
5
±2
4
-
-
-
-
±2
4
μA
μA
μA
pF
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
additional supply
current
VI = VCC - 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
500
-
500
-
input capacitance
2.5
[1] Typical values are measured at maximum VCC and Tamb = 25 °C.
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74LVC1G97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
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74LVC1G97-Q100
Low-power configurable multiple function gate
11. Dynamic characteristics
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11.
Symbol Parameter Conditions
-40 °C to +85 °C
Typ[1]
-40 °C to +125 °C Unit
Min
Max
Min
Max
tpd
propagation delay A, B, C to Y; see Fig. 10
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
[2]
1.0
0.5
0.5
0.5
0.5
-
6.0
3.5
4.2
3.8
3.0
22
14.4
8.3
8.5
6.3
5.1
-
1.0
0.5
0.5
0.5
0.5
-
18.0
10.4
10.6
7.9
6.4
-
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation
capacitance
VCC = 3.3 V; VI = GND to VCC [3]
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of outputs.
11.1. Waveforms and test circuit
V
I
A, B, C input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
V
M
Y output
M
t
V
OL
t
PLH
PHL
V
OH
Y output
V
M
M
V
OL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. Input A, B and C to output Y propagation delay times
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74LVC1G97-Q100
Low-power configurable multiple function gate
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VI
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
VCC
VCC
2.7 V
2.7 V
VCC
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Measurement points are given in Table 11.
Definitions test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Fig. 11. Test circuit for measuring switching times
Table 11. Measurement points
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
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Product data sheet
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74LVC1G97-Q100
Low-power configurable multiple function gate
12. Transfer characteristics
Table 12. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
Typ[1]
-40 °C to +125 °C Unit
Min
Max
Min
Max
VT+
VT-
VH
positive-going
threshold voltage Fig. 14 and Fig. 15
See Fig. 12, Fig. 13,
VCC = 1.8 V
0.70
1.11
1.50
2.16
2.61
1.02
1.42
1.79
2.52
2.99
1.20
1.60
2.00
2.74
3.33
0.67
1.08
1.47
2.13
2.58
1.20
1.60
2.00
2.74
3.33
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V, see Fig. 16
VCC = 4.5 V
VCC = 5.5 V
negative-going
threshold voltage Fig. 14 and Fig. 15
See Fig. 12, Fig. 13,
VCC = 1.8 V
0.30
0.58
0.80
1.21
1.45
0.53
0.77
1.04
1.55
1.86
0.72
1.00
1.30
1.90
2.29
0.30
0.58
0.80
1.21
1.45
0.75
1.03
1.33
1.93
2.32
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V, see Fig. 16
VCC = 4.5 V
VCC = 5.5 V
hysteresis voltage (VT+ - VT-).
See Fig. 12, Fig. 13,
Fig. 14 and Fig. 15
VCC = 1.8 V
0.30
0.40
0.50
0.71
0.71
0.48
0.64
0.75
0.97
1.13
0.62
0.80
1.00
1.20
1.40
0.23
0.34
0.44
0.65
0.65
0.62
0.80
1.00
1.20
1.40
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V, see Fig. 16
VCC = 4.5 V
VCC = 5.5 V
[1] Typical values are measured at Tamb = 25 °C.
12.1. Waveforms transfer characteristics
V
V
T+
O
V
I
V
H
V
T-
V
O
V
I
V
H
mna208
V
V
T+
T-
mna207
VT+ and VT- limits are at 70 % and 20 %.
Fig. 12. Transfer characteristic
Fig. 13. Definition of VT+, VT- and VH
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74LVC1G97-Q100
Low-power configurable multiple function gate
V
O
V
T+
V
I
V
H
V
T-
V
O
V
I
V
H
mnb155
V
T-
V
T+
mnb154
VT+ and VT- limits are at 70 % and 20 %.
Fig. 14. Transfer characteristic
Fig. 15. Definition of VT+, VT- and VH
001aab594
16
I
CC
(mA)
12
8
4
0
0
1
2
3
V (V)
I
Fig. 16. Typical 74LVC1G97-Q100 transfer characteristic; VCC = 3.0 V
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74LVC1G97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
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10 / 14
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74LVC1G97-Q100
Low-power configurable multiple function gate
13. Package outline
TSSOP6: plastic thin shrink small outline package; 6 leads; body width 1.25 mm
SOT363-2
D
B
E
A
X
c
(6x)
y
H
E
v
M
A
e
1
6
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(6x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot363-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT363-2
SC-88A
MO-203
Fig. 17. Package outline SOT363-2 (TSSOP6)
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Nexperia B.V. 2022. All rights reserved
Product data sheet
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Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
14. Abbreviations
Table 13. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14. Revision history
Document ID
Release date
20220124
Data sheet status
Change notice
Supersedes
74LVC1G97_Q100 v.2
Modifications:
Product data sheet
-
74LVC1G97_Q100 v.1
•
•
Table 6: Derating values for Ptot total power dissipation updated.
SOT363 (SC-88) package changed to SOT363-2 (TSSOP6).
74LVC1G97_Q100 v.1
20190322
Product data sheet
-
-
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Product data sheet
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Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
16. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
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liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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©
74LVC1G97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 24 January 2022
13 / 14
Nexperia
74LVC1G97-Q100
Low-power configurable multiple function gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................3
7. Functional description................................................. 3
7.1. Logic configurations.....................................................3
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................5
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 7
12. Transfer characteristics............................................. 9
12.1. Waveforms transfer characteristics............................9
13. Package outline........................................................ 11
14. Abbreviations............................................................12
15. Revision history........................................................12
16. Legal information......................................................13
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 24 January 2022
©
74LVC1G97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 2 — 24 January 2022
14 / 14
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