74LVC2GU04GW-Q100 [NEXPERIA]
Dual unbuffered inverter;
| 型号： | 74LVC2GU04GW-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Dual unbuffered inverter 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2GU04-Q100
Dual unbuffered inverter
Rev. 4 — 11 February 2019
Product data sheet
1. General description
The 74LVC2GU04-Q100 provides two unbuffered inverters. Each inverter is a single stage with
unbuffered output.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device
in a mixed 3.3 V and 5 V environment.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
•
•
•
•
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Input accepts voltages up to 5 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
SOT363
SOT457
74LVC2GU04GW-Q100 -40 °C to +125 °C
74LVC2GU04GV-Q100 -40 °C to +125 °C
SC-88
plastic surface-mounted package; 6 leads
TSOP6
plastic surface-mounted package (TSOP6);
6 leads
74LVC2GU04GM-Q100 -40 °C to +125 °C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
SOT886
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
4. Marking
Table 2. Marking codes
Type number
Marking[1]
YD
74LVC2GU04GW-Q100
74LVC2GU04GV-Q100
74LVC2GU04GM-Q100
VU4
YD
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
V
V
CC
CC
6
1
1A
1Y
1
1
1
3
6
4
100 Ω
Y
A
4
3
2A
2Y
mnb106
mnb107
mna636
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram (one gate)
6. Pinning information
6.1. Pinning
74LVC2GU04
74LVC2GU04
1A
GND
2A
1
2
3
6
5
4
1Y
1
2
3
6
5
4
1A
GND
2A
1Y
V
CC
V
CC
2Y
2Y
001aab681
Transparent top view
001aab680
Fig. 4. Pin configuration SOT363 (SC-88) and SOT457
(TSOP6)
Fig. 5. Pin configuration SOT886 (XSON6)
6.2. Pin description
Table 3. Pin description
Symbol
1A
Pin
1
Description
data input
GND
2A
2
ground (0 V)
data input
3
2Y
4
data output
supply voltage
data output
VCC
1Y
5
6
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74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
2 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
nA
L
Output
nY
H
H
L
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+6.5
-
IOK
VO
IO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode
VO = 0 V to VCC
[1][2]
VCC + 0.5
±50
100
-
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[3]
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and TSOP6 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
1.65
-
-
-
-
-
-
input voltage
0
0
5.5
V
VO
output voltage
Active mode
VCC
+125
20
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
°C
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
ns/V
ns/V
-
10
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74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
3 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = -40 °C to +85 °C
Tamb = -40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
VIL
HIGH-level input VCC = 1.65 V to 5.5 V
voltage
0.75VCC
-
-
0.8VCC
-
V
V
LOW-level input VCC = 1.65 V to 5.5 V
voltage
-
-
-
0.25VCC
-
0.2VCC
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -100 μA;
VCC - 0.1
-
VCC - 0.1
-
V
VCC = 1.65 V to 5.5 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -24 mA; VCC = 3.0 V
IO = -32 mA; VCC = 4.5 V
VI = VIH or VIL
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output voltage
IO = 100 μA;
-
-
0.1
-
0.1
V
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
-
0.45
0.3
-
-
-
-
-
-
0.7
0.45
0.6
0.8
0.8
±1
V
-
V
-
0.4
V
-
-
0.55
0.55
±1
V
V
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
±0.1
μA
ICC
CI
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
-
0.1
5
4
-
-
-
4
-
μA
pF
input
VCC = 3.3 V; VI = GND to VCC
capacitance
[1] All typical values are measured at VCC = 3.3 V and at Tamb = 25 °C.
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74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
4 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.
Symbol Parameter
Conditions
Tamb = -40 °C to +85 °C
Tamb = -40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tpd
propagation
delay
nA to nY; see Fig. 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[2]
0.5
0.3
0.3
0.3
0.3
-
2.3
1.8
2.6
2.3
1.7
7.8
5.0
4.0
4.5
3.7
3.0
-
0.5
0.3
0.3
0.3
0.3
6.3
5.0
5.6
4.5
3.8
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation VI = GND to VCC
;
[3]
capacitance VCC = 3.3 V
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
11.1. Waveforms and test circuit
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
M
V
M
nY output
V
mna344
OL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig. 6. The input (nA) to output (nY) propagation delay times
Table 9. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
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74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
5 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 7. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
mnb108
160
g
fs
(mA/V)
R
bias
= 560 kΩ
120
V
CC
80
40
0
0.47 µF
100 µF
input
output
V
I
A
I
O
mna638
0
1
2
3
4
5
6
V
(V)
CC
fi = 1 kHz.
VO is constant.
Fig. 8. Typical forward transconductance as a function Fig. 9. Test set-up for measuring forward
of supply voltage transconductance
Tamb = 25 °C.
©
74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
6 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
12. Application information
Some applications are:
•
•
Linear amplifier (see Fig. 10)
In crystal oscillator design (see Fig. 11)
Remark: All values given are typical unless otherwise specified.
R2
V
CC
R1
1 µF
R1
U04
R2
Z
L
U04
C1
C2
out
mna052
Vo(p-p) = VCC - 1.5 V centered at 0.5VCC
.
mna053
C1 = 47 pF (typical).
C2 = 22 pF (typical).
GOL = open loop gain.
R1 = 1 MΩ to 10 MΩ (typical).
Au = voltage amplification.
R1 ≥ 3 kΩ, R2 ≤ 1 MΩ.
R2 optimum value depends on the frequency
and required stability against changes in VCC
or average minimum ICC (ICC is typically 2 mA
at VCC = 3.3 V and f = 10 MHz).
ZL > 10 kΩ; GOL = 20 (typical).
Typical unity gain bandwidth product is 5 MHz.
Fig. 10. Linear amplifier configuration
Fig. 11. Crystal oscillator configuration
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74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
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Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
w
M B
p
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
p
c
D
e
e
H
L
Q
v
w
y
E
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig. 12. Package outline SOT363 (SC-88)
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74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
8 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
Plastic, surface-mounted package (SC-74; TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
E
v
M
A
6
5
4
Q
A
pin 1
index
A
1
c
L
p
1
2
3
detail X
b
p
e
w
M B
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
A
A
b
c
D
E
e
H
E
L
p
Q
v
w
y
1
p
max 1.1
nom
0.1
0.40 0.26 3.1 1.7
3.0 0.6 0.33
2.5 0.2 0.23
mm
0.95
0.2 0.2 0.1
0.9 0.013 0.25 0.10 2.7 1.3
min
sot457_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
SC-74
06-03-16
18-11-27
SOT457
Fig. 13. Package outline SOT457 (TSOP6)
©
74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
9 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
e
1
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
b
D
E
e
e
L
L
1
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.30 0.35
0.27 0.32
nom
min
0.20 1.45 1.00 0.6
0.17 1.40 0.95
mm
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Fig. 14. Package outline SOT886 (XSON6)
©
74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
10 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
15. Revision history
Table 12. Revision history
Document ID
Release date
20190211
Data sheet status
Change notice Supersedes
- 74LVC2GU04_Q100 v.3
74LVC2GU04_Q100 v.4
Modifications:
Product data sheet
•
Type number 74LVC2GU04GM-Q100 (SOT886/XSON6) added.
74LVC2GU04_Q100 v.3
Modifications:
20181009 Product data sheet 74LVC2GU04_Q100 v.2
-
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
Legal texts have been adapted to the new company name where appropriate.
Typo corrected in General description.
74LVC2GU04_Q100 v.2
Modifications:
20161214
Table 7: The maximum limits for leakage current and supply current have changed.
20120731 Product data sheet
Product data sheet
-
74LVC2GU04_Q100 v.1
•
74LVC2GU04_Q100 v.1
-
-
©
74LVC2GU04_Q100
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
11 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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Definition
[1][2]
status [3]
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or warranty that such applications will be suitable for the specified use
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data sheet
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This document contains data from
the objective specification for
product development.
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data sheet
Qualification
Production
This document contains data from
the preliminary specification.
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data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
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[2] The term 'short data sheet' is explained in section "Definitions".
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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with the same product type number(s) and title. A short data sheet is
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©
74LVC2GU04_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
12 / 13
Nexperia
74LVC2GU04-Q100
Dual unbuffered inverter
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................2
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 5
12. Application information............................................. 7
13. Package outline.......................................................... 8
14. Abbreviations............................................................11
15. Revision history........................................................11
16. Legal information......................................................12
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 11 February 2019
©
74LVC2GU04_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 4 — 11 February 2019
13 / 13
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