BUK9V13-40H [NEXPERIA]
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)Production;型号: | BUK9V13-40H |
厂家: | Nexperia |
描述: | Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)Production |
文件: | 总13页 (文件大小:306K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in
LFPAK56D (half-bridge configuration)
9 May 2023
Product data sheet
1. General description
D1
Dual, logic level N-channel MOSFET in an LFPAK56D package
(half-bridge configuration), using Trench 9 TrenchMOS technology. This
product has been designed and qualified to AEC-Q101.
G1
G2
An internal connection is made between the source (S1) of the high-
side FET to the drain (D2) of the low-side FET, making the device ideal
to use as a half-bridge switch in high-performance automotive PWM
applications.
S1, D2
S2
aaa-028081
2. Features and benefits
•
•
LFPAK56D package with half-bridge configuration enables:
•
•
•
•
•
Reduced PCB layout complexity
PCB shrinkage through reduced component footprint for 3-phase motor drive
Improved system level Rth(j-amb) due to optimized package design
Lower parasitic inductance to support higher efficiency
Footprint compatibility with LFPAK56D Dual package
Advanced AEC-Q101 grade Trench 9 silicon technology:
•
•
•
Low power losses, high power density
Superior avalanche performance
Repetitive avalanche rated
•
•
LFPAK copper clip packaging provides high robustness and reliability
Gull wing leads support high manufacturability and Automated Optical Inspection (AOI)
3. Applications
•
•
•
•
•
12 V automotive systems
Powertrain, chassis, body and infotainment applications
Brushless or brushed DC motor drive
DC-to-DC systems
LED lighting
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Limiting values FET1 and FET2
VDS
ID
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
-
-
-
-
-
-
40
42
46
V
VGS = 10 V; Tmb = 25 °C; Fig. 2
[1]
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 1
W
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 10 A; Tj = 25 °C;
Fig. 11
7.9
11.35 13.6
mΩ
Dynamic characteristics FET1 and FET2
QGD gate-drain charge
ID = 10 A; VDS = 32 V; VGS = 5 V;
Tj = 25 °C; Fig. 13; Fig. 14
-
-
2.1
4.2
-
nC
nC
Source-drain diode FET1 and FET2
Qr recovered charge
IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; [2]
VDS = 20 V; Tj = 25 °C
16.2
[1] 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
[2] includes capacitive recovery
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol
S2
Description
source2
Simplified outline
Graphic symbol
8
7
6
5
D1
2
G2
gate2
3
S1, D2
G1
source1, drain2
gate1
G1
G2
4
S1, D2
5
D1
drain1
6
D1
drain1
7
S1, D2
S1, D2
source1, drain2
source1, drain2
1
2
3
4
S2
aaa-028081
8
LFPAK56D; Dual
LFPAK (SOT1205)
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
BUK9V13-40H
LFPAK56D;
Dual LFPAK
plastic, single ended surface mounted package
(LFPAK56D); 8 leads
SOT1205
7. Marking
Table 4. Marking codes
Type number
Marking code
9V1340H
BUK9V13-40H
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BUK9V13-40H
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
2 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Limiting values FET1 and FET2
VDS
VGS
Ptot
ID
drain-source voltage
gate-source voltage
total power dissipation
drain current
25 °C ≤ Tj ≤ 175 °C
-
40
V
DC; Tj = 25 °C
-20
20
V
Tmb = 25 °C; Fig. 1
-
46
W
A
VGS = 10 V; Tmb = 25 °C; Fig. 2
VGS = 10 V; Tmb = 100 °C; Fig. 2
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
[1]
-
42
-
30
A
IDM
Tstg
Tj
peak drain current
storage temperature
junction temperature
-
169
175
175
A
-55
-55
°C
°C
Source-drain diode FET1 and FET2
IS
source current
Tmb = 25 °C
-
-
42
A
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
169
Avalanche ruggedness FET1 and FET2
EDS(AL)S non-repetitive drain-
ID = 39.9 A; Vsup ≤ 40 V; RGS = 50 Ω;
[2] [3]
[4]
-
-
10.6
39.9
mJ
A
source avalanche energy VGS = 10 V; Tj(init) = 25 °C; Fig. 4
IAS
non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C;
current
RGS = 50 Ω; Fig. 4
[1] 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
[2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[3] Refer to application note AN10273 for further information.
[4] Protected by 100% test
03aa16
aaa-032340
120
50
40
30
20
10
0
I
D
(A)
P
der
(%)
80
40
0
0
50
100
150
200
0
25
50
75 100 125 150 175 200
T
mb
(°C)
T
(°C)
mb
VGS ≥ 10 V
42A continuous current has been successfully
demonstrated during application tests. Practically
the current will be limited by PCB, thermal design
and operating temperature.
Fig. 1. Normalized total power dissipation as a
function of mounting base temperature
Fig. 2. Continuous drain current as a function of
mounting base temperature, FET1 and FET2
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BUK9V13-40H
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
3 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032342
3
10
I
D
(A)
Limit R
= V / I
DS D
DSon
2
10
t
p
= 10 µs
100 µs
10
DC
1
1 ms
10 ms
100 ms
-1
10
-1
2
10
1
10
10
V
DS
(V)
Tmb = 25 °C; IDM is a single pulse
Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
aaa-032341
2
10
I
AL
(A)
(1)
10
(2)
(3)
1
-1
10
-2
10
-3
-2
-1
10
10
10
1
AL
10
t
(ms)
(1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche
Fig. 4. Avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from Fig. 5
junction to mounting
base
-
3
3.23
K/W
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
4 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032343
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
t
p
-1
P
10
δ =
0.02
single shot
T
t
t
p
T
-2
10
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
p
(s)
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and
FET2
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -40 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
40
-
43
-
V
V
V
V
40.5
40
-
36
1.5
-
VGS(th)
gate-source threshold ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9;
1.85
2.2
voltage
Fig. 10
ID = 1 mA; VDS=VGS; Tj = 175 °C;
Fig. 10
0.7
-
-
V
ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 10
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VDS = 16 V; VGS = 0 V; Tj = 125 °C
VDS = 40 V; VGS = 0 V; Tj = 175 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -10 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
-
-
2.6
5
V
IDSS
drain leakage current
gate leakage current
0.01
0.14
26
2
µA
µA
µA
nA
nA
10
500
100
100
IGSS
2
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BUK9V13-40H
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Product data sheet
9 May 2023
5 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 10 A; Tj = 25 °C;
Fig. 11
7.9
11.35 13.6
mΩ
VGS = 10 V; ID = 10 A; Tj = 105 °C;
Fig. 12
10.9
12
16.87 20.4
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
Ω
VGS = 10 V; ID = 10 A; Tj = 125 °C;
Fig. 12
18.2
21.9
VGS = 10 V; ID = 10 A; Tj = 175 °C;
Fig. 12
14.5
9.8
21.97 26.4
14.04 16.9
VGS = 4.5 V; ID = 10 A; Tj = 25 °C;
Fig. 11
VGS = 4.5 V; ID = 10 A; Tj = 105 °C;
Fig. 12
13.5
14.8
18
20.6
25.4
VGS = 4.5 V; ID = 10 A; Tj = 125 °C;
Fig. 12
22.24 27.2
26.65 32.8
VGS = 4.5 V; ID = 10 A; Tj = 175 °C;
Fig. 12
RG
gate resistance
f = 1 MHz; Tj = 25 °C
0.7
1.7
4.2
Dynamic characteristics FET1 and FET2
QG(tot)
total gate charge
ID = 10 A; VDS = 32 V; VGS = 10 V;
Tj = 25 °C; Fig. 13; Fig. 14
-
13.9
19.4
nC
ID = 10 A; VDS = 32 V; VGS = 5 V;
Tj = 25 °C; Fig. 13; Fig. 14
-
-
-
-
-
-
7.3
2.5
2.1
829
280
38
10.2
3.8
nC
nC
nC
QGS
QGD
Ciss
Coss
Crss
gate-source charge
gate-drain charge
input capacitance
output capacitance
4.2
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 15
1160 pF
420
84
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 30 V; RL = 3 Ω; VGS = 5 V;
RG(ext) = 5 Ω; Tj = 25 °C
-
-
-
-
5.6
8.1
9.1
6.5
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
Source-drain diode FET1 and FET2
VSD
trr
source-drain voltage
IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 16
-
-
-
0.84
21.5
16.2
1
-
V
reverse recovery time IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
ns
nC
VDS = 20 V; Tj = 25 °C
Qr
recovered charge
[1]
-
[1] includes capacitive recovery
©
BUK9V13-40H
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
6 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032344
aaa-032345
60
30
I
R
(mΩ)
D
DSon
10 V
(A)
4.5 V
25
20
15
10
5
48
36
24
12
0
3.5 V
V
= 3 V
GS
2.8 V
2.6 V
0
0
1
2
3
V
4
0
4
8
12
16
V (V)
GS
20
(V)
DS
Tj = 25 °C
Tj = 25 °C; ID = 10 A
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values,
FET1 and FET2
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values, FET1 and
FET2
aaa-032346
aaa-029502
-1
60
10
I
D
I
D
(A)
(A)
-2
-3
-4
-5
-6
48
36
24
12
0
10
10
10
10
10
Min
Typ
Max
175°C
2
T = -55°C
j
25°C
0
1
3
4
5
0
0.5
1
1.5
2
2.5
(V)
3
V
(V)
V
GS
GS
VDS = 8 V
Tj = 25 °C; VDS = 5 V
Fig. 8. Transfer characteristics; drain current as a
function of gate-source voltage; typical values,
FET1 and FET2
Fig. 9. Sub-threshold drain current as a function of
gate-source voltage, FET1 and FET2
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BUK9V13-40H
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
7 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
aaa-029503
aaa-032347
3
80
V
GS(th)
(V)
R
(mΩ)
DSon
2.8 V
3 V
2.5
64
48
32
16
0
Max
2
1.5
1
Typ
Min
3.5 V
4.5 V
0.5
V
GS
= 10 V
0
-60 -30
0
30
60
90 120 150 180
0
6
12
18
24
30
(A)
36
T (°C)
I
D
j
ID = 1 mA ; VDS = VGS
Tj = 25 °C
Fig. 10. Gate-source threshold voltage as a function of Fig. 11. Drain-source on-state resistance as a function
junction temperature, FET1 and FET2
of drain current; typical values, FET1 and FET2
aaa-029504
aaa-032348
2
10
a
V
GS
(V)
1.7
1.4
1.1
0.8
0.5
8
6
4
2
0
V
= 4.5 V
GS
10 V
32 V
= 14 V
V
DS
-60 -30
0
30
60
90 120 150 180
0
4
8
12
16
Q (nC)
G
20
T (°C)
j
Tj = 25 °C; ID = 10 A
Fig. 13. Gate-source voltage as a function of gate
charge; typical values, FET1 and FET2
Fig. 12. Normalized drain-source on-state resistance
factor as a function of junction temperature,
FET1 and FET2
©
BUK9V13-40H
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
8 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032349
4
10
C
(pF)
V
DS
I
D
3
2
10
10
C
C
iss
V
GS(pl)
oss
V
GS(th)
V
GS
C
rss
Q
GS2
Q
GS1
10
10
-1
2
Q
Q
1
10
10
GS
GD
V
DS
(V)
Q
G(tot)
003aaa508
VGS = 0 V; f = 1 MHz
Fig. 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values, FET1 and FET2
Fig. 14. Gate charge waveform definitions
aaa-032350
60
I
S
(A)
48
36
24
12
0
-55°C
175°C
T = 25°C
j
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
(V)
VGS = 0 V
Fig. 16. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values,
FET1 and FET2
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BUK9V13-40H
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Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
9 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
11. Package outline
Plastic single ended surface mounted package LFPAK56D; 8 leads
SOT1205
E
A
A
b
c
1
1
L
1
mounting
base
D
1
D
2
D
H
L
1
2
3
4
X
b
(8x)
e
c
E
1
w
A
E
2
C
A
1
θ
L
p
y
C
detail X
0
2.5
5 mm
scale
Dimensions
Unit
D
(ref)
2
(1)
(1)
(1)
E
(1)
A
A
b
b
c
c
D
D
1
E
E
e
H
L
L
L
p
w
y
θ
1
1
1
1
2
1
°
8
0
max 1.05 0.1 0.50 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85
nom
min 1.02 0.0 0.35 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60
6.2 1.3 0.55 0.85
5.9 0.8 0.30 0.40
mm
1.27
0.25 0.1
°
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot1205_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
14-08-21
14-10-28
SOT1205
Fig. 17. Package outline LFPAK56D; Dual LFPAK (SOT1205)
©
BUK9V13-40H
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
10 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
12. Soldering
Footprint information for reflow soldering of LFPAK56D package
SOT1205
5.85
0.57
0.57
0.7
1.97
1.27
0.65
0.025
1.9
3.325
3.175
3.2
2.0
1.275
0.8
1.0
1.875
2.1
2.7
3.85
3.975
0.025
1.1
1.15
0.65
1.27
1.44
0.7
1.1
solder land
solder land plus solder paste
solder paste deposit
occupied area
14-07-28
solder resist
Dimensions in mm
sot1205_fr
Issue date
20-04-20
Fig. 18. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205)
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Product data sheet
9 May 2023
11 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
13. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
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©
BUK9V13-40H
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
12 / 13
Nexperia
BUK9V13-40H
Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 4
10. Characteristics............................................................5
11. Package outline........................................................ 10
12. Soldering................................................................... 11
13. Legal information......................................................12
© Nexperia B.V. 2023. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 9 May 2023
©
BUK9V13-40H
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
9 May 2023
13 / 13
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