HEF4001BT-Q100 [NEXPERIA]
Quad 2-input NOR gateProduction;型号: | HEF4001BT-Q100 |
厂家: | Nexperia |
描述: | Quad 2-input NOR gateProduction |
文件: | 总10页 (文件大小:192K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4001B-Q100
Quad 2-input NOR gate
Rev. 2 — 19 November 2021
Product data sheet
1. General description
The HEF4001B-Q100 is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VDD
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 3.0 V to 15.0 V
CMOS low power dissipation
High noise immunity
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
Name
Description
Version
HEF4001BT-Q100 -40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
4. Functional diagram
1A
1B
1
2
1Y
2Y
3Y
4Y
3
2A
2B
5
6
4
10
3A
3B
8
9
4A
4B
12
13
nA
nB
11
nY
001aag194
001aag195
Fig. 1. Functional diagram
Fig. 2. Logic diagram (one gate)
5. Pinning information
5.1. Pinning
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2Y
2A
2B
V
DD
4B
4A
4Y
3Y
3B
3A
HEF4001B
8
V
SS
001aag196
Fig. 3. Pin configuration SOT108-1 (SO14)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
input
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
VSS
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
7
input
output
ground (0 V)
supply voltage
VDD
14
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HEF4001B_Q100
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Product data sheet
Rev. 2 — 19 November 2021
2 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
nA
L
nB
L
nY
H
L
L
H
L
H
H
L
H
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min
Max
+18
Unit
V
VDD
IIK
supply voltage
-0.5
input clamping current
input voltage
VI < -0.5 V or VI > VDD + 0.5 V
VO < -0.5 V or VO > VDD + 0.5 V
-
±10
mA
V
VI
-0.5
VDD + 0.5
±10
IOK
II/O
IDD
Tstg
Tamb
Ptot
P
output clamping current
input/output current
supply current
-
mA
mA
mA
°C
-
-
±10
50
storage temperature
ambient temperature
total power dissipation
power dissipation
-65
-40
-
+150
+125
500
°C
Tamb = -40 °C to + 125 °C
per output
[1]
mW
mW
-
100
[1] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
VDD
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
0
-
-
-
-
-
-
VI
input voltage
VDD
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
-
+125 °C
VDD = 5 V
VDD = 10 V
VDD = 15 V
3.75
0.5
μs/V
-
μs/V
μs/V
-
0.08
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HEF4001B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
3 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
9. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min
3.5
7.0
11.0
-
Max
-
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level
input voltage
|IO| < 1 μA
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
-
7.0
-
7.0
-
7.0
-
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level
output voltage
4.95
9.95
4.95
4.95
4.95
10 V
-
9.95
-
9.95
-
9.95
-
15 V 14.95
-
14.95
-
14.95
-
14.95
-
LOW-level
output voltage
5 V
-
0.05
0.05
0.05
-1.7
-0.64
-1.6
-4.2
-
-
0.05
0.05
0.05
-1.4
-0.5
-1.3
-3.4
-
-
0.05
0.05
0.05
-1.1
-0.36
-0.9
-2.4
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
-
-
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
-
-
-1.1 mA
-0.36 mA
-0.9 mA
-2.4 mA
5 V
-
-
-
-
-
-
10 V
15 V
5 V
-
-
-
-
-
IOL
LOW-level
output current
0.64
1.6
4.2
-
0.5
1.3
3.4
-
0.36
0.9
2.4
-
0.36
0.9
2.4
-
-
-
-
mA
mA
mA
10 V
15 V
15 V
-
-
-
-
-
-
II
input leakage
current
±0.1
±0.1
±1.0
±1.0 μA
IDD
supply current all valid input 5 V
combinations;
-
-
-
-
0.25
0.5
1.0
-
-
-
-
-
0.25
0.5
-
-
-
-
7.5
15.0
30.0
-
-
-
-
-
7.5 μA
10 V
15 V
15.0 μA
30.0 μA
IO = 0 A
1.0
CI
input
7.5
-
pF
capacitance
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HEF4001B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
4 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
10. Dynamic characteristics
Table 7. Dynamic characteristics
Tamb = 25 °C unless otherwise specified.; for waveforms see Fig. 4; for test circuit see Fig. 5.
Symbol Parameter
Extrapolation formula [1] VDD
Min
Typ Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHL
tPLH
tTHL
tTLH
HIGH to LOW propagation delay
33 + 0.55 × CL
14 + 0.23 × CL
12 + 0.16 × CL
23 + 0.55 × CL
14 + 0.23 × CL
12 + 0.16 × CL
5 V
-
-
-
-
-
-
-
-
-
-
-
-
60
25
20
50
25
20
60
30
20
60
30
20
120
50
10 V
15 V
5 V
40
LOW to HIGH propagation delay
100
45
10 V
15 V
5 V
35
HIGH to LOW output transition time 10 + 1.00 × CL
120
60
9 + 0.42 × CL
10 V
15 V
5 V
6 + 0.28 × CL
LOW to HIGH output transition time 10 + 1.00 × CL
9 + 0.42 × CL
40
120
60
10 V
15 V
6 + 0.28 × CL
40
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter
VDD Typical formula
Where
PD
dynamic power dissipation 5 V PD = 1100 × fi + Σ(fo × CL) × VDD 2 (μW) fi = input frequency in MHz;
10 V PD = 5000 × fi + Σ(fo × CL) × VDD 2 (μW)
fo = output frequency in MHz;
CL = output load capacitance in pF;
Σ(fo × CL) = sum of the outputs;
15 V PD = 14200 × fi + Σ(fo × CL) × VDD 2 (μW)
VDD = supply voltage in V.
10.1. Waveforms and test circuit
t
t
f
r
V
I
90 %
input
V
M
10 %
0 V
t
t
PLH
PHL
V
OH
90 %
output
V
M
10 %
V
OL
t
t
THL
TLH
001aag197
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 4. Propagation delay, output transition time
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HEF4001B_Q100
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
5 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
Table 9. Measurement points
Supply voltage
Input
VM
Output
VM
VDD
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 5. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
©
HEF4001B_Q100
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
6 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig. 6. Package outline SOT108-1 (SO14)
©
HEF4001B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
7 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
12. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Military
HBM
MIL
MM
Machine Model
13. Revision history
Table 12. Revision history
Document ID
Release date
20211119
Data sheet status
Change notice
Supersedes
HEF4001B_Q100 v.2
Modifications
Product data sheet
-
HEF4001B_Q100 v.1
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 4: Derating values for Ptot total power dissipation updated.
Section 1 and Section 2 updated.
HEF4001B_Q100 v.1
20130220
Product data sheet
-
-
©
HEF4001B_Q100
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
8 / 10
Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
equipment, nor in applications where failure or malfunction of an Nexperia
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severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
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14. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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[1][2]
status [3]
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data sheet
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the objective specification for
product development.
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data sheet
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Production
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the preliminary specification.
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©
HEF4001B_Q100
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
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Nexperia
HEF4001B-Q100
Quad 2-input NOR gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description.............................................................2
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms and test circuit........................................ 5
11. Package outline.......................................................... 7
12. Abbreviations..............................................................8
13. Revision history..........................................................8
14. Legal information........................................................9
© Nexperia B.V. 2021. All rights reserved
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Date of release: 19 November 2021
©
HEF4001B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 19 November 2021
10 / 10
相关型号:
HEF4001BT-T
IC 4000/14000/40000 SERIES, QUAD 2-INPUT NOR GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14, Gate
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HEF4001BT/T3
IC 4000/14000/40000 SERIES, QUAD 2-INPUT NOR GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT-108-1, SOP-14, Gate
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