HEF4021B-Q100 [NEXPERIA]
8-bit static shift register;
| 型号： | HEF4021B-Q100 |
| 厂家： | 
Nexperia |
| 描述： | 8-bit static shift register |
| 文件： | 总15页 (文件大小：766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4021B-Q100
8-bit static shift register
Rev. 4 — 21 March 2016
Product data sheet
1. General description
The HEF4021B-Q100 is an 8-bit static shift register (parallel-to-serial converter). It has a
synchronous serial data input (DS), a clock input (CP) and an asynchronous active HIGH
parallel load input (PL). The HEF4021B-Q100 also has eight asynchronous parallel data
inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each
register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD)
input. Information on D0 to D7 is asynchronously loaded into the register while PL is
HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first
register position. All the data in the register is shifted one position to the right on the
LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant
of slower rise and fall times. It operates over a recommended VDD power supply range of
3 V to 15 V referenced to VSS (usually ground). Connect unused inputs must to VDD, VSS
or another input. This product has been qualified to the Automotive Electronics Council
(AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
,
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Tolerant of slower rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C.
Type number
Package
Name
Description
Version
HEF4021BT-Q100 SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SOT403-1
HEF4021BTT-Q100 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
HEF4021B-Q100
Nexperia
8-bit static shift register
4. Functional diagram
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Fig 1. Functional diagram
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Fig 2. Logic diagram
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
2 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
5. Pinning information
5.1 Pinning
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Fig 3. Pin configuration
5.2 Pin description
Table 2.
Symbol
Q5 to Q7
D0 to D7
VSS
Pin description
Pin
Description
2, 12, 3
buffered parallel output from the last three stages
parallel data input
7, 6, 5, 4, 13, 14,15, 1
8
ground supply voltage
PL
9
parallel load input
CP
10
11
16
clock input (LOW-to-HIGH edge-triggered)
serial data input
DS
VDD
supply voltage
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
3 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
6. Functional description
Table 3.
Function table[1]
Number of clock Inputs
Outputs
Q5
transitions
CP
DS
PL
Q6
Q7
Serial operation
1
2
3
6
7
8
data 1
L
L
L
L
L
L
L
X
X
X
data 2
X
X
X
data 3
X
X
X
X
X
X
X
data 1
data 2
data 3
no change
X
X
data 1
data 2
no change
X
data 1
no change
Parallel operation
X
X
H
D5
D6
D7
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW to HIGH clock transition; = HIGH to LOW clock transition;
data n = data (HIGH or LOW) on the DS input at the nth CP transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
Unit
V
supply voltage
+18
10
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
mA
V
VI
0.5
-
VDD + 0.5
10
IOK
output clamping current
input/output current
supply current
mA
mA
mA
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+125
C
Tamb 40 C to +125 C
SO16 and TSSOP16 package
per output
[1]
-
-
500
100
mW
mW
P
power dissipation
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
4 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
8. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
-
-
-
-
-
-
VI
input voltage
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit
Min
Max
Min
Max
-
Min
Max
Min
Max
VIH
HIGH-level
input voltage
IO < 1 A
5 V
3.5
-
-
3.5
3.5
-
-
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
7.0
7.0
-
7.0
7.0
11.0
-
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
IO < 1 A
IO < 1 A
IO < 1 A
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level
output
voltage
4.95
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
14.95
-
LOW-level
output
voltage
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
-
-
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
-
-
1.1 mA
0.36 mA
0.9 mA
2.4 mA
5 V
-
-
-
-
-
-
10 V
15 V
5 V
-
-
-
-
-
IOL
LOW-level
output current
0.64
1.6
4.2
-
0.5
1.3
3.4
-
0.36
0.9
2.4
-
0.36
0.9
2.4
-
-
-
-
mA
mA
mA
10 V
15 V
15 V
-
-
-
-
-
-
II
input leakage VDD = 15 V
current
0.1
0.1
1.0
1.0 A
IDD
supply
current
IO = 0 A
5 V
10 V
15 V
-
-
-
-
-
5
10
20
-
-
-
-
-
5
-
-
-
-
150
300
600
-
-
-
-
-
150 A
300 A
600 A
10
20
7.5
CI
input
-
pF
capacitance
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
5 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
10. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
Min Typ Max Unit
125 250 ns
[1]
[1]
[1]
tPHL
HIGH to LOW
CP to Qn
see Figure 4
98 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
93 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
88 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
78 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)C
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
propagation delay
10 V
15 V
5 V
55
40
110 ns
80 ns
PL to Qn
see Figure 4
120 240 ns
10 V
15 V
5 V
55
40
110 ns
80 ns
230 ns
100 ns
80 ns
tPLH
LOW to HIGH
CP to Qn
see Figure 4
115
50
propagation delay
10 V
15 V
5 V
40
PL to Qn
see Figure 4
105 210 ns
10 V
15 V
5 V
50
40
60
30
20
100 ns
80 ns
120 ns
60 ns
40 ns
tt
transition time
set-up time
Qn; see Figure 4
10 V
15 V
5 V
tsu
DS to CP;
see Figure 5
+25 15
+25 10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 V
15 V
5 V
+15
50
30
20
40
20
15
5
25
10
5
Dn to PL;
see Figure 6
10 V
15 V
5 V
th
hold time
DS to CP;
see Figure 5
20
10
8
10 V
15 V
5 V
Dn to PL;
see Figure 6
+15 10
10 V
15 V
5 V
15
15
70
30
24
70
30
24
50
40
35
0
0
tW
pulse width
CP = LOW;
minimum width;
see Figure 5
35
15
12
35
15
12
10
5
10 V
15 V
5 V
PL = HIGH;
minimum width;
see Figure 6
10 V
15 V
5 V
trec
recovery time
PL input;
see Figure 6
10 V
15 V
5
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
6 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
fclk(max) maximum clock
frequency
Conditions
VDD
5 V
Extrapolation formula
Min Typ Max Unit
CP input;
see Figure 5
6
13
30
40
-
-
-
MHz
MHz
MHz
10 V
15 V
15
20
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 900 fi + (fo CL) VDD
where:
2
PD
dynamic power
dissipation
fi = input frequency in MHz,
fo = output frequency in MHz,
2
10 V
15 V
PD = 4300 fi + (fo CL) VDD
2
CL = output load capacitance in pF,
VDD = supply voltage in V,
PD = 12000 fi + (fo CL) VDD
(fo CL) = sum of the outputs.
11. Waveforms
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Fig 4. Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times
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Fig 5. Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS.
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
7 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
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Set-up times and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in Table 9.
Fig 6.
Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL.
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
8 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
W
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b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
20 ns
50 pF
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
9 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
12. Package outline
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Fig 8. Package outline SOT109-1 (SO16)
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
10 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
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Fig 9. Package outline SOT403-1 (TSSOP16)
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
11 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
13. Abbreviations
Table 11. Abbreviations
Acronym
HBM
ESD
Description
Human Body Model
ElectroStatic Discharge
Machine Model
Military
MM
MIL
14. Revision history
Table 12. Revision history
Document ID
Release date
20160321
Data sheet status
Change notice
Supersedes
HEF4021B_Q100 v.4
Modifications:
Product data sheet
-
HEF4021B_Q100 v.3
• Type number HEF4021BP-Q100 (SOT38-4) removed.
HEF4021B_Q100 v.3
Modifications:
20130830
• HEF4021BTT-Q100 (TSSOP16) added.
20130220 Product data sheet
• HEF4021BP-Q100 (DIP16) added.
20120807 Product data sheet
Product data sheet
-
-
-
HEF4021B_Q100 v.2
HEF4021B_Q100 v.2
Modifications:
HEF4021B_Q100 v.1
-
HEF4021B_Q100 v.1
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
12 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
15.2 Definitions
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
15.3 Disclaimers
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia's aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
13 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
©
HEF4021B_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 21 March 2016
14 of 15
HEF4021B-Q100
Nexperia
8-bit static shift register
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 21 March 2016
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