HEF4040BT [NEXPERIA]
12-stage binary ripple counterProduction;
| 型号： | HEF4040BT |
| 厂家： | 
Nexperia |
| 描述： | 12-stage binary ripple counterProduction PC 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4040B
12-stage binary ripple counter
Rev. 10 — 7 December 2021
Product data sheet
1. General description
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter
advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and
forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Inputs
are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting
applications.
2. Features and benefits
•
Wide supply voltage range from 3.0 V to 15.0 V
•
•
•
•
•
•
•
•
CMOS low power dissipation
High noise immunity
Tolerant of slow clock rise and fall time
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
•
Specified from -40 °C to +85 °C
3. Applications
•
•
•
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Temperature range
Description
Version
HEF4040BT
-40 °C to +85 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
Nexperia
HEF4040B
12-stage binary ripple counter
5. Functional diagram
10
11
CP
T
12-STAGE COUNTER
MR
C
D
9
7
6
5
3
2
4
13 12 14 15
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig. 1. Functional diagram
FF 1
FF 2
FF 12
Q
Q
Q
CP
T
T
T
Q
Q
Q
CD
CD
CD
MR
Q0
Q1
Q11
001aae615
Fig. 2. Logic diagram
1
2
4
8
16
32
64 128 256 512 1024 2048 4096
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
001aad587
Fig. 3. Timing diagram
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
2 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
6. Pinning information
6.1. Pinning
HEF4040B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q11
Q5
Q4
Q6
Q3
Q2
Q1
V
DD
Q10
Q9
Q7
Q8
MR
CP
Q0
V
SS
001aae614
Fig. 4. Pin configuration SOT109-1 (SO16)
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
VSS
8
ground supply voltage
parallel output
Q0, Q1, Q2, Q3, Q4, Q5,
9, 7, 6, 5, 3, 2,
Q6, Q7, Q 8, Q9, Q10, Q11
4, 13, 12, 14, 15, 1
CP
10
11
16
clock input (HIGH-to-LOW edge-triggered)
master reset input (active HIGH)
supply voltage
MR
VDD
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
+18
Unit
V
supply voltage
-0.5
input clamping current
input voltage
VI < -0.5 V or VI > VDD + 0.5 V
VO < -0.5 V or VO > VDD + 0.5 V
-
±10
mA
V
VI
-0.5
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
-
mA
mA
mA
°C
II/O
-
-
±10
IDD
50
Tstg
Tamb
Ptot
P
storage temperature
ambient temperature
total power dissipation
power dissipation
-65
-40
-
+150
+85
°C
500
mW
mW
per output
-
100
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
3 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
8. Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
VDD
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
0
-
-
-
-
-
-
VI
input voltage
VDD
+85
3.75
0.5
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
-
°C
VDD = 5 V
VDD = 10 V
VDD = 15 V
ms/V
ms/V
ms/V
-
-
0.08
9. Static characteristics
Table 5. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = -40 °C
Tamb = +25 °C Tamb = +85 °C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level input voltage
|IO| < 1 μA
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
LOW-level input voltage
|IO| < 1 μA
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level output voltage |IO| < 1 μA
LOW-level output voltage |IO| < 1 μA
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
-
0.05
0.05
0.05
-1.7
-0.52
-1.3
-3.6
-
-
0.05
0.05
0.05
-1.4
-0.44
-1.1
-3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
HIGH-level output current VO = 2.5 V
VO = 4.6 V
-
-
-
-1.1 mA
-0.36 mA
-0.9 mA
-2.4 mA
5 V
-
-
-
VO = 9.5 V
10 V
15 V
5 V
-
-
-
VO = 13.5 V
-
-
-
IOL
LOW-level output current VO = 0.4 V
VO = 0.5 V
0.52
0.44
0.36
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
1.3
-
1.1
-
0.9
VO = 1.5 V
3.6
-
3.0
-
2.4
ILI
input leakage current
-
-
-
-
-
±0.3
20
40
80
-
-
-
-
-
-
±0.3
20
40
80
7.5
-
-
-
-
-
±1.0 μA
150 μA
300 μA
600 μA
IDD
supply current
IO = 0 A
10 V
15 V
-
CI
input capacitance
-
pF
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
4 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
10. Dynamic characteristics
Table 6. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; unless otherwise specified; for test circuit see Fig. 6.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula [1] Min
Typ
105
45
35
35
15
10
90
40
30
85
40
30
35
15
10
60
30
20
25
15
10
20
15
10
20
15
10
20
30
50
Max Unit
210 ns
90 ns
70 ns
70 ns
30 ns
20 ns
180 ns
80 ns
60 ns
170 ns
80 ns
60 ns
70 ns
30 ns
20 ns
120 ns
60 ns
40 ns
tPHL
HIGH to LOW
CP → Q0;
see Fig. 5
78 ns + (0.55 ns/pF)CL
34 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
[2] (0.55 ns/pF)CL
-
-
propagation delay
10 V
15 V
5 V
-
Qn → Qn + 1
-
10 V
15 V
5 V
[2] (0.23 ns/pF)CL
-
[2] (0.16 ns/pF)CL
-
MR → Qn;
see Fig. 5
63 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
58 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
[2] (0.55 ns/pF)CL
-
10 V
15 V
5 V
-
-
tPLH
LOW to HIGH
CP → Q0;
see Fig. 5
-
propagation delay
10 V
15 V
5 V
-
-
Qn → Qn + 1
see Fig. 5
-
10 V
15 V
5 V
[2] (0.23 ns/pF)CL
-
[2] (0.16 ns/pF)CL
-
tt
transition time
pulse width
[3] 10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
10 V
15 V
5 V
-
-
tW
CP input HIGH;
minimum width;
see Fig. 5
50
30
20
40
30
20
40
30
20
10
15
25
-
-
-
-
-
-
-
-
-
-
-
-
ns
10 V
15 V
5 V
ns
ns
MR input HIGH;
minimum width;
see Fig. 5
ns
10 V
15 V
5 V
ns
ns
trec
recovery time
MR input; see
Fig. 5
ns
10 V
15 V
5 V
ns
ns
fmax
maximum
frequency
CP input;
see Fig. 5
MHz
MHz
MHz
10 V
15 V
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] For loads other than 50 pF at the nth output, use the slope given.
[3] tt is the same as tTHL and tTLH
.
Table 7. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (μW)
where:
2
PD
dynamic power
dissipation
PD = 400 × fi + Σ(fo × CL) × VDD
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
2
2
10 V
15 V
PD = 2000 × fi + Σ(fo × CL) × VDD
PD = 5200 × fi + Σ(fo × CL) × VDD
Σ(fo × CL) = sum of the outputs.
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
5 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
10.1. Waveforms and test circuit
V
I
V
MR input
M
V
SS
t
1/f
W
max
t
rec
V
I
V
M
CP input
V
SS
t
W
t
t
t
PHL
PHL
OH
PLH
V
Q0 or Qn
output
V
M
V
OL
t
t
THL
TLH
t
t
PHL
PLH
V
OH
V
Qn + 1 output
M
V
OL
001aaj763
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 8.
Fig. 5. Waveforms showing the propagation delays, pulse widths, recovery times, maximum clock frequency,
and output transition times
Table 8. Measurement points
Supply voltage
VDD
Input
Output
VM
VI
VM
5 V to 15 V
VDD or VSS
0.5VDD
0.5VDD
t
W
V
I
90 %
90 %
negative
pulse
V
V
V
M
M
10 %
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
90 %
positive
pulse
V
M
M
10 %
10 %
0 V
t
W
001aaj781
a. Input waveforms
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
b. Test circuit
Test data is given in Table 9.
Definitions test circuit:
CL = load capacitance, including the jig and probe capacitance;
RL = load resistance, which should be equal to the output impedance of the pulse generator.
Fig. 6. Test circuit for measuring switching times
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
6 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
Table 9. Test data
Supply voltage
Input
Load
CL
VDD
VI
tr, tf
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
7 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 7. Package outline SOT109-1 (SO16)
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
8 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MM
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
13. Revision history
Table 11. Revision history
Document ID
HEF4040B v.10
Modifications:
Release date
20211207
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4040B v.9
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Section 12 added.
HEF4040B v.9
Modifications:
20160323
Product data sheet
-
HEF4040B v.8
HEF4040B v.7
•
Type number HEF4040BP (SOT38-4) removed.
HEF4040B v.8
Modifications:
20111117
Product data sheet
-
•
•
Legal pages updated.
Changes in Section 1 and Section 2.
HEF4040B v.7
20111010
20091125
20090709
20090304
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
-
HEF4040B v.6
HEF4040B v.5
HEF4040B v.4
HEF4040B_CNV v.3
HEF4040B_CNV v.2
-
HEF4040B v.6
HEF4040B v.5
HEF4040B v.4
HEF4040B_CNV v.3
HEF4040B_CNV v.2
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
9 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
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for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
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or problem which is based on any weakness or default in the customer’s
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[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
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the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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warranties as to the accuracy or completeness of information included herein
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with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
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customer (a) shall use the product without Nexperia’s warranty of the
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©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
10 / 11
Nexperia
HEF4040B
12-stage binary ripple counter
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................4
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms and test circuit........................................ 6
11. Package outline.......................................................... 8
12. Abbreviations..............................................................9
13. Revision history..........................................................9
14. Legal information......................................................10
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 7 December 2021
©
HEF4040B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 7 December 2021
11 / 11
相关型号：
HEF4040BT-Q100,118
Binary Counter, 4000/14000/40000 Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, PDSO16
NXP
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