HEF4046BT [NEXPERIA]
Phase-locked loopProduction;
| 型号： | HEF4046BT |
| 厂家： | 
Nexperia |
| 描述： | Phase-locked loopProduction 光电二极管 |
| 文件： | 总17页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4046B
Phase-locked loop
Rev. 7 — 6 January 2022
Product data sheet
1. General description
The HEF4046B is a phase-locked loop circuit that consists of a linear voltage controlled oscillator
(VCO) and two different phase comparators with a common signal input amplifier and a common
comparator input.
2. Features and benefits
•
Wide supply voltage range from 3.0 V to 15.0 V
•
•
•
•
•
•
•
CMOS low power dissipation
High noise immunity
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
•
Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
-40 °C to +85 °C
Name
Description
Version
HEF4046BT
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
Nexperia
HEF4046B
Phase-locked loop
4. Functional diagram
PHASE
COMPARATOR 1
14
3
2
PC1_OUT
SIG_IN
COMP_IN
13 PC2_OUT
PHASE
COMPARATOR 2
R3
÷ N
1
PCP
LOW-PASS
FILTER
VCO_OUT
C1A
4
6
7
9 VCO_IN
C2
10 SF_OUT
C1
SOURCE
FOLLOWER
C1B
V
SS
VCO
R1
R2
R1 11
R2 12
R
SF
V
SS
V
SS
5
INH
V
15
SS
(pin 8)
ZENER
001aae626
Fig. 1. Functional diagram
5. Pinning information
5.1. Pinning
HEF4046B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCP_OUT
PC1_OUT
COMP_IN
VCO_OUT
INH
V
DD
ZENER
SIG_IN
PC2_OUT
R2
C1A
R1
C1B
SF_OUT
VCO_IN
V
SS
001aae627
Fig. 2. Pin configuration SOT109-1 (SO16)
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
2 / 17
Nexperia
HEF4046B
Phase-locked loop
5.2. Pin description
Table 2. Pin description
Symbol
Pin
1
Description
PCP_OUT
PC1_OUT
COMP_IN
VCO_OUT
INH
phase comparator pulse output
phase comparator 1 output
comparator input
2
3
4
VCO output
5
inhibit input
C1A
6
capacitor C1 connection A
capacitor C1 connection B
ground supply voltage
VCO input
C1B
7
VSS
8
VCO_IN
SF_OUT
R1
9
10
11
12
13
14
15
16
source-follower output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
R2
PC2_OUT
SIG_IN
ZENER
VDD
Zener diode input for regulated supply
supply voltage
6. Functional description
6.1. VCO control
The VCO requires an external capacitor (C1) and resistor (R1) with an optional resistor (R2).
Resistor R1 and capacitor C1 determine the frequency range of the VCO, while resistor R2 enables
the VCO to have a frequency off-set if required. The high input impedance of the VCO simplifies
the design of low-pass filters; it permits the designer a wide choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided
at SF_OUT (pin 10). If this is used, a load resistor (RL) should be connected from SF_OUT to VSS
if unused, SF_OUT should be left open. The VCO output (pin 4) can either be connected directly
to the comparator input COMP_IN (pin 3) or via a frequency divider. A LOW-level at the inhibit
;
input INH_IN (pin 5) enables the VCO and the source follower, while a HIGH-level turns both off to
minimize standby power consumption.
6.2. Phase comparators
The phase-comparator signal input SIG_IN (pin 14) can be direct-coupled, provided the signal
swing is between the standard HE4000B family input logic levels. The signal must be capacitively
coupled to the self-biasing amplifier at the signal input with smaller swings. Phase comparator 1 is
an EXCLUSIVE-OR network. The signal and comparator input frequencies must have a 50% duty
factor to obtain the maximum lock range. The average output voltage of the phase comparator is
equal to 0.5VDD when there is no signal or noise at the signal input. The average voltage to the
VCO input VCO_IN is supplied by the low-pass filter connected to the output of phase comparator
1. This also causes the VCO to oscillate at the center frequency (f0). The frequency capture range
(2fC) is defined as the frequency range of input signals on which the PLL will lock if it was initially
out of lock. The frequency lock range (2fL) is defined as the frequency range of input signals on
which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the
lock range.
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
3 / 17
Nexperia
HEF4046B
Phase-locked loop
With phase comparator 1, the range of frequencies over which the PLL can acquire lock (capture
range) depends on the low-pass filter characteristics and this range can be made as large as the
lock range. Phase comparator 1 enables the PLL system to remain in lock in spite of high amounts
of noise in the input signal. A typical behavior of this type of phase comparator is that it may lock
onto input frequencies that are close to harmonics of the VCO center frequency. Another typical
behavior is that the phase angle between the signal and comparator input varies between 0°
and 180°, and is 90° at the center frequency. Fig. 3 shows the typical phase-to-output response
characteristic.
Fig. 4 shows the typical waveforms for a PLL with a f0 locked phase comparator 1.
(1)
V
DD
0.5V
DD
0
0°
90°
180°
001aae628
(1) Average output voltage.
Fig. 3. Signal-to-comparator inputs phase difference for comparator 1
SIG_IN
COMP_IN
VCO_OUT
PC1_OUT
VCO_IN
V
V
DD
SS
001aae629
Fig. 4. Typical waveforms for phase-locked loop with an f0 locked phase comparator 1
Phase comparator 2 is an edge-controlled digital memory network. It consists of four flip-flops,
control gating and a 3-state output circuit comprising p and n-type drivers with a common output
node. When the p-type or n-type drivers are ON, they pull the output up to VDD or down to VSS
respectively. This type of phase comparator only acts on the positive-going edges of the signals at
SIG_IN and COMP_IN. Therefore, the duty factors of these signals are not of importance.
If the signal input frequency is higher than the comparator input frequency, the p-type output
driver is maintained ON most of the time, and both the n and p-type drivers are OFF (3-state) the
remainder of the time. If the signal input frequency is lower than the comparator input frequency,
the n-type output driver is maintained ON most of the time, and both the n and p-type drivers are
OFF the remainder of the time. If the signal input and comparator input frequencies are equal,
but the signal input lags the comparator input in phase, the n-type output driver is maintained ON
for a time corresponding to the phase difference. If the comparator input lags the signal input in
phase, the p-type output driver is maintained ON for a time corresponding to the phase difference.
Subsequently, the voltage at the capacitor of the low-pass filter connected to this phase comparator
is adjusted until the signal and comparator inputs are equal in both phase and frequency. At this
stable point, both p and n-type drivers remain OFF and thus the phase comparator output becomes
an open circuit and keeps the voltage at the capacitor of the low-pass filter constant.
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
4 / 17
Nexperia
HEF4046B
Phase-locked loop
Moreover, the signal at the phase comparator pulse output (PCP_OUT) is a HIGH level, which
can be used for indicating a locked condition. Thus, for phase comparator 2, no phase difference
exists between the signal and comparator inputs over the full VCO frequency range. Moreover,
the power dissipation due to the low-pass filter is reduced when this type of phase comparator is
used, because both p and n-type output drivers are OFF for most of the signal input cycle. It should
be noted that the PLL lock range for this type of phase comparator is equal to the capture range,
independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to
its lowest frequency for phase comparator 2. Fig. 5 shows typical waveforms for a PLL employing
this type of locked phase comparator.
SIG_IN
COMP_IN
VCO_OUT
V
V
DD
SS
PC2_OUT
VCO_IN
high impedance OFF-state
PCP_OUT
001aae630
Fig. 5. Typical waveforms for phase-locked loop with a locked phase comparator 2
Fig. 6 shows the state diagram for phase comparator 2. Each circle represents a state of the
comparator. The number at the top, inside each circle, represents the state of the comparator, while
the logic state of the signal and comparator inputs are represented by a ‘0’ for a logic LOW or a ‘1’
for a logic HIGH, and they are shown in the left and right bottom of each circle.
The transitions from one to another result from either a logic change at the signal input (S
representing SIG_IN) or the comparator input (C representing COMP_IN). A positive- going and a
negative-going transition are shown by an arrow pointing up or down respectively.
The state diagram assumes, that only one transition on either the signal input or comparator input
occurs at any instant.
•
•
•
States 3, 5, 9 and 11 represent the output condition when the p-type driver is ON.
States 2, 4, 10 and 12 determine the condition when the n-type driver is ON.
States 1, 6, 7 and 8 represent the condition when the output is in its high-impedance OFF state;
i.e. both p and n-type drivers are OFF, and the PCP_OUT output is HIGH. The condition at
output PCP_OUT for all other states is LOW.
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
5 / 17
Nexperia
HEF4046B
Phase-locked loop
1
0
0
C
S
S
C
C
C
S
S
4
2
3
5
0
0
0
1
1
0
0
0
S
C
S
C
C
S
7
8
6
0
1
1
0
1
1
S
1
S
C
C
C
S
C
C
S
S
11
9
10
12
0
1
1
1
1
1
0
n-type driver ON
p-type driver ON
state number of
the comparator
n
n and p-type
drivers are OFF
0
0
logic state of
comparator input (pin 3)
001aae631
logic state of
signal input (pin 14)
S ↑: 0 to 1 transition at the signal input SIG_IN.
C ↓: 1 to 0 transition at the comparator input COMP_IN.
Fig. 6. State diagram for comparator 2
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
Unit
supply voltage
-0.5
+18
±10
V
input clamping current
input voltage
VI < -0.5 V or VI > VDD + 0.5 V
VO < -0.5 V or VO > VDD + 0.5 V
-
mA
V
VI
-0.5
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
-
mA
mA
mA
°C
II/O
-
-
±10
IDD
50
Tstg
Tamb
Ptot
P
storage temperature
ambient temperature
total power dissipation
power dissipation
-65
-40
-
+150
+85
°C
-40 °C to +85 °C
per output
500
mW
mW
-
100
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
6 / 17
Nexperia
HEF4046B
Phase-locked loop
8. Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
Parameter
Conditions
Min
3
Typ
Max
15
Unit
V
VDD
supply voltage
-
-
-
-
-
as fixed oscillator only
3
15
V
phase-locked loop operation
5
15
V
VI
input voltage
0
VDD
+85
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
°C
for INH input
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
-
-
-
3.75
0.5
μs/V
μs/V
μs/V
0.08
9. Static characteristics
Table 5. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level
input voltage
|IO| < 1 μA
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level
output voltage
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
LOW-level
output voltage
-
0.05
0.05
0.05
-1.7
-0.52
-1.3
-3.6
-
-
0.05
0.05
0.05
-1.4
-0.44
-1.1
-3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
-1.1 mA
-0.36 mA
-0.9 mA
-2.4 mA
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level output
current
0.52
1.3
3.6
-
0.44
1.1
3.0
-
0.36
0.9
2.4
-
-
-
-
mA
mA
mA
10 V
15 V
15 V
15 V
-
-
-
-
II
input leakage current
±0.3
1.6
±0.3
1.6
±1.0 μA
12.0 μA
IOZ
OFF-state
output current
output HIGH and
returned to VDD
-
-
-
output LOW and
returned to VSS
15 V
-
1.6
-
1.6
-
12.0 μA
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
7 / 17
Nexperia
HEF4046B
Phase-locked loop
Symbol Parameter
Conditions
VDD
Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min
Max
Min
Max
-
Min
Max
IDD
supply current
IO = 0 A
5 V
[1]
[1]
[1]
[2]
[2]
[2]
-
-
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
-
-
μA
μA
μA
10 V
15 V
5 V
300
-
-
750
-
20
40
80
-
-
-
-
-
20
40
80
7.5
150 μA
300 μA
600 μA
10 V
15 V
CI
input capacitance
for INH input
-
pF
[1] Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 open.
[2] Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 at VDD; input current at pin 14 not included.
10. Dynamic characteristics
Table 6. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤20 ns.
Symbol Parameter
Phase comparators
Conditions
VDD
Min
Typ
Max Unit
RI
input resistance
SIG_IN input; at self-bias operating point 5 V
10 V
15 V
SIG_IN input, AC coupled, peak-to-peak 5 V
-
750
220
140
150
150
200
-
-
kΩ
kΩ
kΩ
mV
mV
mV
V
-
-
-
-
Vi(sens)
VIL
VIH
IIH
input voltage
sensitivity
-
-
values; R1 = 10 kΩ; R2 = ∞; C1 = 100 pF;
independent of the lock range
10 V
15 V
5 V
-
-
-
-
LOW-level input
voltage
SIG_IN and COMP_IN inputs, DC
coupled LOW; full temperature range
-
1.5
10 V
15 V
5 V
-
-
3.0
V
-
-
4.0
V
HIGH-level input
voltage
SIG_IN and COMP_IN inputs, DC
3.5
-
-
-
-
-
-
-
-
-
-
V
coupled HIGH; full temperature range
10 V
15 V
5 V
7.0
-
V
11.0
-
V
HIGH-level input
current
SIG_IN input; at VDD
SIG_IN input; at VSS
-
-
-
-
-
-
7
μA
μA
μA
μA
μA
μA
10 V
15 V
5 V
30
70
-3
IIL
LOW-level input
current
10 V
15 V
-18
-45
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HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
8 / 17
Nexperia
HEF4046B
Phase-locked loop
Symbol Parameter
VCO
Conditions
VDD
Min
Typ
Max Unit
P
power dissipation
f0 = 10 kHz; R1 = 1 MΩ; R2 = ∞;
5 V
-
-
150
2500
9000
1.0
-
-
-
-
-
-
-
μW
VCO_IN at 0.5 VDD
;
10 V
15 V
5 V
μW
see Fig. 10, Fig. 11, and Fig. 12
-
μW
fmax
Δf/ΔT
maximum frequency VCO_IN at VDD; R1 = 10 kΩ; R2 = ∞;
C1 = 50 pF
0.5
1.0
1.3
-
MHz
MHz
MHz
% Hz/°C
10 V
15 V
5 V
2.0
2.7
frequency variation
with temperature
no frequency offset (fmin = 0 Hz)
[1]
0.22 to
0.30
10 V [1]
15 V [1]
-
-
-
-
-
0.04 to
0.05
-
-
-
-
-
% Hz/°C
% Hz/°C
% Hz/°C
% Hz/°C
% Hz/°C
0.01 to
0.05
with frequency offset (fmin > 0 Hz)
5 V
[1]
0 to
0.22
10 V [1]
15 V [1]
0 to
0.04
0 to
0.01
Δf/f
relative frequency
variation
for VCO see Fig. 13 and Fig. 14
R1 > 10 kΩ
5 V
-
-
-
-
-
-
0.50
0.25
0.25
50
-
-
-
-
-
-
% Hz
% Hz
% Hz
%
R1 > 400 kΩ
10 V
15 V
5 V
R1 = 1 MΩ
δ
duty factor
VCO _OUT output
10 V
15 V
50
%
50
%
Rin
input resistance
for pin VCO_IN
10
MΩ
Source follower
Voffset offset voltage
RL = 10 kΩ; VCO_IN at 0.5VDD
5 V
[2]
-
-
-
-
-
-
-
-
-
1.7
2.0
2.1
1.5
1.7
1.8
0.3
1.0
1.3
-
-
-
-
-
-
-
-
-
V
10 V
15 V
5 V
V
V
RL = 50 kΩ; VCO_IN at 0.5VDD
V
10 V
15 V
5 V
V
V
Δf/f
relative frequency
variation
VCO output; RL > 50 kΩ; see Fig. 13
%
%
%
10 V
15 V
Zener diode
VZ
working voltage
dynamic resistance
IZ = 50 μA
-
-
-
-
7.3
25
-
-
V
Rdyn
For internal zener diode; IZ = 1 mA
Ω
[1] Over the recommended component range.
[2] The offset voltage is equal to the input voltage on pin VCO_IN minus the output voltage on pin SF_OUT.
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
9 / 17
Nexperia
HEF4046B
Phase-locked loop
11. Design information
Table 7. Design information
Test
Using phase comparator 1
Using phase comparator 2
VCO adjusts with no signal on SIG_IN
VCO in PLL system adjusts to center VCO in PLL system adjusts to
frequency (f0)
minimum frequency (fmin
)
Phase angle between SIG_IN and COMP_IN 90° at center frequency (f0),
always 0° in lock
approaching 0° and 180° at the ends (positive-going edges)
of the lock range (2fL)
Locks on harmonics of center frequency
Signal input noise rejection
yes
no
high
low
Lock frequency range (2fL)
the frequency range of the input signal on which the loop will stay locked if
it was initially in lock; 2fL = full VCO frequency range = fmax - fmin
Capture frequency range (2fc)
Center frequency (f0)
the frequency range of the input signal on which the loop will lock if it was
initially out of lock
depends on low-pass filter
characteristics; 2fc < 2fL
2fc = 2fL
the frequency of the VCO when VCO_IN at 0.5VDD
11.1. VCO component selection
Recommended range for R1 and R2: 10 kΩ to 1 MΩ.
Recommended range for C1: 50 pF to any practical value.
1. VCO without frequency offset (R2 = ∞).
a. Given f0: use f0 with Fig. 7 to determine R1 and C1.
b. Given fmax: calculate f0 from f0 = 0.5fmax
;
use f0 with Fig. 7 to determine R1 and C1.
2. VCO with frequency offset.
a. Given f0 and 2fL : calculate fmin from the equation fmin = f0 − 2fL;
use fmin with Fig. 8 to determine R2 and C1;
calculate
use
from the equation
;
with Fig. 9 to determine the ratio R2/R1 to obtain R1.
b. Given fmin and fmax: use fmin with Fig. 8 to determine R2 and C1;
calculate
use
;
with Fig. 9 to determine R2/R1 to obtain R1.
©
HEF4046B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 7 — 6 January 2022
10 / 17
Nexperia
HEF4046B
Phase-locked loop
001aae632
001aae633
7
7
6
5
4
10
10
10
10
10
10
10
f
f
o
min
(Hz)
(Hz)
6
5
4
10
10
10
10
10
(1)
(1)
(2)
(3)
(4)
(5)
(6)
(2)
(3)
(4)
(5)
(6)
3
2
3
2
(7)
(8)
(9)
(7)
(8)
(9)
10
1
10
1
2
3
4
5
6
7
2
3
4
5
6
7
10
10
10
10
10
10
10
10
10
10
10
10
10
10
C1 (pF)
C1 (pF)
Tamb = 25 °C; VCO_IN at 0.5VDD; INH_IN at VSS
;
Tamb = 25 °C; VCO_IN at VSS; INH_IN at VSS
;
R2 = ∞.
R1 = ∞.
Lines (1), (4), and (7): VDD = 15 V;
Lines (2), (5), and (8): VDD = 10 V;
Lines (3), (6), and (9): VDD = 5 V;
Lines (1), (2), and (3): R1 = 10 kΩ;
Lines (4), (5), and (6): R1 = 100 kΩ;
Lines (7), (8), and (9): R1 = 1 MΩ.
Lines (1), (4), and (7): VDD = 15 V;
Lines (2), (5), and (8): VDD = 10 V;
Lines (3), (6), and (9): VDD = 5 V;
Lines (1), (2), and (3): R2 = 10 kΩ;
Lines (4), (5), and (6): R2 = 100 kΩ;
Lines (7), (8), and (9): R2 = 1 MΩ.
Fig. 7. Typical center frequency as a function of
capacitor C1
Fig. 8. Typical frequency offset as a function of
capacitor C1
001aae635
5
10
P
(µW)
(1)
001aae634
2
10
4
(2)
(3)
10
10
10
R2
R1
(4)
(1)
(2)
10
3
2
(5)
(6)
1
- 1
10
10
2
3
1
10
10
10
R1 (kΩ)
- 2
10
R2 = ∞; VCO_IN at 0.5VDD; CL = 50 pF.
2
3
1
10
10
10
Lines (1) and (2): VDD = 15 V;
Lines (3) and (4): VDD = 10 V;
Lines (5) and (6): VDD = 5 V;
Lines (1), (3), and (5): C1 = 50 pF;
Lines (2), (4), and (6): C1 = 1 μF.
f
/f
max max
Line (1): VDD = 5 V;
Line (2): VDD = 10 V, 15 V.
Fig. 9. Typical ratio of R2/R1 as a function of the ratio
fmax/fmin
Fig. 10. Power dissipation as a function of R1
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11 / 17
Nexperia
HEF4046B
Phase-locked loop
001aae636
6
10
001aae637
4
3
2
10
P
(µW)
P
(µW)
5
10
10
(1)
(2)
(1)
4
10
(2)
(3)
10
(3)
(4)
3
10
10
1
(5)
(6)
2
10
2
3
1
10
10
10
R2 (kΩ)
2
3
1
10
10
10
R
SF
(kΩ)
R1 = ∞; VCO_IN at VSS (0 V); CL = 50 pF.
VCO_IN at 0.5VDD; R1 = ∞; R2 = ∞.
Lines (1) and (2): VDD = 15 V;
Lines (3) and (4): VDD = 10 V;
Lines (5) and (6): VDD = 5 V;
Lines (1), (3), and (5): C1 = 50 pF;
Lines (2), (4), and (6): C1 = 1 μF.
Line (1): VDD = 15 V;
Line (2): VDD = 10 V;
Line (3): VDD = 5 V.
Fig. 12. Power dissipation of source follower as a
function of RL
Fig. 11. Power dissipation as a function of R2
f
f
max
f
2
f
o
f '
o
f
1
ΔV
ΔV
1/2V
V
DD
DD
V
VCO IN
001aae638
See Section 10.
For VCO linearity:
This figure and the above formula also apply to source follower linearity: substitute VO at SF_OUT for f.
ΔV = 0.3 V at VDD = 5 V;
ΔV = 2.5 V at VDD = 10 V;
ΔV = 5.0 V at VDD = 15 V.
Fig. 13. Definition of linearity
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Nexperia
HEF4046B
Phase-locked loop
001aae639
001aae640
0.5
5
0
(1)
(2)
lin
(%)
lin
(%)
(1)
0
(2)
(3)
(3)
(4)
(4)
- 0.5
- 5
- 1
10
- 10
2
3
2
3
10
10
10
10
10
R1 (kΩ)
R1 (kΩ)
a. VDD = 5 V
b. VDD = 10 V
001aae641
5
0
lin
(%)
(1)
(2)
(3)
(4)
- 5
- 10
2
3
10
10
10
R1 (kΩ)
c. VDD = 15 V
R2 = ∞;
Line (1): C1 = 1 μF;
Line (2): C1 = 1 nF;
Line (3): C1 = 100 pF;
Line (4): C1 = 50 pF.
Fig. 14. VCO frequency linearity as a function of R1
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Product data sheet
Rev. 7 — 6 January 2022
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Nexperia
HEF4046B
Phase-locked loop
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 15. Package outline SOT109-1 (SO16)
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14 / 17
Nexperia
HEF4046B
Phase-locked loop
13. Abbreviations
Table 8. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MM
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
PLL
Phase-Locked Loop
14. Revision history
Table 9. Revision history
Document ID
HEF4046B v.7
Modifications:
Release date
20220106
Data sheet status
Change notice
Supersedes
HEF4046B v.6
Product data sheet
-
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated .
Table 6 and Section 11.1: errata.
Section 13 added.
HEF4046B v.6
Modifications:
20160324
Type number HEF4046BP (SOT38-4) removed.
20111118 Product data sheet
Section Applications removed
Product data sheet
-
HEF4046B v.5
HEF4046B v.4
•
HEF4046B v.5
Modifications:
-
•
•
•
Table 5: IOH minimum values changed to maximum
Table 6: Rin typical value changed from 106 MΩ to 10 MΩ
HEF4046B v.4
20100105
19950101
19950101
Product data sheet
Product specification
Product specification
-
-
-
HEF4046B_CNV v.3
HEF4046B_CNV v.3
HEF4046B_CNV v.2
HEF4046B_CNV v.2
-
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Product data sheet
Rev. 7 — 6 January 2022
15 / 17
Nexperia
HEF4046B
Phase-locked loop
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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sold subject to the general terms and conditions of commercial sale, as
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terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
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Export control — This document as well as the item(s) described herein
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Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
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Non-automotive qualified products — Unless this data sheet expressly
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accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
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or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
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In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
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Nexperia
HEF4046B
Phase-locked loop
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description.............................................................3
6. Functional description................................................. 3
6.1. VCO control.................................................................3
6.2. Phase comparators......................................................3
7. Limiting values............................................................. 6
8. Recommended operating conditions..........................7
9. Static characteristics....................................................7
10. Dynamic characteristics............................................ 8
11. Design information................................................... 10
11.1. VCO component selection....................................... 10
12. Package outline........................................................ 14
13. Abbreviations............................................................15
14. Revision history........................................................15
15. Legal information......................................................16
© Nexperia B.V. 2022. All rights reserved
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For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 6 January 2022
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17 / 17
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IC 4000/14000/40000 SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14, Prescaler/Multivibrator
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