HEF4520BT [NEXPERIA]

Dual binary counterProduction;
HEF4520BT
型号: HEF4520BT
厂家: Nexperia    Nexperia
描述:

Dual binary counterProduction

PC 输入元件 光电二极管 逻辑集成电路 触发器
文件: 总12页 (文件大小:214K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HEF4520B  
Dual binary counter  
Rev. 8 — 1 March 2022  
Product data sheet  
1. General description  
The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0  
and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master  
reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1  
is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be  
used as the clock input to the counter and the other clock input may be used as a clock enable  
input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1.  
Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to  
voltages in excess of VDD  
.
2. Features and benefits  
Tolerant of slow clock rise and fall times  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Wide supply voltage range from 3.0 V to 15.0 V  
CMOS low power dissipation  
High noise immunity  
Standardized symmetrical output characteristics  
Complies with JEDEC standard JESD 13-B  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
Specified from -40 °C to +85 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +85 °C  
Name  
Description  
Version  
HEF4520BT  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
 
 
 
Nexperia  
HEF4520B  
Dual binary counter  
4. Functional diagram  
1Q0  
1Q1  
1Q2  
1Q3  
3
4
5
6
1
2
1CP0  
1CP1  
7
9
1MR  
2Q0 11  
2Q1 12  
2Q2 13  
2Q3 14  
2CP0  
10 2CP1  
15 2MR  
001aae698  
Fig. 1. Functional diagram  
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18  
nCP0  
nCP1  
nMR  
1
10 11 12 13 14 15  
0
1
2
3
4
nQ0  
nQ1  
nQ2  
nQ  
3
001aae707  
Fig. 2. Timing diagram  
nQ0  
nQ1  
nQ2  
nQ3  
Q
Q
Q
Q
Q
Q
Q
FF 1  
CD  
FF 2  
CD  
FF 3  
CD  
FF 4  
nCP1  
nCP0  
T
T
T
T
Q
CD  
nMR  
001aae705  
Fig. 3. Logic diagram for one counter  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
2 / 12  
 
Nexperia  
HEF4520B  
Dual binary counter  
5. Pinning information  
5.1. Pinning  
HEF4520B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1CP0  
1CP1  
1Q0  
V
DD  
2MR  
2Q3  
1Q1  
2Q2  
1Q2  
2Q1  
1Q3  
2Q0  
1MR  
2CP1  
2CP0  
V
SS  
001aae704  
Fig. 4. Pin configuration SOT109-1 (SO16)  
5.2. Pin description  
Table 2. Pin description  
Symbol  
Pin  
Description  
1CP0, 2CP0  
1CP1, 2CP1  
1Q0, 1Q1, 1Q2, 1Q3  
1MR, 2MR  
1, 9  
clock input (LOW-to-HIGH triggered)  
clock input (HIGH-to-LOW triggered)  
output  
2, 10  
3, 4, 5, 6  
7, 15  
master reset input  
VSS  
8
ground supply voltage  
output  
2Q0, 2Q1, 2Q2, 2Q3  
VDD  
11, 12, 13, 14  
16  
supply voltage  
6. Functional description  
Table 3. Function table  
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.  
nCP0  
nCP1  
nMR  
Mode  
H
L
L
L
L
L
L
H
counter advances  
counter advances  
no change  
L
X
X
no change  
L
no change  
H
X
no change  
X
nQ0 to nQ3 = LOW  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
3 / 12  
 
 
 
 
Nexperia  
HEF4520B  
Dual binary counter  
7. Limiting values  
Table 4. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).  
Symbol Parameter  
Conditions  
Min  
Max  
+18  
Unit  
V
VDD  
IIK  
supply voltage  
-0.5  
input clamping current  
input voltage  
VI < -0.5 V or VI > VDD + 0.5 V  
VO < -0.5 V or VO > VDD + 0.5 V  
-
±10  
mA  
V
VI  
-0.5  
VDD + 0.5  
±10  
IOK  
II/O  
IDD  
Tstg  
Tamb  
Ptot  
P
output clamping current  
input/output current  
supply current  
-
mA  
mA  
mA  
°C  
-
-
±10  
50  
storage temperature  
ambient temperature  
total power dissipation  
power dissipation  
per output  
-65  
-40  
-
+150  
+85  
°C  
SO16 package  
500  
mW  
mW  
-
100  
8. Recommended operating conditions  
Table 5. Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
VDD  
VI  
supply voltage  
3
0
-
-
-
-
-
-
15  
V
input voltage  
VDD  
+85  
V
Tamb  
Δt/ΔV  
ambient temperature  
in free air  
-40  
-
°C  
input transition rise and fall rate VDD = 5 V  
3.75 μs/V  
0.5 μs/V  
0.08 μs/V  
VDD = 10 V  
VDD = 15 V  
-
-
9. Static characteristics  
Table 6. Static characteristics  
VSS = 0 V; VI = VSS or VDD unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
Tamb = -40 °C  
Tamb = 25 °C  
Tamb = 85 °C Unit  
Min  
3.5  
7.0  
11.0  
-
Max  
Min  
Max  
Min  
Max  
VIH  
HIGH-level input  
voltage  
|IO| < 1 μA  
5 V  
-
-
3.5  
-
-
3.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V  
15 V  
5 V  
7.0  
7.0  
-
11.0  
-
11.0  
-
VIL  
LOW-level input  
voltage  
|IO| < 1 μA  
1.5  
3.0  
4.0  
-
-
1.5  
3.0  
4.0  
-
-
1.5  
3.0  
4.0  
-
10 V  
15 V  
5 V  
-
-
-
-
-
-
VOH  
HIGH-level output  
voltage  
|IO| < 1 μA;  
VI = VSS or VDD  
4.95  
9.95  
4.95  
4.95  
10 V  
-
9.95  
-
9.95  
-
15 V 14.95  
-
14.95  
-
14.95  
-
VOL  
LOW-level output  
voltage  
|IO| < 1 μA;  
VI = VSS or VDD  
5 V  
-
-
-
0.05  
0.05  
0.05  
-
-
-
0.05  
0.05  
0.05  
-
-
-
0.05  
0.05  
0.05  
10 V  
15 V  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
4 / 12  
 
 
 
 
Nexperia  
HEF4520B  
Dual binary counter  
Symbol Parameter  
Conditions  
VDD  
Tamb = -40 °C  
Tamb = 25 °C  
Tamb = 85 °C Unit  
Min  
Max  
-1.7  
-0.52  
-1.3  
-3.6  
-
Min  
Max  
-1.4  
-0.44  
-1.1  
-3.0  
-
Min  
Max  
IOH  
HIGH-level output  
current  
VO = 2.5 V  
VO = 4.6 V  
VO = 9.5 V  
VO = 13.5 V  
VO = 0.4 V  
VO = 0.5 V  
VO = 1.5 V  
VDD = 15 V  
5 V  
-
-
-
-1.1 mA  
-0.36 mA  
-0.9 mA  
-2.4 mA  
5 V  
-
-
-
10 V  
15 V  
5 V  
-
-
-
-
-
-
IOL  
LOW-level output  
current  
0.52  
0.44  
0.36  
-
-
-
mA  
mA  
mA  
10 V  
15 V  
15 V  
5 V  
1.3  
-
1.1  
-
0.9  
3.6  
-
3.0  
-
2.4  
II  
input leakage current  
supply current  
-
-
-
-
-
±0.3  
20  
-
-
-
-
-
±0.3  
20  
-
-
-
-
-
±1.0 μA  
150 μA  
300 μA  
600 μA  
IDD  
IO = 0 A;  
VI = VSS or VDD  
10 V  
15 V  
-
40  
40  
80  
80  
CI  
input capacitance  
-
7.5  
-
pF  
10. Dynamic characteristics  
Table 7. Dynamic characteristics  
VSS = 0 V; Tamb = 25 °C; unless otherwise specified. For test circuit see Fig. 6.  
Symbol Parameter  
Conditions  
VDD Extrapolation formula [1]  
Min  
Typ  
Max Unit  
220 ns  
100 ns  
tPHL  
HIGH to LOW  
nCP0, nCP1 to nQn;  
5 V 83 ns + (0.55 ns/pF)CL  
10 V 39 ns + (0.23 ns/pF)CL  
15 V 32 ns + (0.16 ns/pF)CL  
-
-
110  
50  
40  
75  
35  
25  
110  
50  
40  
60  
30  
20  
30  
15  
10  
30  
15  
10  
15  
10  
8
propagation delay see Fig. 5  
-
80  
ns  
nMR to nQn; see Fig. 5 5 V 48 ns + (0.55 ns/pF)CL  
10 V 24 ns + (0.23 ns/pF)CL  
-
150 ns  
-
70  
50  
ns  
ns  
15 V 17 ns + (0.16 ns/pF)CL  
-
tPLH  
LOW to HIGH  
nCP0, nCP1 to nQn;  
5 V 83 ns + (0.55 ns/pF)CL  
-
220 ns  
100 ns  
propagation delay see Fig. 5  
10 V 39 ns + (0.23 ns/pF)CL  
-
15 V 32 ns + (0.16 ns/pF)CL  
-
80  
ns  
tt  
transition time  
pulse width  
nQn; see Fig. 5  
5 V 10 ns + (1.00 ns/pF)CL  
-
120 ns  
10 V 9 ns + (0.42 ns/pF)CL  
-
60  
40  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
15 V 6 ns + (0.28 ns/pF)CL  
-
tW  
nCP0 input LOW;  
minimum width;  
see Fig. 5  
5 V  
60  
30  
20  
60  
30  
20  
30  
20  
16  
10 V  
15 V  
5 V  
-
-
nCP1 input HIGH;  
minimum width;  
see Fig. 5  
-
10 V  
15 V  
5 V  
-
-
nMR input HIGH;  
minimum width;  
see Fig. 5  
-
10 V  
15 V  
-
-
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
5 / 12  
 
Nexperia  
HEF4520B  
Dual binary counter  
Symbol Parameter  
Conditions  
VDD Extrapolation formula [1]  
Min  
50  
30  
20  
50  
30  
20  
50  
30  
20  
8
Typ  
25  
15  
10  
25  
15  
10  
25  
15  
10  
16  
30  
40  
Max Unit  
tsu  
set-up time  
nCP0 to nCP1;  
see Fig. 5  
5 V  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
10 V  
15 V  
5 V  
ns  
ns  
nCP1 to nCP0;  
see Fig. 5  
ns  
10 V  
15 V  
5 V  
ns  
ns  
trec  
recovery time  
see Fig. 5  
ns  
10 V  
15 V  
ns  
ns  
fmax  
maximum  
frequency  
nCP0, nCP1; see Fig. 5 5 V  
10 V  
15 V  
MHz  
MHz  
MHz  
15  
20  
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).  
Table 8. Dynamic power dissipation PD  
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.  
Symbol Parameter  
VDD  
5 V  
Typical formula for PD (μW)  
Where:  
2
PD  
dynamic power  
dissipation  
PD = 850 × fi + Σ(fo × CL) × VDD  
fi = input frequency in MHz,  
fo = output frequency in MHz,  
CL = output load capacitance in pF,  
VDD = supply voltage in V,  
2
10 V  
15 V  
PD = 3800 × fi + Σ(fo × CL) × VDD  
2
PD = 10200 × fi + Σ(fo × CL) × VDD  
Σ(fo × CL) = sum of the outputs.  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
6 / 12  
 
Nexperia  
HEF4520B  
Dual binary counter  
10.1. Waveforms and test circuit  
V
I
V
nCP0 input  
0 V  
M
V
I
nCP1 input  
0 V  
V
M
0 V  
t
t
su  
su  
V
I
nMR input  
0 V  
V
M
t
t
t
PHL  
PHL  
PLH  
V
OH  
90 %  
nQn output  
V
M
10 %  
V
OL  
t
t
t
t
001aae702  
a. nCP0 and nCP1 set-up times, propagation delays and output transition times  
1/f  
max  
V
I
nCP1 input  
(nCP0 = LOW)  
V
V
M
0 V  
t
t
W
V
I
nCP0 input  
(nCP1 = HIGH)  
M
0 V  
W
V
I
V
nMR input  
0 V  
M
t
W
t
rec  
001aae701  
b. nMR recovery time, minimum nCP0, nCP1, and nMR pulse widths and maximum frequency  
Measurement points are given in Table 9.  
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.  
Fig. 5. Waveforms showing measurements for switching times  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
7 / 12  
 
 
Nexperia  
HEF4520B  
Dual binary counter  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
90 %  
positive  
pulse  
V
M
M
10 %  
10 %  
0 V  
t
W
001aaj781  
a. Input waveforms  
V
DD  
V
V
O
I
G
DUT  
C
L
R
T
001aag182  
b.Test circuit  
Test data is given in Table 9.  
Definitions for test circuit:  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
Fig. 6. Test circuit for measuring switching times  
Table 9. Measurement points and test data  
Supply voltage  
VDD  
Input  
VI  
Load  
CL  
VM  
tr, tf  
5 V to 15 V  
VDD  
0.5 × VI  
≤ 20 ns  
50 pF  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
8 / 12  
 
 
Nexperia  
HEF4520B  
Dual binary counter  
11. Package outline  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
c
y
H
v
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.1  
0.25  
0.01  
8o  
0o  
0.0100  
0.0075  
0.010 0.057  
0.004 0.049  
0.019  
0.014  
0.39  
0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig. 7. Package outline SOT109-1 (SO16)  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
9 / 12  
 
Nexperia  
HEF4520B  
Dual binary counter  
12. Abbreviations  
Table 10. Abbreviations  
Acronym  
CDM  
DUT  
Description  
Charged Device Model  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
ESD  
HBM  
MM  
13. Revision history  
Table 11. Revision history  
Document ID  
HEF4520B v.8  
Modifications:  
Release date  
20220301  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
HEF4520B v.7  
The format of this data sheet has been redesigned to comply with the identity guidelines of  
Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
Section 1, Section 2, and Section 12 updated.  
HEF4520B v.7  
Modifications:  
20160330  
Type number HEF4520BP (SOT38-4) removed.  
20111118 Product data sheet  
Section Applications removed  
Table 6: IOH minimum values changed to maximum  
Product data sheet  
-
HEF4520B v.6  
HEF4520B v.6  
Modifications:  
-
HEF4520B v.5  
HEF4520B v.5  
20091210  
20090828  
19950101  
19950101  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
-
-
-
-
HEF4520B v.4  
HEF4520B_CNV v.3  
HEF4520B_CNV v.2  
-
HEF4520B v.4  
HEF4520B_CNV v.3  
HEF4520B_CNV v.2  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
10 / 12  
 
 
Nexperia  
HEF4520B  
Dual binary counter  
injury, death or severe property or environmental damage. Nexperia and its  
suppliers accept no liability for inclusion and/or use of Nexperia products in  
such equipment or applications and therefore such inclusion and/or use is at  
the customer’s own risk.  
14. Legal information  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Data sheet status  
Document status Product  
Definition  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
or warranty that such applications will be suitable for the specified use  
without further testing or modification.  
[1][2]  
status [3]  
Objective [short]  
data sheet  
Development  
This document contains data from  
the objective specification for  
product development.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia accepts no liability for  
any assistance with applications or customer product design. It is customer’s  
sole responsibility to determine whether the Nexperia product is suitable  
and fit for the customer’s applications and products planned, as well as  
for the planned application and use of customer’s third party customer(s).  
Customers should provide appropriate design and operating safeguards to  
minimize the risks associated with their applications and products.  
Preliminary [short]  
data sheet  
Qualification  
Production  
This document contains data from  
the preliminary specification.  
Product [short]  
data sheet  
This document contains the product  
specification.  
[1] Please consult the most recently issued document before initiating or  
completing a design.  
Nexperia does not accept any liability related to any default, damage, costs  
or problem which is based on any weakness or default in the customer’s  
applications or products, or the application or use by customer’s third party  
customer(s). Customer is responsible for doing all necessary testing for the  
customer’s applications and products using Nexperia products in order to  
avoid a default of the applications and the products or of the application or  
use by customer’s third party customer(s). Nexperia does not accept any  
liability in this respect.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have  
changed since this document was published and may differ in case of  
multiple devices. The latest product status information is available on  
the internet at https://www.nexperia.com.  
Definitions  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any representations or  
warranties as to the accuracy or completeness of information included herein  
and shall have no liability for the consequences of use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is  
intended for quick reference only and should not be relied upon to contain  
detailed and full information. For detailed and full information see the relevant  
full data sheet, which is available on request via the local Nexperia sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of commercial sale — Nexperia products are  
sold subject to the general terms and conditions of commercial sale, as  
published at http://www.nexperia.com/profile/terms, unless otherwise agreed  
in a valid written individual agreement. In case an individual agreement is  
concluded only the terms and conditions of the respective agreement shall  
apply. Nexperia hereby expressly objects to applying the customer’s general  
terms and conditions with regard to the purchase of Nexperia products by  
customer.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
Nexperia and its customer, unless Nexperia and customer have explicitly  
agreed otherwise in writing. In no event however, shall an agreement be  
valid in which the Nexperia product is deemed to offer functions and qualities  
beyond those described in the Product data sheet.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Disclaimers  
Limited warranty and liability — Information in this document is believed  
to be accurate and reliable. However, Nexperia does not give any  
representations or warranties, expressed or implied, as to the accuracy  
or completeness of such information and shall have no liability for the  
consequences of use of such information. Nexperia takes no responsibility  
for the content in this document if provided by an information source outside  
of Nexperia.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific Nexperia product is automotive qualified, the  
product is not suitable for automotive use. It is neither qualified nor tested in  
accordance with automotive testing or application requirements. Nexperia  
accepts no liability for inclusion and/or use of non-automotive qualified  
products in automotive equipment or applications.  
In no event shall Nexperia be liable for any indirect, incidental, punitive,  
special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal  
or replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards,  
customer (a) shall use the product without Nexperia’s warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
Nexperia’s specifications such use shall be solely at customer’s own risk,  
and (c) customer fully indemnifies Nexperia for any liability, damages or failed  
product claims resulting from customer design and use of the product for  
automotive applications beyond Nexperia’s standard warranty and Nexperia’s  
product specifications.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards customer  
for the products described herein shall be limited in accordance with the  
Terms and conditions of commercial sale of Nexperia.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
specifications and product descriptions, at any time and without notice. This  
document supersedes and replaces all information supplied prior to the  
publication hereof.  
Trademarks  
Suitability for use — Nexperia products are not designed, authorized or  
warranted to be suitable for use in life support, life-critical or safety-critical  
systems or equipment, nor in applications where failure or malfunction  
of an Nexperia product can reasonably be expected to result in personal  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
11 / 12  
 
Nexperia  
HEF4520B  
Dual binary counter  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................1  
4. Functional diagram.......................................................2  
5. Pinning information......................................................3  
5.1. Pinning.........................................................................3  
5.2. Pin description.............................................................3  
6. Functional description................................................. 3  
7. Limiting values............................................................. 4  
8. Recommended operating conditions..........................4  
9. Static characteristics....................................................4  
10. Dynamic characteristics............................................ 5  
10.1. Waveforms and test circuit........................................ 7  
11. Package outline.......................................................... 9  
12. Abbreviations............................................................10  
13. Revision history........................................................10  
14. Legal information......................................................11  
© Nexperia B.V. 2022. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 1 March 2022  
©
HEF4520B  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 1 March 2022  
12 / 12  

相关型号:

HEF4520BT,652

HEF4520B - Dual binary counter SOP 16-Pin
NXP

HEF4520BT,653

IC BINARY COUNTER DUAL 16SOIC
ETC

HEF4520BT-Q100

Dual binary counterProduction
NEXPERIA

HEF4520BT-T

IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOT-108, SO-14, Counter
NXP

HEF4520BTD

Synchronous Up Counter
ETC

HEF4520BTD-T

Synchronous Up Counter
ETC

HEF4521B

24-stage frequency divider and oscillator
NXP

HEF4521BD

24-stage frequency divider and oscillator
NXP

HEF4521BDB

IC 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 24-BIT UP BINARY COUNTER, CDIP16, Counter
NXP

HEF4521BF

24-stage frequency divider and oscillator
NXP

HEF4521BN

24-stage frequency divider and oscillator
NXP

HEF4521BP

24-stage frequency divider and oscillator
NXP