NCA9595PW-Q100 [NEXPERIA]
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and programmable pull-up resistorsProduction;
| 型号： | NCA9595PW-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and programmable pull-up resistorsProduction |
| 文件： | 总30页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt
output, configuration registers and programmable pull-up
resistors
Rev. 1 — 25 April 2023
Product data sheet
1. General description
The NCA9595-Q100 provides 16 bits of General Purpose Input/Output (GPIO) expansion for I²C-
bus/SMBus applications. It is designed for a wide voltage range of 1.65 V to 5.5 V with interrupt
and default pull-up resistors on GPIOs. Nexperia GPIO expanders provide an elegant solution
when additional IOs are needed while keeping the interconnections to a minimum, for example, in
ACPI power switches, sensors, push buttons, LEDs and fan control. The NCA9595-Q100 contains
a set of 8 bit input, output, configuration, polarity inversion and configuration pull-up registers. At
power up all IOs default to inputs. Each IO can be configured as either input or output by changing
the corresponding bit in the configuration register. The data for each input or output is stored in
the corresponding input or output register. The polarity inversion register can be programmed to
invert the polarity of the input register. The pull-up resistors can be disconnected by programming
configuration pull up registers. The NCA9595-Q100 has an open-drain interrupt output which is
activated when any one of the GPIO changes from its corresponding input port register state. The
power on reset sets the registers to default values and initializes the device state machine. The
NCA9595-Q100 has three address pins A0, A1 and A2 which can be used to configure the I²C bus
slave address of the device. It allows up-to eight devices to share the same I²C-bus/SMBus.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +125 °C
•
•
•
•
I²C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
•
4 µA (maximum)
•
Schmitt-trigger action allows slow input transition and better switching noise immunity at the
SCL and SDA inputs
•
•
Vhys = 0.10 × VCC (typical)
Noise filter on SCL and SDA inputs
•
•
•
•
•
•
•
•
•
•
5 V tolerant I/Os
16 I/O pins which power up configured in input state with weak configurable pull-up resistors
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I²C-bus
Internal power-on reset
Configuration pull-up registers to disable pull up resistors on GPIOs
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection:
•
•
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
NCA9595PW-Q100 -40 °C to +125 °C
TSSOP24
plastic thin shrink small outline package;
24 leads; body width 4.4 mm
SOT355-1
4. Block diagram
NCA9595
P1_0
P1_1
P1_2
8-bit
A0
A1
A2
INPUT/
write pulse
P1_3
P1_4
P1_5
P1_6
OUTPUT
PORTS
read pulse
P1_7
SCL
SDA
INPUT
FILTER
I²C-BUS/SMBus
CONTROL
P0_0
P0_1
P0_2
8-bit
INPUT/
OUTPUT
PORTS
P0_3
P0_4
P0_5
P0_6
POWER-ON
RESET
write pulse
read pulse
V
CC
P0_7
GND
V
CC
INT
LP
FILTER
aaa-036328
Remark: All I/Os are set to inputs at reset.
Fig. 1. Block diagram of NCA9595-Q100
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
2 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
5. Pinning information
5.1. Pinning
23
Fig. 2. Pin configuration SOT355-1 (TSSOP24)
5.2. Pin description
Table 2. Pin description
Symbol Pin
Type
O
Description
INT
1
2
3
4
5
6
7
8
9
Interrupt output. Connect to VCC through a pull-up resistor
A1
I
Address input 1. Connect directly to VCC or GND
A2
I
Address input 2. Connect directly to VCC or GND
P0_0 [1]
P0_1 [1]
P0_2 [1]
P0_3 [1]
P0_4 [1]
P0_5 [1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Parallel port I/O. Push-pull driver. At power on, P0_0 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_1 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_2 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_3 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_4 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_5 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_6 is configured as input
Parallel port I/O. Push-pull driver. At power on, P0_7 is configured as input
P0_6 [1] 10
P0_7 [1] 11
GND
12
power Ground
P1_0 [2] 13
P1_1 [2] 14
P1_2 [2] 15
P1_3 [2] 16
P1_4 [2] 17
P1_5 [2] 18
P1_6 [2] 19
P1_7 [2] 20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Parallel port I/O. Push-pull driver. At power on, P1_0 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_1 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_2 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_3 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_4 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_5 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_6 is configured as input
Parallel port I/O. Push-pull driver. At power on, P1_7 is configured as input
Address input 0. Connect directly to VCC or GND
A0
21
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
3 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Symbol Pin
Type
Description
SCL
SDA
VCC
22
23
24
I
Serial clock bus. Connect to VCC through a pull-up resistor
Serial data bus. Connect to VCC through a pull-up resistor.
I/O
power Supply voltage.
[1] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance inputs.
[2] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance inputs.
6. Functional description
For the block diagram of the NCA9595-Q100 see Fig. 1.
6.1. Device address
slave address
0
1
0
0
A2 A1 A0 R/W
fixed
hardware
selectable
002aaf819
Fig. 3. NCA9595-Q100 device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)
or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit of the slave
address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a
read operation, while a LOW (logic 0) selects a write operation.
6.2. Registers
6.2.1. Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a command
byte, which is stored in the address pointer register of the NCA9595-Q100. The lower three
bits of this data byte state the operation (read or write) and the internal registers (input, output,
configuration, polarity inversion and configuration pull-up registers) that will be affected. This
register is write only.
B7 B6 B5 B4 B3 B2 B1 B0
002aaf540
Fig. 4. Pointer register bits
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NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
4 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Table 3. Command byte
Pointer register bits
B7 B6 B5 B4 B3 B2 B1 B0
Command byte Register
(hexadecimal)
Protocol
Power-up
default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Input port 0
read byte
read byte
xxxx xxxx [1]
xxxx xxxx
Input port 1
Output port 0
read/write byte 1111 1111
read/write byte 1111 1111
read/write byte 0000 0000
read/write byte 0000 0000
read/write byte 1111 1111
read/write byte 1111 1111
Output port 1
Polarity Inversion port 0
Polarity Inversion port 1
Configuration port 0
Configuration port 1
Configuration pull-up port 0 read/write byte 1111 1111
Configuration pull-up port 1 read/write byte 1111 1111
[1] The default value ‘X’ is determined by the externally applied logic level.
6.2.2. Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the logic levels of the pins, regardless of whether
the pin is defined as an input or an output by the Configuration register. The Input port registers
are read only; writes to these registers have no effect. The default value ‘X’ is determined by the
externally applied logic level. An Input port register read operation is performed as described in
Section 7.2.
Table 4. Input port 0 register (address 00h)
Bit
7
I0.7
X
6
I0.6
X
5
I0.5
X
4
I0.4
X
3
I0.3
X
2
I0.2
X
1
I0.1
X
0
I0.0
X
Symbol
Default
Table 5. Input port 1 register (address 01h)
Bit
7
I1.7
X
6
I1.6
X
5
I1.5
X
4
I1.4
X
3
I1.3
X
2
I1.2
X
1
I1.1
X
0
I1.0
X
Symbol
Default
6.2.3. Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) define the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins defined
as inputs. In turn, reads from these registers reflect the value that was written to these registers,
not the actual pin value. A register pair write is described in Section 7.1 and a register pair read is
described in Section 7.2.
Table 6. Output port 0 register (address 02h)
Bit
7
O0.7
1
6
O0.6
1
5
O0.5
1
4
O0.4
1
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Symbol
Default
Table 7. Output port 1 register (address 03h)
Bit
7
O1.7
1
6
O1.6
1
5
O1.5
1
4
O1.4
1
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
Symbol
Default
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
5 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
6.2.4. Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs
by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding
port pin’s polarity is inverted in the Input register. If a bit in this register is cleared (written with a ‘0’),
the corresponding port pin’s polarity is retained. A register pair write is described in Section 7.1 and
a register pair read is described in Section 7.2.
Table 8. Polarity inversion port 0 register (address 04h)
Bit
7
N0.7
0
6
N0.6
0
5
N0.5
0
4
N0.4
0
3
N0.3
0
2
N0.2
0
1
N0.1
0
0
N0.0
0
Symbol
Default
Table 9. Polarity inversion port 1 register (address 05h)
Bit
7
N1.7
0
6
N1.6
0
5
N1.5
0
4
N1.4
0
3
N1.3
0
2
N1.2
0
1
N1.1
0
0
N1.0
0
Symbol
Default
6.2.5. Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in
these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit
in these registers is cleared to 0, the corresponding port pin is enabled as an output. A register pair
write is described in Section 7.1 and a register pair read is described in Section 7.2.
Table 10. Configuration port 0 register (address 06h)
Bit
7
C0.7
1
6
C0.6
1
5
C0.5
1
4
C0.4
1
3
C0.3
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
Symbol
Default
Table 11. Configuration port 1 register (address 07h)
Bit
7
C1.7
1
6
C1.6
1
5
C1.5
1
4
C1.4
1
3
C1.3
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
Symbol
Default
6.2.6. Configuration pull-up register pair (08h, 09h)
The Configuration pull-up registers (registers 8 and 9) are used to disable the pull-up resistors on
GPIOs. If a bit in these registers is set to 0, the corresponding port pull-up resistors are disabled.
This helps in disabling the pull-up resistors on the output ports and saves power consumption. A
register pair write is described in Section 7.1 and a register pair read is described in Section 7.2.
The default values of these registers at start up is 1 so that the pull-up resistors are enabled at
power-up on all parallel ports.
Table 12. Configuration pull-up port 0 register (address 08h)
Bit
7
R0.7
1
6
R0.6
1
5
R0.5
1
4
R0.4
1
3
R0.3
1
2
R0.2
1
1
R0.1
1
0
R0.0
1
Symbol
Default
Table 13. Configuration pull-up port 1 register (address 09h)
Bit
7
R1.7
1
6
R1.6
1
5
R1.5
1
4
R1.4
1
3
R1.3
1
2
R1.2
1
1
R1.1
1
0
R1.0
1
Symbol
Default
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
6 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
6.3. I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance
input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port
register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND.
The external voltage applied to this I/O pin should not exceed the recommended levels for proper
operation. The pull-up resistor of 100 kΩ is enabled by default at power-on as Q3 is enabled. If a bit
in configurable pull-up register is set to 0, the corresponding port pull-up resistor is disabled.
pull-up resistor
configuration
register
data from
shift register
D
Q
V
CC
FF
write pull-up resistor
configuration pulse
CK
Q
Q3
data from
shift register
configuration
register
output port
register data
data from
shift register
Q1
D
Q
FF
100 k
write configuration
pulse
D
Q
CK
Q
FF
P0_0 to P0_7
P1_0 to P1_7
write pulse
CK
Q2
output port
register
GND
input port
register
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity inversion
register
data from
shift register
polarity inversion
register data
D
Q
FF
write polarity
pulse
CK
aaa-036329
At power-on reset, all registers return to default values.
Fig. 5. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
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NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
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Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
6.4. Power-on reset
When power (from 0 V) is applied to VCC and starts rising, an internal power-on reset holds the
NCA9595-Q100 in a reset condition until VCC has reached VPOR. At that time, the reset condition
is released and the NCA9595-Q100 registers and I²C-bus/SMBus state machine initializes to
their default states. After that, VCC must be lowered to below VPORF and back up to the operating
voltage for a power-reset cycle. See Section 8.2.
6.5. Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After
time tv(INT), the signal INT is valid. The interrupt is reset when data on the port changes back
to the original value or when data is read form the port that generated the interrupt (see Fig. 9
and Fig. 10). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge
(NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK
clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Any
change of the I/Os after resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an
input may cause a false interrupt to occur, if the state of the pin does not match the contents of the
Input Port register.
7. Bus transactions
The NCA9595-Q100 is an I²C-bus slave device. Data is exchanged between the master and
NCA9595-Q100 through write and read commands using I²C-bus. The two communication lines
are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
7.1. Writing to the port registers
Data is transmitted to the NCA9595-Q100 by sending the start condition, the device address and
setting the read-write bit to a logic 0 (see Fig. 3). The command byte is sent after the address and
determines which register will receive the data following the command byte.
Eight registers within the NCA9595-Q100 are configured to operate as four register pairs. The four
pairs are input port, output port, polarity inversion, configuration registers. After sending data to
one register, the next data byte is sent to the other register in the pair (see Fig. 6 and Fig. 7). For
example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0
(register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, the
host can continuously update a register pair independently of the other registers, or the host can
simply update a single register.
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NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
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Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and programmable pull-up resistors
SCL
1
2
3
4
5
6
7
8
9
slave address
A2 A1 A0
command byte
data to port 0
DATA 0
data to port 1
DATA 1
SDA
S
0
1
0
0
0
A
0
0
0
0
0
0
1
0
A
0.7
0.0
A
1.7
1.0
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
write to port
t
v(Q)
data out
from port 0
t
v(Q)
data out
from port 1
DATA VALID
002aah344
Fig. 6. Write to output port registers
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
slave address
A2 A1 A0
command byte
0/1 0/1 0/1
data to register
DATA 0
data to register
DATA 1
SDA
S
0
1
0
0
0
A
0
0
0
0
0
A
A
A
P
MSB
LSB
MSB
LSB
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
aaa-035814
Fig. 7. Write to Control registers
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Nexperia B.V. 2023. All rights reserved
Product data sheet
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Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
7.2. Reading the port registers
In order to read data from the NCA9595-Q100, the bus master must first send the NCA9595-Q100
start condition, address with read-write bit set to logic 0 (see Fig. 3). The command byte is sent
after the address and determines which register will be accessed. After a start or restart, the device
address is sent again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte is sent by the NCA9595-Q100 (see Fig. 8, Fig. 9 and Fig. 10). Data
is clocked into the register on the rising edge of the acknowledge clock pulse. After the first byte is
read, additional bytes may be read but the data now reflects the information in the other register in
the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is no limit on
the number of data bytes received in one read transmission, but on the final byte received the bus
master must not acknowledge the data.
After a subsequent start or restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register that is
read after the restart is the Input Port 0.
command byte
0/1 0/1 0/1 A
slave address
A2 A1 A0
(cont.)
SDA
S
0
1
0
0
0
A
0
0
0
0
0
START condition
R/W
acknowledge
from slave
acknowledge
from slave
data from lower or
upper byte of register
data from upper or
lower byte of register
slave address
A2 A1 A0
MSB
LSB
MSB
LSB
(cont.)
S
0
1
0
0
1
A
DATA (first byte)
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from master
no acknowledge STOP
from master condition
acknowledge
from slave
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
aaa-035815
Remark: Transfer can be stopped at any time by a STOP condition.
Fig. 8. Read from register
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
10 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and programmable pull-up resistors
data into port 0
data into port 1
INT
t
t
rst(INT)
v(INT)
SCL
SDA
1
2
3
4
5
6
7
8
9
R/W
STOP condition
slave address
A2 A1 A0
I0.x
I1.x
I0.x
I1.x
S
0
1
0
0
1
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
1
P
START condition
acknowledge
from slave
acknowledge
from master
acknowledge
from master
acknowledge
from master
non acknowledge
from master
read from port 0
read from port 1
aaa-036333
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to ‘00h’ (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Fig. 8).
Fig. 9. Read input port register, scenario 1
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NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
11 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and programmable pull-up resistors
data into port 0
data into port 1
INT
DATA 00
DATA 01
DATA 02
DATA 03
t
t
su(D)
h(D)
DATA 10
DATA 11
DATA 12
t
t
su(D)
h(D)
t
t
rst(INT)
v(INT)
3
SCL
SDA
1
2
4
5
6
7
8
9
R/W
STOP condition
slave address
A2 A1 A0
I0.x
I1.x
DATA 10
I0.x
DATA 03
I1.x
S
0
1
0
0
1
A
DATA 00
A
A
A
DATA 12
1
P
START condition
acknowledge
from slave
acknowledge
from master
acknowledge
from master
acknowledge
from master
non acknowledge
from master
read from port 0
read from port 1
aaa-036327
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to ‘00h’ (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Fig. 8).
Fig. 10. Read input port register, scenario 2
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
12 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
8. Application design-in information
V
CC
(3.3 V)
(1)
SUB-SYSTEM 1
(e.g., temp sensor)
10 k
10 k
10 k
2 k
100 k
(×3)
V
CC
V
CC
INT
MASTER
CONTROLLER
NCA9595
SCL
SCL
SDA
INT
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
SUB-SYSTEM 2
(e.g., counter)
SDA
INT
RESET
A
GND
controlled
switch
(e.g., CBT device)
enable
B
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
(1)
SUB-SYSTEM 3
(e.g., alarm system)
10 DIGIT
NUMERIC
KEYPAD
ALARM
A2
A1
A0
GND
GND
aaa-036342
Device address configured as 0100 000X for this example.
P0_0, P0_2, P0_3 configured as outputs.
P0_1, P0_4, P0_5 configured as inputs.
P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.
(1) Internal pull-up may be configured for output ports to save power consumption.
Fig. 11. Typical application
8.1. Minimizing ICC when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as
shown in Fig. 11. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less
than VCC. The supply current, ICC, increases as VI becomes lower than VCC
.
Designs needing to minimize current consumption, such as battery power applications, should
consider maintaining the I/O pins greater than or equal to VCC when the LED is off. Fig. 12 shows a
high value resistor in parallel with the LED. Fig. 13 shows VCC less than the LED supply voltage by
at least 1.2 V. Both of these methods maintain the I/O VI at or above VCC and prevents additional
supply current consumption when the LED is off.
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
13 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
V
CC
3.3 V
5 V
V
100 k
CC
LED
V
CC
LED
Pn
Pn
aaa-035816
aaa-035817
Fig. 12. High value resistor in parallel with
the LED
Fig. 13. Device supplied by a lower voltage
8.2. Power-on reset requirements
In the event of a glitch or data corruption, NCA9595-Q100 can be reset to its default conditions by
using the power-on reset feature. Power-on reset requires that the device go through a power cycle
to be completely reset. This reset also happens when the device is powered on for the first time in
an application.
The two types of power-on reset are shown in Fig. 14 and Fig. 15.
V
CC
ramp-up
ramp-down
re-ramp-up
t
d(rst)
time
time to re-ramp
when V drops
t
(V )
rise CC
t
(V
fall CC
)
t (V )
rise CC
CC
below 0.2 V or to GND
aaa-035819
Fig. 14. VCC is lowered below 0.2 V or to 0 V and then ramped up to VCC
V
CC
ramp-down
ramp-up
t
d(rst)
V drops below POR levels
I
time
time to re-ramp
t
(V
fall CC
)
t
(V )
rise CC
when V
drops
CC
to V
- 50 mV
PORF(min)
aaa-035820
Fig. 15. VCC is lowered below the POR threshold, then ramped back up to VCC
Table 14 specifies the performance of the power-on reset feature for NCA9595-Q100 for both types
of power-on reset.
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
14 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Table 14. Recommended supply sequencing and ramp rates
Tamb = 25 °C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Tamb = 25 °C
Unit
Min
0.1
0.1
1
Typ
Max
trise(V
supply ramp up time
supply ramp down time
reset delay time
Fig. 14
Fig. 14
-
-
-
2000 ms
2000 ms
)
CC
tfall(V
)
CC
td(rst)
Fig. 14; re-ramp time when VCC
drops below 0.2 V or to GND
-
µs
Fig. 15; re-ramp time when VCC
drops to VPOR(min) - 50 mV
1
-
-
µs
ΔVCC(gl)
glitch supply voltage difference
Fig. 16
-
-
-
1
-
V
V
VCC_MIN(gl) minimum glitch supply voltage
minimum voltage that VCC can
glitch down to, but not cause
functional disruption when tw(gl)V
Fig. 16
1.5
CC
tw(gl)V
supply voltage glitch pulse width
Fig. 16
-
-
10
μs
CC
Glitches in the power supply can also affect the power-on reset performance of this device.
The glitch width (tw(gl)V ) and glitch height (ΔVCC(gl)) are dependent on each other. The bypass
CC
capacitance, source impedance, and device impedance are factors that affect power-on
reset performance. Fig. 16 and Table 14 provide more information on how to measure these
specifications.
V
CC
V
V
CC(gl)
CC_MIN(gl)
time
t
w(gl)V
CC
aaa-035821
Fig. 16. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is
released and all the registers and the I²C-bus/SMBus state machine are initialized to their default
states. The value of VPOR differs based on the VCC being lowered to or from 0 V. Fig. 17 and Table
14 provide more details on this specification.
V
CC
V
(rising V
(falling V
)
)
PORR
CC
CC
V
PORF
time
POR
time
aaa-035822
Fig. 17. Power-on reset voltage (VPOR
)
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
15 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
8.3. Device current consumption with internal pull-up and pull-down
resistors
The NCA9595-Q100 integrates pull-up resistors to eliminate external components when pins are
configured as inputs and pull-up resistors are required (for example, nothing is driving the inputs to
the power supply rails. Since these pull-up resistors are internal to the device itself, they contribute
to the current consumption of the device and must be considered in the overall system design.
If the resistor is configured as a pull-up, that is, connected to VCC, a current will flow from the VCC
pin through the resistor to ground when the pin is held LOW. This current will appear as additional
ICC upsetting any current consumption measurements.
The pull-up resistors are simple resistors and the current is linear with voltage. The resistance
specification for these devices spans from 50 kΩ with a nominal 100 kΩ value. Any current
flow through these resistors is additive by the number of pins held LOW and the current can be
calculated by Ohm’s law. See Fig. 21 for a graph of supply current versus the number of pull-up
resistors.
9. Limiting values
Table 15. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
Max
6
Unit
V
supply voltage
-0.5
input voltage
[1]
[1]
-0.5
6
V
VO
output voltage
-0.5
6
V
IIK
input clamping current
output clamping current
input/output clamping current
A0, A1, A2, SCL; VI < 0 V
INT; VO < 0 V
-
-20
-20
±20
-20
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
IOK
-
IIOK
P port; VO < 0 V or VO > VCC
SDA; VO < 0 V
-
-
IOL
LOW-level output current
continuous; I/O port
continuous; SDA, INT
continuous; P port
-
-
25
IOH
HIGH-level output current
supply current
-
25
ICC
-
-
160
250
200
+150
135
+125
IGND
Ptot
ground supply current
total power dissipation
storage temperature
maximum junction temperature
ambient temperature
-
Tstg
-65
-
Tj(max)
Tamb
°C
operating in free air
-40
°C
[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
16 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
10. Recommended operating conditions
Table 16. Operating conditions
Symbol
VCC
Parameter
Conditions
Min
1.65
Max
5.5
Unit
V
supply voltage
VIH
HIGH-level input voltage
SCL, SDA
0.7 × VCC
0.7 × VCC
0.7 × VCC
-0.5
5.5
V
P1_7 to P0_0
A0, A1, A2,
5.5
V
VCC
V
VIL
LOW-level input voltage
SCL, SDA
0.3 × VCC
0.3 × VCC
10
V
A0, A1, A2, P1_7 to P0_0
P1_7 to P0_0
P1_7 to P0_0
-0.5
V
IOH
IOL
HIGH-level output current
LOW-level output current
-
mA
mA
-
25
11. Thermal characteristics
Table 17. Thermal characteristics
Symbol
Parameter
transient thermal impedance from junction to ambient
Conditions
TSSOP24 package
Max
Unit
K/W
Zth(j-a)
[1]
100
[1] The package thermal impedance is calculated in accordance with JESD 51-7.
12. Static characteristics
Table 18. Static characteristics
VCC = 1.65 V to 5.5 V; unless otherwise specified.
Symbol Parameter
Conditions
Tamb = -40 °C
to +125 °C
Unit
Min Typ [1] Max
VIK
input clamping voltage
II = -18 mA
-1.2
0.8
-
-
-
V
V
VPORF
power-on reset trip voltage; VI = VCC or GND; IO = 0 mA
VCC falling
1.1
VPORR
IOL
power-on reset trip voltage; VI = VCC or GND; IO = 0 mA
VCC rising
-
1.25
1.6
V
LOW-level output current
VOL = 0.4 V; VCC = 1.65 V to 5.5 V
SDA
3
3
-
-
-
mA
mA
INT
28 [2]
P port
VOL = 0.5 V; VCC = 1.65 V
VOL = 0.7 V; VCC = 1.65 V
VOL = 0.5 V; VCC = 2.3 V
VOL = 0.7 V; VCC = 2.3 V
VOL = 0.5 V; VCC = 3.0 V
VOL = 0.7 V; VCC = 3.0 V
VOL = 0.5 V; VCC = 4.5 V
VOL = 0.7 V; VCC = 4.5 V
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
8
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
8
10
8
10
8
10
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
17 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Symbol Parameter
Conditions
Tamb = -40 °C
to +125 °C
Unit
Min Typ [1] Max
VOH
HIGH-level output voltage
P port
IOH = -8 mA; VCC = 1.65 V
[4] 1.2
[4] 1.05
[4] 2.0
[4] 1.9
[4] 2.6
[4] 2.5
[4] 4.1
[4] 4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IOH = -10 mA; VCC = 1.65 V
IOH = -8 mA; VCC = 2.3 V
IOH = -10 mA; VCC = 2.3 V
IOH = -8 mA; VCC = 3.0 V
IOH = -10 mA; VCC = 3.0 V
IOH = -8 mA; VCC = 4.5 V
IOH = -10 mA; VCC = 4.5 V
P port; IOL = 8 mA
VOL
LOW-level output voltage
VCC = 1.65 V
-
-
-
-
-
-
-
-
0.45
0.30
0.25
0.2
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
II
input current
VCC = 1.65 V to 5.5 V
SCL, SDA; VI = VCC or GND
A0, A1, A2; VI = VCC or GND
P port; VI = VCC; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
1
±1
1
μA
μA
μA
μA
IIH
IIL
HIGH-level input current
LOW-level input current
P port; VI = GND; VCC = 1.65 V to 5.5 V;
pull up disabled
-1
P port; VI = GND; VCC = 1.65 V to 5.5 V;
pull up enabled
-
-
-100 μA
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
18 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Symbol Parameter
Conditions
Tamb = -40 °C
to +125 °C
Unit
Min Typ [1] Max
ICC
supply current
SDA, P port, A0, A1, A2;
[5]
VI on SDA = VCC or GND;
VI on P port and A0, A1, A2 = VCC
;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
(tr = 30 ns)
VCC = 3.6 V to 5.5 V
VCC = 2.3 V to 3.6 V
VCC = 1.65 V to 2.3 V
-
-
-
13
6.4
3
29
12
μA
μA
6.5 μA
SCL, SDA, P port, A0, A1, A2;
VI on SCL, SDA = VCC or GND;
VI on P port and A0, A1, A2 = VCC
;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
VCC = 3.6 V to 5.5 V
-
-
-
1.5
0.95
0.5
4
3
2
μA
μA
μA
VCC = 2.3 V to 3.6 V
VCC = 1.65 V to 2.3 V
Active mode; P port, A0, A1, A2;
VI on P port, A0, A1, A2 = VCC
;
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz (tr = 30 ns), continuous
register read
VCC = 3.6 V to 5.5 V
VCC = 2.3 V to 3.6 V
VCC = 1.65 V to 2.3 V
-
-
-
15
7.4
3.5
60
27
11
μA
μA
μA
with pull-ups enabled; P port, A0, A1, A2;
VI on SCL and SDA = VCC or GND;
VI on P port = GND;
VI on A0, A1, A2 = VCC or GND;
IO = 0 mA; I/O = inputs with pull-up enabled;
fSCL = 0 kHz
VCC = 1.65 V to 5.5 V
-
-
0.88
-
1.6 mA
ΔICC
additional quiescent supply SCL, SDA; one input at VCC - 0.6 V, other
10
μA
current
inputs at VCC or GND; VCC = 1.65 V to 5.5 V
P port, A0, A1, A2; one input at VCC - 0.6 V,
other inputs at VCC or GND;
-
-
18
μA
VCC = 1.65 V to 5.5 V
Ci
input capacitance
VI = VCC or GND; VCC = 1.65 V to 5.5 V
VI/O = VCC or GND; VD = 1.65 V to 5.5 V
-
-
1.5
3
3.5 pF
pF
Cio
input/output capacitance
5
[1] For ICC, all typical values are at nominal supply voltage (1.8 V, 3.3 V or 5 V VCC) and Tamb = 25 °C. Except for ICC, the typical values
are at VCC = 3.3 V and Tamb = 25 °C.
[2] Typical value for Tamb = 25 °C. VOL = 0.4 V and VCC = 3.3 V.
[3] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 200 mA.
[4] The total current sourced by all I/Os must be limited to 160 mA.
[5] For ICC parameters, all pull-up resistors are configured as enabled.
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
19 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
12.1. Typical characteristics
aaa-035957
aaa-035958
25
20
15
10
5
2
1.5
1
I
I
CC
(μA)
CC
(µA)
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
0.5
0
0
-40
-10
20
50
80
T
110
(°C)
140
-40
-10
20
50
80
T
110
(°C)
140
amb
amb
fSCL = 400 kHz
(1) VCC = 1.65 V
(2) VCC = 1.8 V
(3) VCC = 2.3 V
(4) VCC = 2.5 V
(5) VCC = 3.3 V
(6) VCC = 3.6 V
(7) VCC = 5.0 V
(8) VCC = 5.5 V
(1) VCC = 1.65 V
(2) VCC = 1.8 V
(3) VCC = 2.3 V
(4) VCC = 2.5 V
(5) VCC = 3.3 V
(6) VCC = 3.6 V
(7) VCC = 5.0 V
(8) VCC = 5.5 V
Fig. 19. Standby supply current versus ambient
temperature
Fig. 18. Supply current versus ambient temperature
aaa-035960
1.2
I
CC
(mA)
1
aaa-035959
0.8
0.6
0.4
0.2
0
25
I
CC
(4)
(3)
(2)
(1)
(μA)
20
15
10
5
0
2
4
6
8
10
12
14
16
Number of I/O held LOW
VCC = 5.5 V
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 85 °C
0
1.5
2
2.5
3
3.5
4
4.5
CC
5
(V)
5.5
V
(4) Tamb = 125 °C
Tamb = 25 °C; fSCL = 400 kHz
Fig. 20. Supply current versus supply voltage
Fig. 21. Supply current versus number of I/O held LOW
with default when pull ups are enabled
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
20 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
aaa-035961
aaa-035962
25
20
15
10
5
25
20
15
10
5
I
I
sink
(mA)
sink
(mA)
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
0
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(V)
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(V)
V
OL
V
OL
a. VCC = 1.65 V
b. VCC = 1.8 V
aaa-035963
aaa-035964
40
40
I
I
sink
sink
(mA)
(mA)
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
30
20
10
0
30
20
10
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(V)
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(V)
V
OL
V
OL
c. VCC = 2.5 V
d. VCC = 3.3 V
aaa-035965
aaa-035966
50
50
I
I
sink
sink
(mA)
(mA)
40
30
20
10
0
40
30
20
10
0
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(V)
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(V)
V
OL
V
OL
e. VCC = 5.0 V
f. VCC = 5.5 V
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 85 °C
(4) Tamb = 125 °C
Fig. 22. I/O sink current versus LOW-level output voltage
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NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
21 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
aaa-035967
aaa-035968
30
40
I
I
I
I
I
I
source
(mA)
source
(mA)
25
20
15
10
5
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
30
20
10
0
0
0
0.1
0.2
0.2
0.2
0.3
0.4
CC
0.5
(V)
0.6
0
0.1
0.2
0.2
0.2
0.3
0.4
CC OH
0.5
(V)
0.6
V
V
V
- V
OH
V
V
V
- V
a. VCC = 1.65 V
b. VCC = 1.8 V
aaa-035969
aaa-035970
50
60
source
(mA)
source
(mA)
50
40
30
20
10
0
40
30
20
10
0
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
0
0.1
0.3
0.4
0.5
(V)
0.6
0
0.1
0.3
0.4
CC
0.5
(V)
0.6
- V
- V
OH
CC
OH
c. VCC = 2.5 V
d. VCC = 3.3 V
aaa-035971
aaa-035972
80
80
source
(mA)
source
(mA)
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
60
40
20
0
60
40
20
0
0
0.1
0.3
0.4
0.5
(V)
0.6
0
0.1
0.3
0.4
CC
0.5
(V)
0.6
- V
- V
OH
CC
OH
e. VCC = 5.0 V
f. VCC = 5.5 V
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 85 °C
(4) Tamb = 125 °C
Fig. 23. I/O source current versus HIGH-level output voltage
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
22 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
aaa-035973
aaa-035974
250
300
- V
OH
V
V
CC
OL
(mV)
(mV)
250
200
150
100
50
200
150
100
50
(1)
(2)
(3)
(4)
(1)
(3)
(2)
(4)
0
-40
0
-40
-10
20
50
80
T
110
(°C)
140
-10
20
50
80
T
110
(°C)
140
amb
amb
(1) VCC = 1.8 V; Isink = 10 mA
(2) VCC = 5 V; Isink = 10 mA
(3) VCC = 1.8 V; Isink = 1 mA
(4) VCC = 5 V; Isink = 1 mA
(1) VCC = 1.8 V; Isource = -10 mA
(2) VCC = 5 V; Isource = -10 mA
(3) VCC = 1.8 V; Isource = -1 mA
(4) VCC = 5 V; Isource = -1 mA
Fig. 24. LOW-level output voltage versus temperature
Fig. 25. I/O high voltage versus temperature
13. Dynamic characteristics
Table 19. I²C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Fig. 26.
Symbol Parameter
Conditions
Standard-mode
I²C-bus
Fast-mode
I²C-bus
Unit
Min
0
Max
100
-
Min
0
Max
400 kHz
fSCL
tHIGH
tLOW
tSP
SCL clock frequency
HIGH period of the SCL clock
LOW period of the SCL clock
4
0.6
1.3
0
-
-
μs
μs
ns
4.7
0
-
pulse width of spikes that must be
suppressed by the input filter
50
50
tSU;DAT data set-up time
tHD;DAT data hold time
250
-
-
100
0
-
-
ns
ns
0
-
tr
rise time of both SDA and SCL signals
1000
20
300 ns
tf
fall time of both SDA and SCL signals
-
300 20×(VCC/5.5 V) 300 ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tHD;STA hold time (repeated) START condition
tSU;STO set-up time for STOP condition
tVD;DAT data valid time
4
4
-
-
-
0.6
0.6
-
-
-
μs
μs
SCL LOW to SDA
output valid
3.45
0.9 μs
tVD;ACK data valid acknowledge time
ACK signal from
SCL LOW to SDA
(out) LOW
-
3.45
-
0.9 μs
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NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
23 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Table 20. Switching characteristics
Over recommended operating free air temperature range; CL ≤ 100 pF; unless otherwise specified. See Fig. 27.
Symbol Parameter
Conditions
Standard-mode
I²C-bus
Fast-mode
I²C-bus
Unit
Min
Max
Min
Max
tv(INT)
trst(INT)
tv(Q)
valid time on pin INT
from P port to INT
from SCL to INT
-
-
1
1
-
1
μs
μs
ns
ns
ns
reset time on pin INT
data output valid time
data input set-up time
data input hold time
-
1
from SCL to P port
from P port to SCL
from P port to SCL
-
280
-
-
280
tsu(D)
th(D)
-50
240
-50
240
-
-
-
14. Parameter measurement information
V
CC
R
L
= 1 k
SDA
DUT
C
L
= 50 pF
aaa-035847
a. SDA load configuration
(1)
two bytes for read Input port register
R/W
STOP
condition condition
(P) (S)
START
Address
Bit 7
(MSB)
Data
Bit 7
(MSB)
Data
STOP
condition
(P)
Address
Bit 1
ACK
(A)
Bit 0
Bit 0
(LSB)
(LSB)
002aag952
b. Transaction format
t
HIGH
t
t
SP
LOW
0.7 × V
0.3 × V
CC
CC
SCL
SDA
t
t
r
VD;DAT
t
t
SU;STO
BUF
t
f
t
t
SU;STA
VD;ACK
t
f(o)
0.7 × V
0.3 × V
CC
CC
t
f
t
r
t
VD;ACK
t
t
t
HD;DAT
HD;STA
SU;DAT
repeat START condition
STOP condition
aaa-035843
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I²C-bus address; Byte 2, byte 3 = P port data.
(1) See Fig. 9.
Fig. 26. I²C-bus interface load circuit and voltage waveforms
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NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
24 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
V
CC
R
L
= 4.7 k
INT
DUT
C
L
= 100 pF
aaa-035848
a. Interrupt load configuration
acknowledge
from slave
acknowledge
from slave
no acknowledge
from master
START condition
slave address
R/W
STOP
8 bits (one data byte)
from port
condition
data from port
DATA 2
SDA
S
0
1
0
0
A2 A1 A0
1
A
DATA 1
A
1
P
SCL
1
2
3
4
5
6
7
8
9
B
B
t
t
rst(INT)
rst(INT)
INT
A
A
t
v(INT)
t
su(D)
data into
port
ADDRESS
DATA 1
SCL
DATA 2
0.7 × V
0.3 × V
CC
CC
INT
0.5 × V
0.5 × V
R/W
A
CC
t
v(INT)
t
rst(INT)
Pn
INT
0.5 × V
CC
CC
View A - A
View B - B
aaa-035844
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig. 27. Interrupt load circuit and voltage waveforms
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NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
25 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Pn
DUT
C
= 100 pF
L
aaa-036330
a. P port load configuration
0.7 × V
0.3 × V
CC
CC
SCL
P0
A
P7
SDA
Pn
t
v(Q)
last stable bit
unstable
data
aaa-035845
b. Write mode (R/W = 0)
0.7 × V
0.3 × V
CC
CC
SCL
P0
A
P7
t
t
h(D)
su(D)
Pn
aaa-035846
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 × VCC on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig. 28. P port load circuit and voltage waveforms
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NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
26 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
15. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig. 29. Package outline SOT355-1 (TSSOP24)
©
NCA9595_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
27 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
16. Abbreviations
Table 21. Abbreviations
Acronym
ACPI
CBT
Description
Advanced Configuration and Power Interface
Cross-Bar Technology
CDM
CMOS
ESD
Charged-Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Field-Effect Transistor
FET
FF
Flip-Flop
GPIO
HBM
I²C-bus
I/O
General Purpose Input/Output
Human Body Model
Inter-Integrated Circuit bus
Input/Output
LED
Light Emitting Diode
SMBus
System Management Bus
17. Revision history
Table 22. Revision history
Document ID
Release date Data sheet status
20230425 Product data sheet
Change notice Supersedes
NCA9595_Q100 v.1
-
-
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Product data sheet
Rev. 1 — 25 April 2023
28 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
18. Legal information
risk.
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
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Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
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Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
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Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
NCA9595_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
29 / 30
Nexperia
NCA9595-Q100
Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output, configuration registers and
programmable pull-up resistors
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Block diagram...............................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
6.1. Device address............................................................4
6.2. Registers......................................................................4
6.2.1. Pointer register and command byte..........................4
6.2.2. Input port register pair (00h, 01h).............................5
6.2.3. Output port register pair (02h, 03h).......................... 5
6.2.4. Polarity inversion register pair (04h, 05h)................. 6
6.2.5. Configuration register pair (06h, 07h).......................6
6.2.6. Configuration pull-up register pair (08h, 09h)............6
6.3. I/O port........................................................................ 7
6.4. Power-on reset............................................................ 8
6.5. Interrupt output............................................................ 8
7. Bus transactions.......................................................... 8
7.1. Writing to the port registers......................................... 8
7.2. Reading the port registers.........................................10
8. Application design-in information.............................13
8.1. Minimizing ICC when the I/Os are used to control
LEDs...................................................................................13
8.2. Power-on reset requirements.................................... 14
8.3. Device current consumption with internal pull-up
and pull-down resistors......................................................16
9. Limiting values........................................................... 16
10. Recommended operating conditions......................17
11. Thermal characteristics............................................17
12. Static characteristics................................................17
12.1. Typical characteristics..............................................20
13. Dynamic characteristics.......................................... 23
14. Parameter measurement information..................... 24
15. Package outline........................................................ 27
16. Abbreviations............................................................28
17. Revision history........................................................28
18. Legal information......................................................29
© Nexperia B.V. 2023. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 25 April 2023
©
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 1 — 25 April 2023
30 / 30
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