PHB21N06LT [NEXPERIA]
N-channel TrenchMOS logic level FETProduction;
| 型号： | PHB21N06LT |
| 厂家： | 
Nexperia |
| 描述： | N-channel TrenchMOS logic level FETProduction 开关 脉冲 晶体管 |
| 文件： | 总12页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Low on-state resistance
• Fast switching
VDSS = 55 V
ID = 19 A
• Logic level compatible
RDS(ON) ≤ 75 mΩ (VGS = 5 V)
g
RDS(ON) ≤ 70 mΩ (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D2PAK)
SOT428 (DPAK)
tab
tab
PIN
1
DESCRIPTION
tab
gate
2
drain 1
source
2
2
3
1 2 3
1
3
1
3
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
VGSM
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage Tj ≤ 150˚C
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
55
55
± 15
± 20
19
V
V
V
V
A
Continuous drain current
Tmb = 25 ˚C
mb = 100 ˚C
T
13
A
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tmb = 25 ˚C
Tmb = 25 ˚C
-
-
76
56
175
A
W
˚C
- 55
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 9.7 A;
tp = 100 µs; Tj prior to avalanche = 25˚C;
-
34
mJ
energy
VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to
fig:15
IAS
Peak non-repetitive
avalanche current
-
19
A
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
2.7
K/W
Rth j-a
Thermal resistance junction SOT78 package, in free air
60
50
-
-
K/W
K/W
to ambient
SOT428 and SOT404 package, pcb
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA;
55
50
-
-
-
-
V
V
Tj = -55˚C
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
1.0
0.5
-
-
-
-
5
-
-
1.5
-
-
55
60
-
13
10
0.05
-
2.0
-
2.3
70
75
158
-
100
10
500
V
V
V
mΩ
mΩ
mΩ
S
nA
µA
µA
Tj = 175˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 10 A
VGS = 5 V; ID = 10 A
Tj = 175˚C
Tj = 175˚C
gfs
IGSS
IDSS
Forward transconductance
Gate source leakage current VGS = ±5 V; VDS = 0 V
Zero gate voltage drain
current
VDS = 25 V; ID = 10 A
VDS = 55 V; VGS = 0 V;
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 20 A; VDD = 44 V; VGS = 5 V
-
-
-
9.4
2.2
5.4
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; RD = 1.2 Ω;
RG = 10 Ω; VGS = 5 V
Resistive load
-
-
-
-
7
15
120
40
ns
ns
ns
ns
88
25
25
45
Ld
Ld
Internal drain inductance
Internal drain inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
-
-
3.5
4.5
-
-
nH
nH
Ls
Internal source inductance
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
466
95
71
650
135
85
pF
pF
pF
August 1999
2
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
-
19
76
A
A
V
ISM
VSD
IF = 20 A; VGS = 0 V
1.2
1.5
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
43
94
-
-
ns
nC
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
Normalised Power Derating, PD (%)
100
10
1
100
90
80
70
60
50
40
30
20
10
0
tp = 10 us
100 us
1 ms
D.C.
10 ms
100 ms
0.1
0
25
50
75
100
125
150
175
1
10
Drain-Source Voltage, VDS (V)
100
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-mb (K/W)
10
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
D = 0.5
1
0.1
0.2
0.1
0.05
0.02
P
D = tp/T
D
tp
single pulse
T
0.01
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
Pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
August 1999
3
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
Drain Current, ID (A)
35
Transconductance, gfs (S)
15
14
13
12
11
10
9
8
7
6
5
VDS > ID X RDS(ON)
Tj = 25 C
Tj = 25 C
30
25
20
15
10
5
VGS = 10V
5 V
175 C
3.4 V
3.2 V
3 V
4
3
2
1
2.8 V
2.6 V
2.4 V
0
0
0
2
4
6
8
10
12
14
16
18
20
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain current, ID (A)
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Normalised On-state Resistance
Drain-Source On Resistance, RDS(on) (Ohms)
0.3
2.4
2.2
2
2.6 V
Tj = 25 C
2.8V
0.25
0.2
0.15
0.1
0.05
0
2.4 V
1.8
1.6
1.4
1.2
1
3 V
3.2 V
3.4 V
0.8
0.6
0.4
0.2
0
5 V
VGS = 10V
30 35
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
0
5
10
15
20
25
Junction temperature, Tj (C)
Drain Current, ID (A)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Threshold Voltage, VGS(TO) (V)
2.25
Drain current, ID (A)
20
VDS > ID X RDS(ON)
2
18
16
14
12
10
8
maximum
1.75
typical
1.5
1.25
1
minimum
0.75
0.5
0.25
0
6
4
175 C
Tj = 25 C
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
August 1999
4
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
Drain current, ID (A)
1.0E-01
Source-Drain Diode Current, IF (A)
30
25
20
15
10
5
VGS = 0 V
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
minimum
typical
175 C
Tj = 25 C
maximum
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
0
0.5
1
1.5
2
2.5
3
Source-Drain Voltage, VSDS (V)
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Maximum Avalanche Current, IAS (A)
100
Capacitances, Ciss, Coss, Crss (pF)
10000
10
1
25 C
1000
100
10
Ciss
Tj prior to avalanche = 150 C
Coss
Crss
0.1
0.001
0.01
0.1
Avalanche time, tAV (ms)
1
10
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
ID = 20A
Tj = 25 C
VDD = 11 V
8
7
VDD = 44 V
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
August 1999
5
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
SOT78
E
P
A
A
1
q
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
2
b
e
A
b
D
E
L
D
1
L
1
A
1
c
UNIT
P
q
Q
1
max.
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
97-06-11
SOT78
TO-220
Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
MECHANICAL DATA
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.40 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
98-12-14
99-06-25
SOT404
Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
August 1999
8
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
A
y
A
2
E
A
A
1
b
D
1
2
mounting
base
E
1
D
H
E
L
2
2
L
1
L
1
3
b
1
b
w
M
A
c
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
b
E
H
E
max.
D
L
y
1
min.
A
max.
D
max.
E
max.
1
1
(1)
1
A
b
2
A
UNIT
mm
b
c
e
e
1
L
L
w
2
1
2
max.
max.
min.
max.
0.65 0.89
0.45 0.71
0.7
0.5
2.38
2.22
0.89 1.1
0.71 0.9
5.36
5.26
0.4 6.22
0.2 5.98
6.73
6.47
2.95
2.55
10.4
9.6
4.81
4.45
4.57
0.2
0.2
4.0 2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT428
98-04-07
Fig.19. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
MOUNTING INSTRUCTIONS
August 1999
9
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.20. SOT428 : soldering pattern for surface mounting.
August 1999
10
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
11
Rev 1.500
相关型号：
PHB220N03MT
TRANSISTOR 75 A, 25 V, 0.0037 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power
NXP
©2020 ICPDF网 联系我们和版权申明