DP7261 [NIDEC]
Dual Digital Potentiometers;
| 型号： | DP7261 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | Dual Digital Potentiometers |
| 文件： | 总15页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7261
Dual Digital Potentiometers
(DP) with 256 Taps and SPI Interface
FEATURES
DESCRIPTION
Two linear-taper digital potentiometers
The DP7261 is two Digital Potentiometers
(DPs) integrated with control logic and 8 bytes of
NVRAM memory. Each DP consists of a series
of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the wiper
tap switches for each DP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the non-
volatile data registers is via a SPI serial bus. On power-
up, the contents of the first data register (DR0) for each
of the potentiometers is automatically loaded into its
respective wiper control register.
256 resistor taps per potentiometer
End to end resistance 50k or 100k
Potentiometer control and memory access via
SPI interface
Low wiper resistance, typically 100
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
The DP7261 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
Industrial temperature range
For Ordering Information details, see page 14.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC/TSSOP (W, Y)
¯¯¯¯¯
R
H0
R
H1
CS
SCK
SI
SO
A0
1
2
3
4
5
6
7
8
24
HOLD
WIPER
CONTROL
REGISTERS
SPI BUS
INTERFACE
23 SCK
22 NC
21 NC
20 NC
19 NC
18 GND
17 RW1
R
R
W0
SO
NC
NC
NC
NC
VCC
RL0
W1
DP
7261
WP
A0
A1
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
HOLD
R
L0
R
L1
RH0
9
16 RH1
RW0 10
15 RL1
14 A1
13 SI
¯¯¯
CS
11
12
¯¯¯
WP
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2122 Rev. D
DP7261
PIN DESCRIPTIONS
Pin #
1
Name Function
SI: Serial Input
SI is the serial data input pin. This pin is used
to input all opcodes, byte addresses and data
to be written to the DP7261. Input data is
latched on the rising edge of the serial clock.
SO
A0
Serial Data Output
2
Device Address, LSB
3
NC
NC
NC
NC
VCC
RL0
RH0
RW0
No Connect
SO: Serial Output
4
No Connect
SO is the serial data output pin. This pin is
used to transfer data out of the DP7261.
During a read cycle, data is shifted out on the
falling edge of the serial clock.
5
No Connect
6
No Connect
7
Supply Voltage
SCK: Serial Clock
8
Low Reference Terminal for Potentiometer 0
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the DP7261. Opcodes,
byte addresses or data present on the SI pin
are latched on the rising edge of the SCK.
Data on the SO pin is updated on the falling
edge of the SCK.
9
High Reference Terminal for Potentiometer 0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Wiper Terminal for Potentiometer 0
¯¯¯
CS
Chip Select
¯¯¯
WP
Write Protection
SI
A1
Serial Input
A0, A1: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of four
devices can be addressed on a single bus. A
match in the slave address must be made
with the address input in order to initiate
communication with the DP7261.
Device Address
RL1
Low Reference Terminal for Potentiometer 1
RH1
RW1
GND
NC
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
RH, RL: Resistor End Points
The RH and RL pins are equivalent to the
terminal connections on
potentiometer.
No Connect
a
mechanical
NC
No Connect
NC
No Connect
RW: Wiper
The RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
NC
No Connect
SCK
Bus Serial Clock
Hold
¯¯¯
CS: Chip Select
¯¯¯¯¯
HOLD
¯¯¯
¯¯¯
CS is the Chip select pin. CS low enables
¯¯ high disables the
the DP7261 and CS
¯¯¯
DP7261. CS high takes the SO output pin to high impedance and forces the devices into a Standby mode
(unless an internal write operation is underway). The DP7261 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a
valid write sequence is what initiates an internal write cycle.
¯¯¯
¯¯¯
¯¯¯
WP: Write Protect
¯¯¯
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
¯¯¯
WP is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register
¯¯¯ ¯¯¯
is allowed). WP going low while CS is still low will interrupt a write to the registers. If the internal write cycle has
¯¯¯
already been initiated, WP going low will have no effect on any write operation.
¯¯¯¯¯
HOLD: Hold
¯¯¯¯¯
The HOLD pin is used to pause transmission to the DP7261 while in the middle of a serial sequence without
¯¯¯¯¯
having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be
¯¯¯¯¯
¯¯¯¯¯
ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any
¯¯¯¯¯
time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor.
¯¯¯
WP: Write Protect Input
¯¯¯
The WP pin when tied low prevents non-volatile writes to the device (change of wiper control register is allowed)
and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 6 for
more details.
Doc. No. MD-2122 Rev. E
2
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7261
SERIAL BUS PROTOCOL
The DP7261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the DP7261 to interface directly with
many of today's popular microcontrollers. The
DP7261 contains an 8-bit instruction register. The
instruction set and the operation codes are detailed in
the instruction set table 3 on page 9.
DEVICE OPERATION
The DP7261 is two resistor arrays integrated with an
SPI serial interface logic, two 8-bit wiper control
registers and eight 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (RW) by a After the device is selected with
of the six op-codes that define the operation to be
performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper
control register. Data can be read or written to the
wiper control registers or the non-volatile memory
data registers via the SPI bus. Additional instructions
allows data to be transferred between the wiper
control registers and each respective potentiometer's
non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
¯¯¯
CS going low the first byte will be received. The part
is accessed via the SI pin, with data being clocked in
on the rising edge of SCK. The first byte contains one
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
3
Doc. No. MD-2122 Rev. E
DP7261
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC + 2.0
-0.2 to +7.0
1.0
Units
ºC
Temperature Under Bias
Storage Temperature
°C
V
Voltage on Any Pin with Respect to Ground (1) (2)
VCC with Respect to Ground
Package Power Dissipation Capability (TA = 25ºC)
Lead Soldering Temperature (10s)
Wiper Current
V
W
300
ºC
6
mA
RECOMMENDED OPERATING CONDITIONS
Parameters
VCC
Ratings
+2.5 to +6.0
-40 to +85
Units
V
Industrial Temperature
°C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol Parameter
Test Conditions
Units
Min
Typ.
100
50
Max
RPOT
RPOT
Potentiometer Resistance (-00)
k
k
Potentiometer Resistance (-50)
Potentiometer Resistance
Tolerance
RPOT Matching
20
1
%
%
mW
mA
Power Rating
25°C, each pot
50
IW
RW
Wiper Current
3
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Noise
IW = 3mA @ VCC = 3V
IW = 3mA @ VCC = 5V
200
100
300
150
VCC
RW
VTERM
VN
0
V
(4)
nV¥Hz
Resolution
0.4
%
Absolute Linearity (5)
Relative Linearity (6)
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
Rw(n)(actual)-R(n)(expected)(8)
Rw(n+1)-[Rw(n)+LSB](8)
1
LSB (7)
LSB (7)
ppm/ºC
ppm/ºC
pF
0.2
TCRPOT
TCRATIO
(4)
(4)
(4)
300
20
CH/CL/CW Potentiometer Capacitances
fc Frequency Response
10/10/25
0.4
(4)
RPOT = 50k
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = RTOT / 255 or (RH - RL) / 255, single pot
(8) n = 0, 1, 2, ..., 255
Doc. No. MD-2122 Rev. E
4
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7261
D.C. OPERATING CHARACTERISTICS
CC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter Test Conditions
SCL = 400kHz, SDA = Open
V
Min
Max
1
Units
mA
f
ICC1
Power Supply Current
VCC = 6V, Inputs = GNDs
Power Supply Current
Non-volatile WRITE
fSCK = 400kHz, SDA Open
5
mA
ICC2
VCC = 6V, Input = GND
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC, SDA = Open
VIN = GND to VCC
1
10
µA
µA
µA
V
ILO
VOUT = GND to VCC
10
VIL
-1
VCC x 0.3
VIH
VOL1
VOH1
Input High Voltage
VCC x 0.7 VCC + 1.0
V
Output Low Voltage (VCC = 3.0V) IOL = 3mA
Output High Voltage IOH = -1.6mA
0.4
V
VCC – 0.8
V
PIN CAPACITANCE(1)
TA = 25ºC, f = 1.0MHz, VCC = 5V, unless otherwise specified.
Symbol Test
Conditions
Max
8
Units
pF
(1)
COUT
Output Capacitance (SO)
¯¯¯
VOUT = 0V
VIN = 0V
(1)
¯¯¯ ¯¯¯¯¯
CIN
6
pF
Input Capacitance (CS, SCK, SI, WP,HOLD, A0, A1)
A.C. CHARACTERISTICS
Symbol Parameter
Test Conditions
Units
ns
Min
50
Max
tSU
tH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
50
ns
tWH
tWL
fSCK
tLZ
125
125
DC
ns
ns
3
50
2
MHz
ns
¯¯¯¯¯
HOLD to Output Low Z
(1)
tRI
Input Rise Time
Input Fall Time
µs
(1)
tFI
2
µs
¯¯¯¯¯
CL = 50pF
tHD
tCD
tV
100
100
ns
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
ns
Output Valid from Clock Low
Output Hold Time
200
ns
tHO
tDIS
tHZ
0
ns
Output Disable Time
250
100
ns
¯¯¯¯¯
HOLD to Output High Z
ns
¯¯¯
tCS
tCSS
tCSH
2
ns
CS High Time
¯¯¯
250
250
ns
CS Setup Time
¯¯¯
CS Hold Time
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2122 Rev. E
DP7261
POWER UP TIMING (1)(2)
Symbol Parameter
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
DP TIMING
Symbol Parameter
tWRPO Wiper Response Time After Power Supply Stable
tWRL Wiper Response Time After Instruction Issued
WRITE CYCLE LIMITS
Min
5
Max
10
Units
µs
5
10
µs
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
V
(3)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
(3)
ILTH
100
mA
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
Figure 1. Synchronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
H
t
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line = mode (1, 1)
Doc. No. MD-2122 Rev. E
6
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7261
¯¯¯¯¯
Figure 2. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
by CMOS input signals or tied to VCC or VSS. The
remaining two bits in the device address byte must be
set to 0.
INSTRUCTION AND REGISTER
DESCRIPTION
DEVICE TYPE / ADDRESS BYTE
INSTRUCTION BYTE
The first byte sent to the DP7261 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
DP7261 are fixed at 0101[B] (refer to Table 1).
The next byte sent to the DP7261 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I3 - I0. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the DP7261 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
0
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
(MSB)
ID2
1
ID1
0
ID0
A3
A2
A1
A0
(LSB)
1
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
7
Doc. No. MD-2122 Rev. E
DP7261
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as standard memory locations for system
parameters or user preference data.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The DP7261 contains two 8-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of
256 switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be
written by the host via Write Wiper Control Register
instruction; it may be written by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction; it can be modified
one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.
Write in Process
The contents of the Data Registers are saved to
¯¯¯
nonvolatile memory when the CS input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
INSTRUCTIONS
Five of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in the
WCR
The Wiper Control Register is a volatile register that
loses its contents when the DP7261 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
Data Registers (DR)
— Read Data Register – read the contents of the
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
selected Data Register
— Write Data Register – write a new value to the
selected Data Register
— Read Status – Read the status of the WIP bit
which when set to "1" signifies a write cycle is in
progress.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Instruction
Operation
I3
I2
I1
I0
R1
R0
WCR1/ P1 WCR0/ P0
Read Wiper Control Register
1
0
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Wiper Control
Register pointed to by P1-P0
Write new value to the Wiper Control
Register pointed to by P1-P0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
Transfer the contents of the Data
Register pointed to by P1-P0 and R1-
R0 to its associated Wiper Control
Register
Write Wiper Control Register
Read Data Register
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
Write Data Register
XFR Data Register to Wiper
Control Register
XFR Wiper Control Register
to Data Register
1
0
1
0
1
0
0
1
1/0
1/0
1/0
1/0
1/0
0
1/0
0
Transfer the contents of the Wiper
Control Register pointed to by P1-P0 to
the Data Register pointed to by R1-R0
Transfer the contents of the Data
Registers pointed to by R1-R0 of all
four pots to their respective Wiper
Control Registers
Global XFR Data Registers
to Wiper Control Registers
Global XFR Wiper Control
Registers to Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper
Control Registers to their respective
data Registers pointed to by R1-R0 of
all four pots
Increment/Decrement Wiper
Control Register
Read Status (WIP bit)
0
0
0
1
1
0
0
1
0
0
0
0
1/0
0
1/0
1
Enable Increment/decrement of the
Control Latch pointed to by P1-P0
Read WIP bit to check internal write
cycle status
Doc. No. MD-2122 Rev. E
8
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7261
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
potentiometers and one of its associated registers; or
the transfer can occur between both potentiometers
and one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is differ-
ent from the other commands. Once the command is
issued the master can clock the selected wiper up
and/ or down in one segment steps; thereby providing
a fine tuning capability to the host. For each SCK
clock pulse (tHIGH) while SI is HIGH, the selected wiper
will move one resistor segment towards the RH
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
DP7261; either between t he host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0
A2 A1 A0
A3
I3 I2 I1
I0
R1 R0 P1 P0
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 8. Three-Byte Instruction Sequence
0
1
0
1
0
0
SI
I3
ID0 A3 A2 A1 A0
I1
P1 P0 D7 D6 D5 D4 D3 D2 D1 D0
I0 R1 R0
I2
ID3 ID2
ID1
Internal
Address
Device ID
Instruction
Opcode
Data
Pot/WCR
WCR[7:0]
or
Register Address
Address
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
0
0
SI
ID3 ID2 ID1 ID0
A3 A2 A1 A0
I3
I2
I1
I0
R1 R0 P1 P0
I
I
D
E
C
1
I
D
E
C
n
N
C
N
C
2
N
C
n
Instruction
Opcode
Pot/WCR
Data
Internal
Address
Device ID
Address 1
Register
Address
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
9
Doc. No. MD-2122 Rev. E
DP7261
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRL
SCK
SI
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0
1
0
1
0
0
A
1
A 1 0
0
0
1
0
0
P
1
P
0
7
6
5
4
3
2
1
0
¯¯¯
CS
¯¯¯
CS
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0
1
0
0
A
1
A
0
1
0
1
0
0
0
P
1
P
0
7
6
5
4
3
2
1
0
¯¯¯
CS
¯¯¯
CS
Read Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1
0
0
A
1
A
0
1 0 1 1 R
1
R
0
P
1
P 7 6 5 4 3 2 1 0
0
¯¯¯
CS
¯¯¯
CS
Write Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
High Voltage
Write Cycle
0 1 0 1 0 0 A A 1 1 0 0 R R P P 7 6 5 4 3 2 1 0
¯¯¯
CS
¯¯¯
CS
1 0
1 0 1 0
Read Status (WIP)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1
0
0
A
1
A
0
0
1
0
1
0
0
0
1
7
0
6
0
5
0
4
0
3
0
2
0
1 W
¯¯¯
CS
¯¯¯
CS
0
I
P
Doc. No. MD-2122 Rev. E
10
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7261
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES INSTRUCTION
0 1 0 1
0
0
A
1
A
0
0 0 0 1 R R
1 0
0
0
¯¯¯
CS
¯¯¯
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High Voltage
Write Cycle
0 1 0 1 0
0
A
1
A 1 0 0 0 R R 0
0
¯¯¯
CS
¯¯¯
CS
0
1 0
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High Voltage
Write Cycle
0 1 0 1 0
0
A
1
A 1 1 1 0 R R P P
¯¯¯
CS
¯¯¯
CS
0
1 0
1
0
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
0 1 0 1
0
0
A
1
A
0
1 1 0 1 R R P
P
0
¯¯¯
CS
¯¯¯
CS
1 0
1
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES INSTRUCTION
0 0 1 0 0
DATA
0 1 0 1
0
0
A
1
A
0
0
P P I/D I/D
1 0
. . .
I/D I/D
¯¯¯
CS
¯¯¯
CS
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2122 Rev. E
DP7261
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead 300mils (W)
SYMBOL
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
A
A1
A2
b
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
b
e
L
Q
PIN#1 IDENTIFICATION
Q1
5°
15°
TOP VIEW
h
D
h
Q1
A2
Q
A
Q1
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC specification MS-013.
Doc. No. MD-2122 Rev. E
12
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7261
TSSOP 24-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
Q1
0.50
0°
0.70
8°
e
TOP VIEW
D
c
A2
A1
A
Q1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC specification MO-153.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
13
Doc. No. MD-2122 Rev. E
DP7261
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
DP
7261
W
I
-00
- T1
Package
W: SOIC
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
Resistance
50: 50k
00: 100k
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Company ID
Product Number
7261
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The device used in the above example is a DP7261WI-00-T1 (SOIC, Industrial Temperature, 100k, Tape & Reel).
Ordering Part Number
DP7261WI-50
DP7261WI-00
DP7261YI-50
DP7261YI-00
Doc. No. MD-2122 Rev. E
14
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
11/18/2003
05/04/2004
A
B
Initial Issue
Updated wiper resistance from 50 to 100
Updated Functional Diagram
¯¯¯
Updated WP Pin Description
Updated notes in Absolute Max Ratings Eliminated Commercial temp range in all areas
Updated Potentiometer Characteristics table
Updated DC Characteristics table
Updated Pin Capacitance table
Updated AC Characteristics table
Added DP Timing Table on page 6
Corrected Synchronous Data Timing (Figure 1) drawing
09/21/2004
07/31/2007
02/07/2008
C
D
E
Updated Figure 8 (Three Byte Instruction Sequence)
Updated Example of Ordering Information
Update Package Outline Drawings
Added MD- to document number
Update Instruction Format – Read Data Register (DR) and Write Data Register (DR)
NIDEC COPAL ELECTRONICS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
NIDEC COPAL ELECTRONICS CORP. product s are not de signe d, int e nde d, or aut horize d for use as compone nt s in syst e ms int e nde d for surgical implant int o t he body, or
ot he r applicat ions int e nde d t o support or sust ain life , or for any ot he r applicat ion in which t he failure of t he NIDEC COPAL ELECTRONICS CORP. product could cre at e a
sit uat ion where personal injury or deat h may occur.
NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s
labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.
NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e
t ypical semiconduct or applicat ions and may not be complet e.
NIDEC COPAL ELECTRONICS CORP.
Japan Head Office
Nishi-Shinjuku, Kimuraya Bldg.,
7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023
Document No: MD-2122
Phone: +81-3-3364-7055
Fax: +81-3-3364-7098
Revision:
E
Issue date:
02/07/08
www.nidec-copal-electronics.com
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