NJU#7380E-TE2 [NJRC]
Micro Peripheral IC,;
| 型号： | NJU#7380E-TE2 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Micro Peripheral IC, |
| 文件： | 总7页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU7380
STEPPER MOTOR CONTROLLER
■GENERAL DESCRIPTION
■PACKAGE OUTLINE
NJU7380 is a controller with transrator which convert
from input step and direction pulse to driver's phase signal
for full and half step.
NJU7380 translates from pulse input signal (Serial
interface) to phase signal input, so NJM3700 series dual
channel bipolar drivers or NJM2672 dual H-bridge driver
can be easily controlled by a micro processor .
NJU7380 is also including Auto Current Down (ACD)
circuit which is suitable for reducing power dissipation of
power devices and motor.
NJU7380E
■
FEATURES
• Operating Voltage VDD=4.75 5.25V
Absolute Maximum Voltage 7V
•
• Half -step and Full - step Operation
• Internal Phase Logic
• Phase Logic Reset Terminal(RESET)
• Internal Auto Current Down Function
• Specially matched to NJM3775,NJM3777 and NJM2672.
• C-MOS Technology
• Package Outline EMP14
■PIN CONFIGURATIONS
14
13
12
11
1
2
1. DIR
2. STEP
3. HSM
4. RESET 11. Dis1
5. MO
6. Ct
8. PGND
9. ACD
10. Dis2
3
12. P2
13. P1
4
5
6
7
10
9
7. SGND 14. VDD
8
Fig. 1Pin Configurations
- 1 -
NJU7380
■BLOCK DIAGLAM
VDD
POR
P1
STEP
DIR
Dis1
HSM
RESET
P2
Phase Logic
&
ACD Logic
Dis2
ACD
Ct
SGND
MO
PGND
Fig.2 Block Diagram
■PIN DESCRIPTION
Pin
1
Pin name
DIR
Description
Direction command input for determining motor turning direction
2
STEP
Motor steeping pulse input, phase logic operation triggered by negative edge of
STEP signal
3
HSM
Half/Full step mode switching input
H level in full step mode and L level in half step mode
4
5
6
RESET
MO
Ct
Phase logic initial input
Phase output initial status detection output
A value of connected capacitor determines lock detection time (Ton) and auto
resume time (Toff)
7
8
9
SGND
PGND
ACD
SGND (Logic GND) and PGND (Analog GND) is not connect in the IC
SGND and PGND pins should be connected ground respectively.
Auto Current Down output terminal
L level in active
10
11
12
13
14
DIS2
DIS1
P2
P1
VDD
Step sequence output terminals
P1/DIS1(P2/DIS2) determine a sequence output on Phase1(2) for driver IC
P1(P2) determine a motor current direction on Phase1(2) for driver IC
DIS1(DIS2) determine a phase current OFF mode at the half-step
Logic power supply voltage terminal
- 2 -
NJU7380
■ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
NOTE
PARAMETER
RATINGS
SYMBOL [unit]
Supply Voltage
Input Voltage
+7.0
-0.3 VDD+0.3
10
VDD[V]
VID[V]
Output Current
IO [mA]
TOPR[°C]
TSTG [°C]
PD [mW]
Operating Temperature Range
Storage Temperature Range
Power Dissipation
-40 85
-40 +125
300
Device itself
■RECOMMENDED OPERATING CONDITIONS
VDD=4.75V 5.25V
■ELECTRICAL CHARACTERISTICS
(V+=5V, Ta=25°C)
PARAMETER
SYSMBOL
IDD
CONDITION
MIN.
-
TYP.
0.2
MAX.
0.3
UNIT
mA
Operating Current
No Signal
H Level Input Voltage
L Level Input Voltage
H Level Input Current
VIH
VIL
-
-
3.5
-
-
-
-
V
V
1.5
IIH
IIL
-
-
-
-
0.1
-50
1.0
µA
µA
V
L Level Input Current
-100
Phase Output
Saturation Voltage
DIS Output
IP=5mA
VP
-
-
0.5
IDIS=5mA
IMO=5mA
VDIS
VVR
VMO
ILEAK
TON
-
-
-
-
-
-
0.5
0.5
0.5
1
V
V
Saturation Voltage
VR Detection Voltage
-
-
MO Output Saturation
Voltage
IMO=5mA
V
Output Leak Current
VDD =7V
-
µA
ms
Power Down ON
Time
CT=0.1µF
200
-
Turn ON Time
Set-up Time
TDON
TS
-
-
-
-
-
3
-
µs
400
ns
Step-pulse
Continuation Time
VSPC
-
800
-
-
ns
- 3 -
NJU7380
■APPLACATION INFORMATION
V
CC（+5V）
VMM
10kΩ
+
R1
R3
4.7µF
0.1µF
10µF
4×10kΩ
14
VDD
SETP
9
ACD
12
VCC
4
VMM1
19
VMM1
2
13
11
9
3
1
Phase1
PA
STEP
MA1
MB1
1
3
10
7
Dis1
VR1
Direction
DIR
Dis1
NJU
7380
Half／Full Step
HSM
NJM3775
4
6
14
12
10
20
22
RESET
RESET
Phase2
Dis2
PB
Dis2
MO
MA2
MB1
12
16
Ct
STEPPER
MOTOR
5
VR2
MO
+5V
E1
C2
21
RC GND
5,6,
C1
E2
15
PGND
8
SGND
7
12kΩ
4700pF
11
8
2
Pin number refer
to DIP package
R2
17,18
GND(VCC)
RS
0.47Ω
RS
0.47Ω
GND(VMM
)
Fig.3 Typical stepper motor driver application with NJM3775.
■FUNCTIONAL DESCRIPTION
NJU7380 is a transrator, intended to convert from input step and direction pulse to driver's phase signal for 2-
phase stepper motor driver. Motor control is simply attained only by the pulse generator because you use it by
NJM3775 and the set.
■LOGIC INPUT
NJU7380 contains all phase logic necessary to control the motor in a proper way. If any of the logic inputs are left
open, the circuit will accept it as a HIGH level. In order to make noise-proof nature into the maximum, it is
necessary to connect an idle input terminal to VDD level.
• STEP – Stepping pulse
The built-in phase logic sequencer goes UP on every negative edge of the STEP signal (pulse). In full step
mode, the pulse turns the stepping motor at the basic step angle. In half step mode, two pulses are required to
turn the motor at the basic step angle.
The DIR (direction) signal and HSM (half/full mode) are latched to the STEP negative edge and must
therefore be established before the start of the negative edge. Note the setup time ts in Figure 4.
• DIR – direction
The DIR signal determines the step direction. The direction of the stepping motor depends on how the
NJU7380 and NJM3775 are connected to the motor. Although DIR can be modified this should be avoided
since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. See the timing
chart in Figure 4.
- 4 -
NJU7380
• HSM – half/full step mode switching
This signal determines whether the stepping motor turns at half step or full step mode. The built-in phase
logic is set to the half step mode when HSM is low level. Although HSM can be modified this should be
avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. See
the timing chart in Figure 4.
• RESET
A two-phase stepping motor repeats the same winding energizing sequence every angle that is a multiple of
four of the basic step. The phase logic sequence is repeated every four pulses in the full step mode and every
eight pulses in the half step mode.
RESET forces to initialize the phase logic to sequence start mode.
When RESET is at L level, the phase logic is initialized and the energizing pattern of phase logic at
sequence start is output. At this time, the STEP input of phase logic will be ignored during the RESET is at Ｌ
level.
■POR – power on and reset function
The internal power-on and reset circuit, which is connected to Vcc, resets the phase logic and turns off phase
output when the power is supplied to prevent missteps.
Each time the power is turned on, the energizing pattern of phase logic at sequence start is output.
■MO – origin monitor
At sequence start of the phase logic or after POR or external RESET, an L level output is made to indicate to
external devices that the energizing sequence is in initial status.
In a system using a stepping motor, the device sensor and the MO AND function enable a higher resolution
detection of motor origin.
HSM,DIR
STEP,RESET
ts
tp
Vp
td
Fig.4 Timing chart
- 5 -
NJU7380
■TIMING CHART
POR
1
2
3
4
1
2
3
4
1
DIR
H
Fig.5-1 Full-step mode,forward
4-step sequence
HSM
H
H
STEP
PA OFF
PB OFF
DISA ON
DISB ON
MO
ON
POR
1
2
3
4
1
2
3
4
1
Fig.5-2 Full-step mode,reverse
4-step sequence
DIR
L
HSM
H
H
STEP
PA OFF
PB OFF
DISA ON
DISB ON
MO
ON
POR
1
2
3
4
5
6
7
8
1
Fig.5-3 Half-step mode,forward
8-step sequence
DIR
H
L
HSM
STE
H
PA OFF
PB OFF
DISA ON
DISB ON
MO
ON
POR
1
2
3
4
5
6
7
8
1
Fig.5-4 Half-step mode,reverse
8-step sequence
DIR
L
HSM
L
STEP
H
PA OFF
PB OFF
DISA ON
DISB ON
MO
ON
- 6 -
NJU7380
■ACD– auto current down function
The ACD feature monitors step signals and sets the ACD pin output to H when the negative edge of a STEP
signal is input. It then sets the ACD output to L after a time (TON) that is fixed by the capacitor that is connected to
the Ct pin.
By combining this pin with the VR pin that determines motor current for the NJM3775 motor, it is possible to
reduce current when stopping the motor.
If the next negative edge of a STEP is input during the time TON, an internal retrigger will operate, maintaining the
ACD pin's H output.
That is, after the final negative edge of a STEP is input, ACD H output is maintained during the time TON, after
which it is set to L.
The time TON must be long enough to securely stop the stepping motor.
Approximately 100mS is usually sufficient for normal applications.
The following expression determines the time TON.
Ton[ms]=3×109×Ct[F]
STEP
PA
PB
AC
D
CT
Normal Revolution State
ACD Operation State
TON=2x106xCT
TON
TON
Fig.6 ACD Operation Timing Diagram
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 7 -
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