NJU26160 [NJRC]
NJU26100 Series Hardware Specification; NJU26100系列硬件规格
| 型号： | NJU26160 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | NJU26100 Series Hardware Specification |
| 文件： | 总17页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU26100 Series
NJU26100 Series Hardware Specification
■
General Description
■Package
This document describes the NJU26100 Series common hardware specifications.
This document is applied to the NJU26101 up to the NJU26199.
The individual function is described in the each data sheet. Please refer to the
each data sheet to find the detail functions. The firmware commands are
described in the each firmware document.
NJU26100 Series
■
Hardware Specification
• 24bit Fixed-point Digital Signal Processing
• Maximum System Clock Frequency
• Digital Audio Interface
: 38MHz
: 3 Input ports / 3 Output ports
• Master / Slave Mode
• Master Mode MCK
:1/2 fclk, 1/3 fclk
ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs
• Two kinds of micro computer interface
I2C bus (standard-mode/100kbps)
Serial interface (4 lines: clock, enable, input data, output data)
• Power Supply
• Package
: 2.5V ( 3.3V Input tolerant )
: QFP32-R1
NJU26100 Series
AD1/SDIN AD2/SSb
SERIAL AUDIO
INTERFACE
DSP ARITHMETIC UNIT
SCL/SCK
BCKO
LRO
SERIAL
HOST
PROGRAM
CONTROL
INTERFACE
SDA/SDOUT
SERIAL OUT
SERIAL OUT
SERIAL OUT
SERIAL IN
SDO0
SDO1
SDO2
24-BIT x 24-BIT
MULTIPLIER
ALU
RESETb
SDI0
SDI1
MCK
XI
SERIAL IN
TIMING
GENERATOR
ADDRESS GENERATION UNIT
SERIAL IN
SDI2
XO
BCKI
LRI
DELAY
RAM
DATA
RAM
FIRMWARE
ROM
GPIO0
GPIO1
GPIO AND
CONFIGURATION
INTERFACE
Ver.2005-02-24
- 1 -
NJU26100 Series
■
Pin Configuration
SDI0
GPIO1
VSSC
VDDC
RESETb
VSSO
XO
SDI1
SDI2
LRI
NJU26100
Series
BCKI
MCK
BCKO
LRO
XI
VDDO
■
Pin Description
Pin Description
No. Symbol
I/O Description
No. Symbol I/O Description
1
SDO2
O
O
O
Audio Data Output CH2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDDC
VDDC
VSSC
VSSC
VDDR
VDDR
VSSR
VSSR
SDI0
--
--
--
--
--
--
--
--
I
Core Power Supply +2.5V
Core Power Supply +2.5V
Core GND
2
SDO1
Audio Data Output CH1
Audio Data Output CH0
3
SDO0
4
GPIO0
SCL/SCK
SDA/SDOUT
AD1/SDIN
AD2/SSb
VDDO
XI
I/O General Purpose IO
Core GND
5
I
I2C Clock / Serial Clock
I/O Power Supply +2.5V
I/O Power Supply +2.5V
I/O GND
6
I/O I2C I/O / Serial Output
7
I
I2C Address / Serial Input
I2C Address / Serial Enable
OSC Power Supply +2.5V
X’tal Clock Input
8
I
I/O GND
9
--
I
Audio Data Input CH0
Audio Data Input CH1
Audio Data Input CH2
LR Clock Input
10
11
12
13
14
15
16
SDI1
I
XO
O
--
I
OSC Output
SDI2
I
VSSO
OSC GND
LRI
I
RESETb
VDDC
RESET (active Low)
Core Power Supply +2.5V
Core GND
BCKI
MCK
I
Bit Clock Input
--
--
O
O
O
Master Clock Output
Bit Clock Output
VSSC
BCKO
LRO
GPIO1
I/O General Purpose IO
LR Clock Output
*1 I : Input, O : Output, I/O : Bi-directional
*2 SDI0, SDI1, SDI2, SDO0, SDO1, SDO2, GPIO0, GPIO1 are different by any function. Refer to each datasheet.
Ver.2005-02-24
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NJU26100 Series
1. Electric Characteristics
1.1 Absolute Maximum Ratings
Table1-1 Absolute Maximum Ratings (VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Supply Voltage
XI Input Voltage
Symbol
VDD
Vx(OSC)
Rating
0 to 3.05
-0.3 to VDD
Units
V
V
Input Pin Voltage
Power Dissipation
Storage Temperature
Vx(IN)
PD
Tstg
-0.3 to 3.6
0.3
-40 to +125
V
W
°C
*1 They apply SCL/SCK, AD1/SDIN, AD2/SSb, RESETb, SDI0, SDI1, SDI2, LRI, and BCKI pin. It applies to GPIO0
(SEL1) pin of NJU26100 series except NJU26150. However, it applies to SDA/SDOUT pin at the time of I2C
mode operation.
Ver.2005-02-24
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NJU26100 Series
1.2 Electric Characteristics
Table1-2 Electric Characteristics (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Operating VDD Voltage
Operating Current
Symbol
VDD
Test Condition
VDDO, VDDC, VDDR pin
fOSC=36.864MHz
Min.
2.25
-
Typ.
2.5
40
Max.
2.75
-
Units
V
mA
IDD
Operating Temperature
TOPR
-40
25
85
°C
Recommended Operating
TOPRR
VDDO=VDDC=VDDR =2.5V
-10
25
70
°C
Temperature
High Level Input
Voltage (XI)
High Level Input Voltage
Low Level Input Voltage
VIH(OSC) XI pin
VIH
VIL
2.0
-
VDD
V
2.0
VSS
-
-
3.3
0.5
V
V
VSS=VSSO=VSSC=VSSR
VIN =3.3V
High Level Input Current
IIH
-10
-
+10
µA
expect for GPIO pin
VIN =3.3V
High Level Input Current
Low Level Input Current
High Level Output Voltage
IIH(pd)
IIL
100
-10
-
-
-
300
+10
-
µA
µA
V
GPIO pin Only
VIN=VSSO=VSSC=VSSR
IOH=-2mA
VDD -0.4
VOH
VDD -0.1
IOH=-100µA
Low Level Output Voltage
Input Capacitance
VOL
CIN
IOL=2mA
-
-
-
5
0.4
-
V
pF
except for SCL/SCK,
SDA/SDOUT,
Input Rise/Fall transition Time
tr / tf
-
-
100
ns
AD1/SDIN, AD2/SSｂ
pin*1
XI pin
XI pin
Clock Frequency
Ext.System Clock Duty Cycle
fOSC
rEC
-
-
50
38.0
52.5
MHz
%
47.5
*1 The tr / tf of these pins are specified separately.
*2 All input / input-and-output pins serve as the Schmidt trigger input except for XI pin.
VDDC
VDDO
XO
pin
VSSO
VSSC
VDDR
VDDC
VDDR
Output
XI
Input
pin
pin
pin
VSSR
VSSC
Input pin
Output pin
XI / XO pin
(XI, XO)
(GPIO0, SCL/SCK, SDA/SDOUT,
AD1/SDIN, AD2/SSb, RESETb, GPIO1,
SDI0, SDI1, SDI2, LRI, BCKI pin)
(SDO0, SDO1, SDO2, GPIO0,
*3SDA/SDOUT, GPIO1, MCK,
BCKO, LRO pin)
Fig.1- 1 I/O Equivalent Circuits
*3 SDA becomes Open-Drain at the time of the output of I2C.
Ver.2005-02-24
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NJU26100 Series
2. Clock and Reset
The NJU26100 Series XI pin requires the system clock that should be related to the sample frequency Fs. The
XI/XO pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator.
When the external oscillator is connected to XI/XO pins, check the voltage level of the pins. Because the
maximum input voltage level of XI pin is deferent from the other input or bi-directional pins. The maximum
voltage-level of XI pin equals to VDD.
To initialize the NJU26100 Series, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26100 Series.
To select I2C bus or 4-Wire serial bus, some level should be supplied to GPIO0 pin (SEL1 pin). When GPIO0 pin
(SEL1 pin)=”Low”, I2C bus is selected. When GPIO0 pin (SEL1 pin)=”High”, 4-Wire serial bus is selected. The level
of GPIO0 pin (SEL1 pin) is checked by the NJU26100 Series in 1 m sec after RESETb pin level goes to “High”.
After the power supply and the oscillation of the NJU26100 Series becomes stable, RESETb pin should be kept
Low-level more than tRESETb period.
VDD
OSC unstable
XI
OSC stable
tRESETb
RESETb
Fig. 2- 1 Reset Timing
Table 2- 1 Reset Time
Symbol
tRESETb
Time
≥1µs
Notice :
Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts.
NJRC would not take the responsibility on the external parts of clock generating.
Ver.2005-02-24
- 5 -
NJU26100 Series
3. Audio Clock
Audio data samples must be transferred in synchronism between all components of the digital audio system.
That is, for each audio sample originated by an audio source there must be one and only one audio sample
processed by the NJU26100 Series and delivered to the D/A converters. To accomplish this, one device in the
system is selected to generate the audio sample rate; the remaining devices are designated to follow this sample
rate. The device that generates the audio sample rate is called the MASTER device; all devices following this
sample rate are called SLAVE(s).
LR, BCK and MCK should be synchronized. This is described in next section. When the NJU26100 Series is in
MASTER mode, the NJU26100 Series system clock should be 768 multiples of the sampling frequency (Table3-1).
When the NJU26100 Series is in SLAVE mode, NJU26100 Series system clock should be from 768 multiples of
the sampling frequency up to the maximum operating frequency.
3.1 System Clock
Three types of clock signals are included in the serial audio interface. Two of the clock signals LR (LRI and LRO)
and BCK (BCKI and BCKO) establish data transfer on the serial data lines. The third clock, MCK, is not associated
with serial data transfer but is required by delta-sigma A/D and D/A converters.
The frequency of the LR clock is, by definition, equal to the digital audio sample rate, Fs. BCK and MCK operate
at multiples of the LR clock rate. Therefore the signals LR, BCK and MCK must be locked, that is, they must be
generated or derived from a single frequency reference. In SLAVE mode, the NJU26100 Series dose not generate
MCK clock.
Table 3-1 Sampling Frequency and BCK, MCK, XI
Clock Signal
LR
Multiple Frequency
1Fs
32kHz
44.1kHz
44.1kHz
48kHz
32kHz
48kHz
BCK(32Fs)
BCK(64Fs)
MCK(256Fs)
MCK(384Fs)
XI
32Fs
1.024MHz
2.048MHz
8.192MHz
12.288MHz
24.576MHz
1.4112MHz
2.822MHz
11.289MHz
16.934MHz
33.8688MHz
1.536MHz
3.072MHz
12.288MHz
18.432MHz
36.864MHz
64Fs
256Fs
384Fs
768Fs
SDIx
SDOx
BCKO
BCKI
LRI
LRO
MCK
CLOCK
DIVIDER
MAS TER
SLAVE
XI
XO
Oscillator
Fig. 3-1 MASTER / SLAVE Mode
Ver.2005-02-24
- 6 -
NJU26100 Series
4. Audio Interface
The serial audio interface carries audio data to and from the NJU26100 Series. Industry standard serial data
formats of I2S, MSB-first left-justified or MSB-first right-justified are supported. These serial audio formats define a
pair of digital audio signals (stereo audio) on each data line. Two clock lines, BCK (bit clock) and LR (left/right word
clock) establish timing for serial data transfers.
The NJU26100 Series serial audio interface includes three data input lines, SDI0, SDI1 and SDI2, and three data
output lines, SDO0, SDO1 and SDO2, as shown in the figure below. The input serial data is selected by the
firmaware command. The number of these serial audio interfaces depends on the DSP function. Check the each
data sheet.
The NJU26100 Series has a pair of left/right clock lines (LRI and LRO) and a pair of bit clock lines (BCKI and
BCKO). Clock inputs BCKI and LRI are used to accept timing signals from an external device when the NJU26100
Series is operating in SLAVE clock mode.
The BCKO, LRO and MCK, system clock output, are provided for delta-sigma A/D and D/A converters when the
NJU26100 Series operates in MASTER mode. In SLAVE mode, the output of BCKO and LRO are the buffered
output of BCKI and LRI. The output of MCK is fixed to Low level in SLAVE mode.
Serial
Data
Serial
Data
SDO0
SDO1
SDO2
SDI0
SDI1
SDI2
Inputs
Outputs
NJU26100
Serial
Clock
Inputs
BCKI
LRI
BCKO
Serial
Clock
Outputs
LRO
MCK
System clock for
A/D, D/A converters
(DSP MASTER mode only)
Fig. 4-1 Serial Audio Interface
4.1 Audio Data Format
The NJU26100 Series can exchange data using any of three industry-standard digital audio data formats: I2S,
MSB-first Left-justified, or MSB-first Right-justified.
The three serial formats differ primarily in the placement of the audio data word relative to the LR clock.
Left-justified format places the most-significant data bit (MSB) as the first bit after an LR transition. I2S format places
the most-significant data bit (MSB) as the second bit after an LR transition (one bit delay relative to left-justified
format). Right-justified format places the least-significant data bit (LSB) as the last bit before an LR transition.
Clock LR (LRI, LRO) marks data word boundaries and clock BCK (BCKI, BCKO) clocks the transfer of serial
data bits. One period of LR defines a complete stereo audio sample and thus the rate of LR equals the audio
sample rate (Fs). All formats transmit the stereo sample left channel first. Note that polarity of LR is opposite in I2S
format (LR:LOW = Left channel data) compared to Left-Justified or Right-Justified formats.
Ver.2005-02-24
- 7 -
NJU26100 Series
The number of BCK clock must follow the serial data format. If the BCK clock is not enough, the right sound are
not produced. Set serial data format for the adequate mode that A/Ds, D/As or Codecs reqire.
The NJU26100 Series supports serial data format which includes 32(32Fs) or 64(64Fs) BCK clocks. This serial
data format is applied to both MASTER and SLAVE mode.
4.2 Serial Audio Data Transmitting Diagram
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23
32 Clocks
32 Clocks
Fig. 4-2 Left-Justified Data Format 64Fs, 24bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig. 4-3 Right-Justified Data Format 64Fs, 24bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig. 4-4 I2S Data Format 64Fs, 24bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19
32 Clocks
32 Clocks
Fig. 4-5 Left-Justified Data Format 64Fs, 20bit Data
* The 24bit data is always outputted to a SDO0 pin in the format of figure 4-5 to figure 4-10.
Ver.2005-02-24
- 8 -
NJU26100 Series
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig. 4-6 Right-Justified Data Format 64Fs, 20bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig. 4-7 I2S Data Format 64Fs, 20bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17
32 Clocks
32 Clocks
Fig. 4-8 Left-Justified Data Format 64Fs, 18bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig. 4-9 Right-Justified Data Format 64Fs, 18bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB
MSB
LSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig. 4-10 I2S Data Format 64Fs, 18bit Data
Ver.2005-02-24
- 9 -
NJU26100 Series
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks 16 Clocks
Fig. 4-11 Left-Justified Data Format 32Fs, 16bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks 16 Clocks
Fig. 4-12 Right-Justified Data Format 32Fs, 16bit Data
Left Channel
Right Channel
LRI, LRO
BCKI, BCKO
SDI, SDO
MSB
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks 16 Clocks
Fig. 4-13 I2S Data Format 32Fs, 16bit Data
Ver.2005-02-24
- 10 -
NJU26100 Series
4.3 Serial Audio Timing
Table 4-1 Serial Audio Input Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Symbol
fBCKI
Test Condition
Min
0.9
Typ.
-
Max
4.0
Units
MHz
BCKI Frequency **
BCKI Period
**
Low Pulse Width
tSIL
tSIH
85
85
-
-
ns
High Pulse Width
BCKI to LRI Time **
LRI to BCKI Time **
TSLI
tLSI
tDS
tDH
40
40
40
40
-
-
-
-
-
-
-
-
ns
ns
ns
ns
Data Setup Time
Data Hold Time
*
*
*
It is the regulation to BCKI in slave mode and to BCKO in master mode.
** It is the regulation in slave mode.
LRI
t
t
SIL
t
SLI
SIH
t
LSI
BCKI
t
DS
t
DH
SDI0,1
Fig. 4-14 Serial Audio Input Timing
Ver.2005-02-24
- 11 -
NJU26100 Series
Table 4-2 Serial Audio Output Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
BCKO to LRO Time *
Data Output Delay
Symbol
tSLO
tDOD
Test Condition
Min
-20
-
Typ.
-
-
Max
20
20
Units
ns
ns
CL:LRO, BCKO,
SDO=25pF
* It is the regulation in master mode.
LRO
t
SLO
BCKO
SDO
t
DOD
Fig. 4-15 Serial Audio Output Timing
Table 4-3 Serial Audio Clock Timing Parameters (In slave mode)
(VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Symbol
Test Condition
Min
Typ.
Max
20
Units
ns
Clock Output Delay
tPDL
-
-
CL:LRO,BCKO,
SDO=25pF
(LRI --> LRO)
Clock Output Delay
(BCKI --> BCKO)
tPDB
-
-
20
ns
LRI
LRO
t
PDL
BCKI
BCKO
t
PDB
Fig. 4-16 Serial Audio Clock Timing (In slave mode)
Ver.2005-02-24
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NJU26100 Series
5. Host Interface
The NJU26100 Series can be controlled via Serial Host Interface (SHI) using either of two serial bus formats:
4-Wire serial bus or I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. The SHI operates
only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and
initiates data transfers, regardless of the chosen communication protocol.
Table 5-1 Serial Host Interface Pin Description
Symbol
Pin No.
4-Wire Serial bus Format
I2C bus Format
(I2C / Serial)
SCL/SCK
5
6
Serial Clock
Serial Clock
Serial Data
SDA/SDOUT
Serial Data Output
(Bi-directional)
7
AD1/SDIN
Serial Data Input
I2C bus address Bit1
I2C bus address Bit2
8
AD2/SSb
SLAVE Select
Note : SDA /SDOUT pin is a bi-directional open drain.
SDA /SDOUT output is normal CMOS output in case of 4-Wire Serial bus mode and SSb=”Low”.
SDA /SDOUT output is Hi-Z state in case of 4-Wire Serial bus mode and SSb=”High”.
This pin requires a 4.7k pull-up resister in both 4-Wire serial and I2C bus mode.
5.1 4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting GPIO0 pin (*SEL1
pin)=”High” during the Reset initialization sequence. SHI bus communication is full-duplex; a write byte is shifted
into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first
and are enabled by setting the Slave Select pin Low (SSb = 0). Data is clocked into SDIN on rising transitions of
SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the
falling transitions of SSb. SDOUT is Hi-Z in case of SSb = “High”. SDOUT is CMOS output in case of SSb = “Low”.
SDOUT needs a pull-up resistor when SDOUT is Hi-Z.
* It excepts NJU26150. Refer to each data sheet.
Ver.2005-02-24
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NJU26100 Series
Table 5-2 4-Wire Serial Interface Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Symbol
tMSDr
tMSDf
Timelines
a-b
a-b
d-e
f-g
Min.
-
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Input Data Rising Time
-
-
-
-
-
-
-
-
100
Input Data Falling Time
Serial Clock Rising Time
Serial Clock Falling Time
Serial Strobe Rising Time
Serial Strobe Falling Time
Serial Clock High Duration
Serial Clock Low Duration
Serial Clock Period
-
100
tMSCr
tMSCf
tMSSr
tMSSf
-
100
-
100
p-q
m-n
e-f
-
100
-
100
tMSCa
tMSCn
tMSCc
tMSSs
tMSSh
tMSSa
tMSSn
tMSDis
tMSDih
50
50
250
100
30
-
-
-
-
-
-
-
-
-
-
g-h
e-i
Serial Strobe Setup Time
Serial Strobe Hold Time
Serial Strobe Low Duration
Serial Strobe High Duration
Input Data Setup Time
Input Data Hold Time
Output Data Delay
n-e
j-q
n-p
q-r
1.0
40
20
20
b-e
e-c
tMSDos
tMSDo
tMSDoh
n-o,CL=25pF
-
-
-
50
ns
(From SSb)
Output Data Delay
g-k(data-6),
CL=25pF
g-k(data-7)
q-l
-
50
ns
(From SCK)
Output Data Hold Time
Output Data Turn off Time (Hi-Z)
0
-
-
-
-
ns
ns
tMSDov
40
a
c
SDIN
SCK
7
1
0
6
5
j
d
e f g h
i
Note (3)
SDOUT
SSb
Hi-Z
6
5
1
Hi-Z
7
0
l
m
n
MSB
LSB
p
q
r
Fig. 5-1 4-Wire Serial Interface Timing
Note : *1 When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP
core at the transition of SSb=”High”.
*2 When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
*3 After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes
“High”.
*4 SDOUT is Hi-Z in case of SSb = “High”. SDOUT is CMOS output in case of SSb = “Low”.
SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level.
Ver.2005-02-24
- 14 -
NJU26100 Series
5.2 I2C Bus
When the NJU26100 Series is configured for I2C bus communication in GPIO0 pin (*SEL1 pin)=”Low”, the serial
host interface transfers data to the SDA pin and clocks data to the SCL pin. SDA is an open drain pin requiring an
external 4.7k pull-up resistor. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial
host interface. This offers additional flexibility to a system design by four different SLAVE addresses of the
NJU26100 Series. An address can be arbitrarily set up by the AD1, 2 pins. The I2C address of AD1, 2 is decided by
connection of AD1, 2 pins. The I2C address should be the same level of AD1, 2 pins. The real I2C address is
described in the each data sheet. Refer to the each data sheet.
* It excepts NJU26150. Refer to each data sheet.
Table 5-3 I2C Bus SLAVE Address
bit7
0
bit6
0
bit5
1
bit4
1
bit3
1
bit2
bit1
bit0
R/W
AD2*1
AD1*1
*1 The SLAVE address bit is 0 when ADx-pin is low level. The SLAVE address bit is 1 when ADx-pin is high level.
The figure on the following page shows the basic timing relationships for transfers. A transfer is initiated with a
START condition, followed by the SLAVE address byte. The SLAVE address consists of the seven-bit SLAVE
address followed by a read/write (R/W) bit. When an address with an effective serial host interface is detected, the
acknowledgement bit which sets a SDA line to Low in the ninth bit clock cycle is returned.
The R/W bit in the SLAVE address byte sets the direction of data transmission until a STOP condition terminates
the transfer. R/W = 0 indicates the host will send to the NJU26100 Series while R/W = 1 indicates the host will
receive data from the NJU26100 Series.
SDA
SCL
1-7
8
9
1-7
8
9
S
P
Start
Address
R/W ACK
Data
ACK
Stop
Fig. 5-2 I2C Bus Format
In case of the NJU26100 Series, only single-byte transmission is available.
The serial host interface supports “Standard-Mode (100kbps)” I2C bus data transfer.
Ver.2005-02-24
- 15 -
NJU26100 Series
Table 5-4 I2C Bus Interface Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Standard Mode
Parameter
Symbol
Units
Min
0
Max
SCL Clock Frequency
fSCL
tHD:STA
tLOW
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
Start Condition Hold Time
SCL “Low” Duration
SCL “High” Duration
Start Condition Setup Time
Data Hole Time
4.0
4.7
4.0
4.7
0
-
-
-
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
-
3.45
-
Data Setup Time
250
-
Rising Time
1000
300
-
Falling Time
tF
-
Stop Condition Setup Time
Bus Release Time
tSU:STO
4.0
4.7
tBUF
-
SDA
tBUF
tR
tF
tHD:STA
SCL
tSU:STA
t
tHD:STA tLOW
tHD:DAT
tHIGH
tSU:DAT
Sr
P
S
P
Fig. 5-3 I2C Bus Timing
■
I2C License
Purchase of I2C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies
conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the
system conforms to the I2C Standard specification as defined by Philips.
Ver.2005-02-24
- 16 -
NJU26100 Series
6. Package Dimensions (EIAJ : QFP032-P-0707-1)
Weight 0.2g (TYP)
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver. 1.14
Ver.2005-02-24
- 17 -
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