NJU26207V-TE2 [NJRC]
Digital Signal Processor,;
| 型号： | NJU26207V-TE2 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Digital Signal Processor, |
| 文件： | 总9页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU26207
Dolby Volume Decoder
ꢀ General Description
■Package
The NJU26207 is a digital signal processor that provides the function of Dolby Volume.
Dolby Volume solves volume level difference among channels, input sources and etc.
The mix balance is reproduced by high or low volume level.
The applications of NJU26207 are suitable for Digital TV, Front Surround Speaker and
speakers system.
ꢀ
Features
-Software
NJU26207V
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Dolby Volume (512FFT Window / 20Band)
Delay
Master Volume / Balance Control
Sampling Frequency : 32kHz, 44.1kHz, 48kHz
2 Input channels, 2 Output channels
-Hardware
ꢁ 24bit Fixed-point Digital Signal Processing
ꢁ Maximum Clock Frequency
ꢁ Digital Audio Interface
ꢁ Digital Audio Format
: 12.288MHz(Standard), built-in PLL Circuit
: 4 Input ports / 3 Output ports
: I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs
ꢁ Master / Slave Mode
ꢁ Microcomputer Interface
I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
ꢁ Operating Voltage
: VDD = VDDPLL = 1.8V
: VDDIO = 3.3V
ꢁ Input Terminal
ꢁ Package
: +5.0V Input tolerant
: SSOP44 (Pb-Free)
* The detail hardware specification of the NJU26207 is described in the “ NJU26200 Series Hardware Data Sheet”.
Ver.2008-12-03
- 1 -
NJU26207
ꢀ Hardware Block Diagram
AD1/SDIN AD2/SSb
SERIAL AUDIO
INTERFACE
DSP ARITHMETIC UNIT
SCL/SCK
SERIAL
HOST
BCKO
LRO
PROGRAM
INTERFACE
CONTROL
SDA/SDOUT
L/Rout
SDO0
SDO1
SDO2
24-BIT ｘ 24-BIT
(L+R)/2out
Monitor L/R
MULTIPLIER
ALU
RESETb
MCK
in
SDI0~3
BCKI
LRI
TIMING
GENERATOR
/ PLL
CLK
ADDRESS GENERATION UNIT
CLKOUT
PROC
MUTEb
SEL
General I/O
INTERFACE
DATA
RAM
FIRMWARE
ROM
WDC
Fig. 1 NJU26207 Hardware Block Diagram
ꢀ
Function Block Diagram
Delay
L/R(SDI0)
L/R(SDI1)
L/R(SDI2)
L/R(SDI3)
Dolby
Volume
L/R(SDO0)
(L+R)/2(SDO1)
Monitor L/R(SDO2)
Fig. 2 NJU26207 Function Block Diagram (Firmware)
Ver.2008-12-03
- 2 -
NJU26207
ꢀ Pin Configuration
SDI3
SDI2
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
VSS
SDI1
3
VSSIO
VDDIO
SDI0
4
LRI
5
SDO0
SDO1
SDO2
TEST
LRO
VDDIO
BCKI
6
7
VSS
8
VDD
9
TEST
MUTEb
WDC
PROC
VSSIO
VDDIO
SEL
10
11
12
13
14
15
16
17
18
19
20
21
22
BCKO
MCK
NJU26207
SSOP44
VDDIO
SDA/SDOUT
SCL/SCK
AD2/SSb
AD1/SDIN
TEST
VDDPLL
VSSPLL
VSS
TEST
TEST
VDD
RESETb
VDDIO
CLKOUT
CLK
VSSIO
Fig. 3 NJU26207 Pin Configuration
Ver.2008-12-03
- 3 -
NJU26207
ꢀ Pin Description
Table 1 Pin Description
Pin No.
Symbol
SDI3
SDI2
SDI1
SDI0
LRI
I/O
Function
1
I
I
I
I
I
-
I
-
-
Audio Data Input ch.3 (L/R)
Audio Data Input ch.2 (L/R)
Audio Data Input ch.1 (L/R)
Audio Data Input ch.0 (L/R)
LR Clock Input
I/O Power Supply +3.3V
Bit Clock Input
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
for test
2
3
4
5
6
7
8
9
VDDIO
BCKI
VSS
VDD
10
TEST *
I
connect with VSSIO through 3.3-ohm resistance.
Master Volume Status after reset ‘1’: 0dB, ‘0’: Mute
Watchdog Clock output pin (Open drain output)
Signal Processing after reset ‘1’: Normal Processing, ‘0’: Waiting for a
Command without Processing
11
12
MUTEb *
WDC *
I
OD
13
PROC *
I
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
-
-
I/O Power Supply GND
I/O Power Supply +3.3V
VSSIO
VDDIO
SEL
I
Host Interface Selection ‘1’: Serial Interface, ‘0’: I2C bus
PLL Power Supply +1.8V
VDDPLL
VSSPLL
VSS
-
-
PLL Power Supply GND
-
DSP Core Power Supply GND
VDD
-
DSP Core Power Supply +1.8V
OSC Clock Output
CLKOUT
CLK
O
I
OSC Clock Input (12.288MHz)
VSSIO
VDDIO
RESETb
TEST
-
I/O Power Supply GND
-
I/O Power Supply +3.3V
I
Reset (RESETb=’0’: DSP Reset)
for test (connect to VDDIO)
I
TEST
I
for test (connect to VSSIO)
TEST
I
for test (connect to VSSIO)
AD1/SDIN
AD2/SSb
SCL/SCK
SDA/SDOUT
VDDIO
I
I2CAddress (I2C mode) / Serial In (4-wire serial mode)
I2CAddress (I2C mode) / Serial enable (4-wire serial mode)
I2C SCL (I2C mode) / Serial clock (4-wire serial mode)
I2C SDA (I2C mode) / Serial Out (4-wire serial mode)
I/O Power Supply +3.3V
A/D, D/A clock output (buffer output of a CLK pin)
Bit Clock Output
I
I
I/O
-
O
O
O
O
O
O
O
-
MCK
BCKO
LRO
LR Clock Output
TEST
SDO2
SDO1
SDO0
VDDIO
VSSIO
VSS
For test (Non connect)
Audio Data Output ch.2 (Monitor L/R)
Audio Data Output ch.1 ((L+R)/2)
Audio Data Output ch.0 (L/R)
I/O Power Supply +3.3V
-
I/O Power Supply GND
-
DSP Core Power Supply GND
-
DSP Core Power Supply +1.8V
VDD
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3k resistance
Ω
Ver.2008-12-03
- 4 -
NJU26207
ꢀ Audio Interface
The NJU26207 audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first
Right-justified. The NJU26207 audio interface provides four data inputs, SDI0, SDI1, SDI2 and SDI3, and three data
outputs, SDO0, SDO1 and SDO2 as shown in table 2 and 3. The input serial data is selected by the firmware
command.
Table 2 Serial Audio Input Pin
Pin No.
Symbol
SDI0
SDI1
SDI2
SDI3
Description
4
3
2
1
Audio Data Input 0 (L/R)
Audio Data Input 1 (L/R)
Audio Data Input 2 (L/R)
Audio Data Input 3 (L/R)
Table 3 Serial Audio Output Pin
Pin No.
40
Symbol
SDO0
SDO1
SDO2
Description
Audio Data Output 0 (L/R)
39
Audio Data Output 1 ((L/R)/2)
38
Audio Data Output 2 (Monitor L/R)
ꢀ Host Interface
The NJU26207 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or
4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a
SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data
transfers, regardless of the chosen communication protocol.
The detail I2C bus and 4-Wire Serial bus information are described in the ‘NJU26200 Series Hardware Data
Sheet’.
Table 4 Serial Host Interface Pin Descriptions
Pin No.
Symbol
Setting
Low
High
Host Interface
I2C Bus Interface
4-Wire Serial Interface
16
SEL
Table 5 Serial Host Interface Pin Description
Symbol
(I2C /Serial)
AD1/SDIN
AD2/SSb
SCL/SCK
Pin No.
I2C bus Interface
4-Wire Serial Interface
29
30
31
I2C Address Select Bit1
I2C Address Select Bit2
Serial Clock
Serial data input
Slave select
Serial Clock
Serial Data Input/Output
(Open Drain output)
Serial data output
(CMOS Output)
32
SDA/SDOUT
Note: When I2C Bus is selected, the SDA/SDOUT pin is a bi-directional Open Drain output. This pin, which is assigned
for I2C Bus, requires a pull-up resistance.
When 4-Wire Serial bus is selected, the SDA/SDOUT pin is CMOS output.
The SDA/SDOUT pin isn’t 5.0V Input tolerant.
Ver.2008-12-03
- 5 -
NJU26207
ꢀ I2C Bus
When the NJU26207 is configured for I2C bus communication in SEL=”Low”, the serial host interface transfers
data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance.
Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)
Table 6 I2C Bus Interface Slave address
AD2
bit2
0
AD1
bit1
0
R/W
bit0
bit7
0
bit6
0
bit5
1
bit4
1
bit3
1
R/W
0
0
1
1
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
Start
Bit
R/W
bit
ACK
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
* SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”.
Note:
Both “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” data transfer rate are supported.
ꢀ 4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the
Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the
same time that a read byte is shifted out of the SDOUT pin.
Data transfers are MSB first and are enabled by setting SSb = “Low”. Data is clocked into SDIN on rising
transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is
latched on the falling transitions of SSb. SDOUT is always CMOS output. SDOUT does not require a pull-up
resistance.
SSb
SCK
SDIN
bit7
MSB
bit7
bit1
bit1
bit6
bit6
bit5
bit5
bit0
LSB
bit0
unstable
unstable
SDOUT
Fig. 4 4-Wire Serial Interface Timing
Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
transition of SSb=”High”.
When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”.
Ver.2008-12-03
- 6 -
NJU26207
ꢀ Pin setting
The NJU26207 operates default command setting after resetting the NJU26207. In addition, the NJU26207
restricts operation at power on by setting PROC pin and MUTEb pin. These pins are input pin. However, these pins
operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3k resistance.
Ω
Table 7 Pin setting
Pin No. Symbol
Setting Function
“High”
“Low”
The NJU26207 operates default setting after reset.
The NJU26207 does not operate after reset. Sending start
command is required for starting operation.
Master volume is set 0dB after reset.
13
11
PROC
“High”
“Low”
MUTEb
Master volume is set mute after reset.
ꢀ WatchDog Clock
The NJU26207 outputs clock pulse through WDC (Pin No.12) during normal operation. The WDC clock is useful
to check the status of the NJU26207 operation. For example, a microcomputer monitors the WDC clock and checks
the status of the NJU26207. When the WDC clock pulse is lost or not normal clock cycle, the NJU26207 does not
operate correctly. Then reset the NJU26207 and set up the NJU26207 again. The WDC clock is able to be variable
for 0msec to 100msec by command. Default setting of WDC clock is 100msec.
The WDC pin is open drain output. The WDC pin setting (Table 8)
Table 8 WDC pin setting
Pin No. Symbol
Setting
WDC pin is used.
Connect with VDDIO through 3.3k
Ω
resistance.
resistance.
12
WDC
Connect with VSSIO through 3.3k
Ω
WDC pin is not used.
Do not open WDC pin.
Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing.
In slave mode, when there is no input of BCKI/LRI, WDC can’t output.
It is required to set up a sampling rate correctly.
Ver.2008-12-03
- 7 -
NJU26207
ꢀ
Firmware Command Table
Host processor can control the NJU26207 via I2C bus or 4-Wire serial bus interface. The following table
summarizes the available user commands.
Table 9 Command Table
No.
1
Command Description
Set Task Command
2
System State Command
3
Sample rate Select Command
Smooth Control Config Command
Master Volume Control Command
Master Volume Balance Control Command
Input Reference Level Command
Output Reference Level Command
Calibration Level Command
Digital Volume Level Command
Analog Volume Level Command
Reset Flag Command
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Input Select / Delay Command
Up data Command
Firmware Version Number Request Command
DSP Reset Command
Start Command
Nop Command
Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a
licenser (Dolby) is required.
ꢀ
Response of status
NJU26207 returns the response of 4 types to the host controller.
Table 10 Response of status
Response
Status : Command Accepted
Status : Command Error
Status : Command Process
Status : Not Ready
Command
0x80
Remark
Reception OK
Reception ERROR
Command processing
Initialization
0x81
0x82
0x83
Ver.2008-12-03
- 8 -
NJU26207
ꢀ
License Information
The Word “DOLBY”, “Dolby Volume” and the double D mark are trademarks of Dolby Laboratories.
The NJU26207 can only be delivered to licensees of Dolby Laboratories.
Please refer to the licensing application manual issued by Dolby Laboratories.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2008-12-03
- 9 -
相关型号：
©2020 ICPDF网 联系我们和版权申明