NJU3427F [NJRC]
Vacuum Fluorescent Driver, CMOS, QFP-52;
| 型号： | NJU3427F |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Vacuum Fluorescent Driver, CMOS, QFP-52 驱动 接口集成电路 |
| 文件： | 总19页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
NJU3427
36 Outputs VFD Controller/Driver
ꢀ GENERAL DESCRIPTION
ꢀ Package
The NJU3427 is a 36-output VFD (Vacuum Fluorescent
Display) controller/driver.
The NJU3427 consists of high-voltage driving circuit,
Timing/ Segment driver select circuit, display data RAM
(DDRAM), address counter, instruction register, reset circuit
serial interface and oscillator.
The direct control from the MPU and high voltage drivers
make the NJU3427 well suited for various VFD displays
NJU3427F
ꢀ FEATURES
ꢁ
Display Capability
DR0 Pin (ISO1
DR1~DR35 Pins (ISO2
From 20-Seg x16-Timing to 28-Seg x 4-Timing
20mA(VDD=5V)
10mA(VDD=5V)
)
)
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Segment and Timing Driver Configure 4 patterns
High VFD Driving Voltage
Programmable Display Duty Ratio
|VDD-VFDP|≤40V
1/4, 1/8, 1/12 or 1/16
Programmable Timing Signal Duty Ratio2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16
Display ON/OFF
Display Data RAM
CR Oscillator
Serial Data Transfer
Logic Power Supply
C-MOS
47x8 bits
External CR and capable of clock input from outside
Clock frequency: 2MHz Max.
3.0V / 5.0V
Package
QFP52
ꢀ BLOCK DIAGRAM
DR0
DR35
High Voltage Drivers
VDD
Timing/Segment Select
VSS
VFDP
Segment Data Latch
Timing Decoder
Duty
Counter
Address
Counter
Display RAM
Timing
Counter
Instruction Decoder
Serial Buffer
XT
XTb
OSC
SI
SCK
RSTb
Reset
CSb
Ver.2005-10-24
- 1 -
NJU3427
Preliminary
ꢀ PIN CONFIGURATION
VFDP
40
DR23
DR22
DR21
DR20
26
25
24
23
NC
41
VDD
NC
VSS
XT
42
43
44
45
22
21
DR19
DR18
XTb
NC
46
20
DR17
DR16
DR15
DR14
DR13
DR12
NJU3427F
47
48
19
18
SCK
SI
49
50
51
52
17
16
15
14
NC
CSb
RSTb
NC
ꢀ PIN DESCRIPTION
No.
42
Symbol
VDD
Function
Logic power supply
3.0V / 5.0V
GND
44
VSS
VSS=0V
40
VFDP
Power supply for VFD driving
2 ~ 13,
15 ~ 38
DR0~
DR35
Driving signal output
The configure of the Segment and Timing drivers is determined by the
instruction, refer to (2) Instruction Register.
52
51
RSTb
CSb
Reset
If RSTb=“L", reset occurs, but data on DDRAM not changing.
Chip select
If CSb=“L", data transmission is enabled.
Serial clock
48
49
SCK
SI
Serial data input (8-bit/one word)
45,
46
XT,
XTb
NC
Connecting external capacitor and resistor, or input clock via this pin
If using external clock, input clock signal via XT and keep XTb open.
No connect
1, 14, 39, 41,
43, 47, 50
Usually open.
Ver.2005-10-24
- 2 -
Preliminary
NJU3427
ꢀ FUNCTION DESCRIPTION
(1) Address Counter
The address counter specifies the RAM address, and the display data from CPU is written to the specified
address.
If the upper 2 bits (B7, B6) of the 1st word are “0,0”, the rest 6 bits (B5~B0) will be interpreted as RAM
address. The 2nd word will be interpreted as display data and saved on the RAM which address is specified by
the B5~B0 of the 1st data.
Once the RAM address is determined by the 1st data, the address counter will automatically increase (+1) for
every following word. So there is no need to specify the address for every word for a consecutive data transfer.
During display data writing, even there is unused or not-existing RAM area, be sure to input 8-bit serial data.
The data allocated to the above mentioned area is invalid.
The RAM address range varies with programmable duty ratios. For 1/4 duty, the address range is
from”00H~0FH”. For 1/8 duty, the range is from “00H~1FH”. For 1/12 duty, the range is from “00H~23H”.
For 1/16 duty, the range is from “00H~2FH”. When automatically increased address excess the address range
and display data is still transferred from CPU, the address counter will return to “00H” and count up again.
Address Data
B7
0
B6
0
B5
B4
B3
B2
B1
B0
AD5 AD4 AD3 AD2 AD1 AD0
Address flag
RAM address
Ver.2005-10-24
- 3 -
NJU3427
Preliminary
Ver.2005-10-24
- 4 -
Preliminary
NJU3427
Ver.2005-10-24
- 5 -
NJU3427
Preliminary
(2) Instruction Register 1
The Instruction Register 1 is used for setting duty ratio and driver (DR) pins configure. If B7 of the 1st word
is “1”, the rest 4 bits (B5, B4, B1, B0) is interpreted as instruction 1.
The value on register is initialized to the default by reset signal. But, during power on, the value of register 1
is unspecified, it is necessary to set value in register 1.
The contents of the “Instruction register 1” is initially set up by reset signal, as shown below. Because the
NJU3427 is unstable during power on, reset shall be executed.
Instruction Register 1 Default
Duty ratio
DR pins
1/16
pattern 1
B7
1
B6
*
B5
B4
B3
*
B2
*
B1
B0
DY1 DY0
DR1 DR0
Instruction flag
Duty ratio
DR pins configure
DY1
DY0
Duty Ratio
1/16
0
0
1
1
0
1
0
1
1/12
1/8
1/4
Note): For Segment and Timing pins configure, please refer to “The Relationship Between Duty Ratio and
Segment/Timing Pins”. When select 1/4 and 1/8 duty, configures of segment and timing pins are the same.
DR1
DR0
DR configure
Pattern 1
Pattern 2
Pattern 3
Pattern 4
0
0
1
1
0
1
0
1
Note): For Segment and Timing pins configure, please refer to “The relationship Between Duty Ratio and
Segment/Timing Pins”.
Ver.2005-10-24
- 6 -
Preliminary
NJU3427
The Relationship Between Duty Ratio and Segment (S)/Timing (T) Pins Configure
•
Pattern 1
NC S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
NC S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
NC S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
S12
S13
S14
S15
S16
S17
S18
S19
T15
T14
T13
T12
NC
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
NC
S12
S13
S14
S15
S16
S17
S18
Interface
Interface
1/16 duty
1/12 duty
1/8 or 1/4
Interface
S19
S20
S21
S22
S23
NC
NC T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
NC T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
NC T0 T1 T2 T3 T4 T5 T6 T7 S27 S26 S25 S24
•
Pattern 2
NC S0 S1 S2 T15 T14 S3 S4 T13 T12 S5 S6 S7
NC S0 S1 T11 S2 S3 T10 S4 S5 T9 S6 S7 T8
NC T7 S0 S1 S2 S3 T6 S4 S5 S6 S7 T5 S8
T11
T10
S8
S8
S9
S9
S10
T7
S11
T4
S9
S10
S11
T6
T9
S12
S13
S14
S15
T3
T8
S10
S11
S12
T7
S12
S13
T5
1/16 duty
1/12 duty
1/8 or 1/4
Interface
Interface
Interface
S14
S15
T4
S16
S17
S18
NC
T6
S13
NC
NC
NC T0 T1 S19 S18 T2 T3 S17 S16 S15 T4 T5 S14
NC T0 S23 S22 T1 S21 S20 T2 S19 S18 T3 S17 S 1 6
NC T0 S27 S26 S25 S24 T1 S23 S22 S21 S20 T2 S 1 9
•
Pattern 3
NC T15 S0 S1 T14 S2 S3 T13 S4 S5 T12 S6 S7
NC T11 S0 S1 T10 S2 S3 T9 S4 S5 T8 S6 S7
NC T7 S0 S1 T6 S2 S3 T5 S4 S5 T4 S6 S7
T11
T7
T3
S8
S8
S8
S9
S9
S9
T10
S10
S11
T9
T6
T2
S10
S11
T5
S10
S11
T1
1/16 duty
1/12 duty
1/8 or 1/4
Interface
Interface
Interface
S12
S13
T8
S12
S13
T4
S12
S13
S14
S15
S16
NC
S14
S15
NC
S14
S15
NC
NC T0 T1 T2 T3 T4 T5 S19 S18 T6 S17 S16 T7
NC T0 S23 S22 S21 S20 T1 S19 S18 T2 S17 S16 T 3
NC T0 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S 1 7
•
Pattern 4
NC T15 S0 S1 S2 S3 S4 S5 S6 S7 S8 T14 T13
NC T11 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
NC T7 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
T12
T11
T10
T9
S11
S12
T10
T9
S11
S12
S13
S14
S15
S16
T6
T8
T8
T7
T7
T6
T6
1/16 duty
1/12 duty
1/8 or 1/4
Interface
Interface
Interface
T5
T5
T5
T4
T4
T4
T3
T3
T3
T2
T2
T2
T1
T1
T1
NC
NC
NC
NC T0 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S 9
NC T0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S 1 3
NC T0 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S 1 7
Ver.2005-10-24
- 7 -
NJU3427
Preliminary
(3) Instruction Register 2
The Instruction Register 2 is used for setting Timing signal duty ratio and controlling display ON/OFF. If B7
and B6 of the 1st word are “0, 1”, the rest 4 bits (B4~B1) is interpreted as instruction 2.
When power on or reset signal input, the Register 2 is initialized as below: Because the NJU3427 is unstable
during power on, reset shall be executed.
Instruction Register 2 Default
Timing duty ratio
Display ON/OFF
2/16
OFF
B7
0
B6
1
B5
*
B4
B3
B2
B1
B0
*
DT2 DT1
DT0 DSP
Instruction flag Timing signal duty ratio
Display ON/OFF
DT2
0
0
DT1
0
0
DT0
0
1
Timing duty ratio
2/16
4/16
0
1
0
6/16
0
1
1
8/16
1
1
1
1
0
0
1
1
0
1
0
1
10/16
12/16
14/16
15/16
Note): For the output waveform, refer to “Timing Signal Duty Ratio”.
DSP
Display control
0
1
OFF
ON
Note): During display off, there is no signal from Timing pins and Segment pins.
Ver.2005-10-24
- 8 -
Preliminary
NJU3427
ꢁ
Timing Signal and Duty Ratio
frame time
13 14 15 0 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 0 1
2
3
4 5 6
(duty counter value)
DT2 DT1 DT0
2/16
4/16
6/16
0
0
0
0
0
1
0
1
0
8/16
0
1
1
0
1
0
Timing driver
(T0~T15)
10/16
12/16
14/16
15/16
1
1
1
0
1
1
1
0
1
Segment driver
Ver.2005-10-24
- 9 -
NJU3427
Preliminary
ꢁ Display Timing Charter
• Duty ratio 1/16
fCL
fCL
tBK
tDG
T0
T1
T2
T3
•
•
•
•
•
•
T15
tSP
S0~S19
External Clock Frequency
800kHz~2.5MHz
fCL
Minimum Blinking Time
(Timing Signal Duty Ratio = 15/16)
1-character display time
Frame time
40µs~12.8µs
tBK=(1/fCL) x 16 x 2
640µs ~204.8µs
10.24ms~3.2768ms
tDG=tBK x 16
tSP=tDG x 16
• Duty ratio 1/12
fCL
fCL
tBK
tDG
T0
T1
T2
T3
•
•
•
•
•
•
T11
tSP
S0~S23
External Clock Frequency
800kHz~2.5MHz
fCL
Minimum Blinking Time
(Timing Signal Duty Ratio = 15/16)
1-character display time
Frame time
55µs~17.6µs
tBK=(1/fCL) x 22 x 2
880µs ~281.6µs
10.56ms~3.3792ms
tDG=tBK x 16
tSP=tDG x 12
Ver.2005-10-24
- 10 -
Preliminary
NJU3427
• Duty Ratio 1/8
fCL
fCL
tBK
tDG
T0
T1
T2
T3
•
•
•
•
•
•
T7
tSP
S0~S27
External Clock Frequency
Minimum Blinking Time
(Timing Signal Duty Ratio = 15/16)
1-character display time
Frame time
800kHz~2.5MHz
80µs~25.6µs
(fCL)
tBK=(1/fCL) x 32 x 2
1.28ms~409.6µs
10.24ms~3.2768ms
tDG=tBK x 10
tSP=tDG x 8
• Duty ratio 1/4 (T4~T7 output pins)
fCL
fCL
tBK
tDG
T0
T1
T2
T3
•
•
•
•
•
•
T7
tSP
S0~S27
External Clock Frequency
Minimum Blanking Time
(Timing Signal Duty Ratio = 15/16)
1-character display time
Frame time
800kHz~2.5MHz
160µs~51.2µs
(fCL)
tBK=(1/fCL) x 64 x 2
2.56ms~819.2µs
10.24ms~3.2768ms
tDG=tBK x 16
tSP=tDG x 4
Ver.2005-10-24
- 11 -
NJU3427
Preliminary
(4) Serial Interface
8-bit per word serial data is transferred from CPU to NJU3427 with synchronous clock signal (SCK). At the
every rising edge of the SCK, data is taken in, and at the rising edge of CSb, the data of words are latched.
If the 1st data is address data when CSb becoming “L”, without changing CSb, the following data will be
interpreted as display data. If the 1st data is instruction, without changing CSb signal, all the following data is
invalid.
SCK
SI
D0
D1
D2
D3
D4
D5
D6
D7
Serial data transmission
CSb
SCK
SI
Nth word
1st word
2nd word
Serial data transmission format
•
Serial Data
1st word
Address data
B7
0
B6
0
B5
AD5
B4
AD4
B3
AD3
B2
AD2
B1
AD1
B0
AD0
Instruction 1
B7
1
B6
*
B5
DY1
B4
DY0
B3
*
B2
*
B1
DR1
B0
DR0
*:don’t care
*:don’t care
Instruction 2
B7
0
B6
1
B5
*
B4
DT2
B3
DT1
B2
DT0
B1
DSP
B0
*
From the 2nd word
If the 1st word is address data
If the 1st word is instruction data
display data
invalid data
Ver.2005-10-24
- 12 -
Preliminary
NJU3427
(5) Reset Circuit
If RSTb="L", reset circuit functions, and the following default is set up. Because the NJU3427 is unstable
during power on, reset shall be executed.
Address Data
(AD0, AD1, AD2, AD3, AD4, AD5): (0, 0, 0, 0, 0, 0)
Instruction Register 1
Duty ratio
1/16
DR pins configure
Pattern 1
Instruction Register 2
Timing signal duty ratio
Display ON/OFF
2/16
OFF
Ver.2005-10-24
- 13 -
NJU3427
Preliminary
ꢀ ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply
Input Voltage
VFD Driving Voltage
H Level Output Current 1
H Level Output Current 2
L Level Output Current
Operating Temperature
Storage Temperature
Power Dissipation
Symbol
VDD
VIN
VFDP
IOH1
IOH2
IOL
Topr
Tstg
PD
Rating
-0.3~+7.0
-0.3~VDD+0.3
VDD-45~VDD+0.3
-35
Unit
V
V
Conditions
V
VDD as reference voltage
DR0 output, signal pin
DR1 ~ DR35 output, signal pin
mA
mA
mA
°C
°C
-15
20
-40 ~ 85
-55 ~ 125
900
mW Glass epoxy board (76.2 x114.3x1.6mm)
Note 1): The IC must be used within the Absolute Maximum Ratings, otherwise, an electrical or physical stress may
cause a permanent damage to it.
Note 2): De-coupling capacitors should be placed between VDD-VSS and VFDP-VSS.
Note 3): The condition of VDD> VSS≥ VFDP and VSS=0 must be maintained.
Ver.2005-10-24
- 14 -
Preliminary
NJU3427
ꢀ ELECTRICAL CHARACTERISTICS
DC Characteristics 1
(VDD=5.0V, VSS=0V, Ta=-40 ~ 85°C)
Parameter
Power Supply (1)
Power Supply (2)
H Level Input Voltage
L Level Input Voltage
Symbol
VDD
VFDP
VIH
Conditions
MIN
4.5
-40
0.8VDD
-
TYP
MAX
5.5
VSS
Unit
V
V
VDD pin
-
-
-
-
VFDP pin and VDD as reference
XT, RSTb, CSb, SCK, SI pins
-
V
VIL
0.2VDD
CSb, SCK, SI pins
VDD=5.5V, VI=0 or 5.5V
Input off-leak current
IIZ
-
-
±1
µA
DR0 pin
DR1 ~ DR35 pin
RSTb pin, Ta=25°C, VI=VSS
DR0 ~ DR35 pins, Ta=25°C
VI=VDD, VFDP=VDD-40V
VDD=4.5V,VFDP=VDD-40 -11.5
-20
-10
-
-
-
mA
mA
kΩ
Display Current
IOH
V, VOH=VDD-2.25V
-5.5
100
Pull-up Resistance
Pull-down Resistance
RUR
RDST
300
75
-
-
195
kΩ
VSS pin
CR oscillation (R=6.8kΩ, C=100pF),
All Segment/Timing pins open, RSTb
open
Logic Circuit
Power Supply
ISS
0.6
0.8
mA
All Segment/Timing pins output display
OFF signal.
VFDP pin, VFDP=VDD-40V,
Operation Current
IFDP
fCR
-
12
16.5
1.21
mA
CR oscillation (R=6.8kΩ, C=100pF),
All driving pins output display ON signal
Ta=25°C
CR Oscillation Frequency
1.05
1.13
MHz
R=6.8kΩ, C=100pF
•
AC Characteristics 1
Parameter
(VDD=5.0V, VSS=0V, Ta=-40 ~ 85°C)
Symbol
fCL
tCLH, tCLL
tSIS
Conditions
Fig 1
Fig 1
Fig2
MIN
0.8
200
35
TYP
-
MAX
2.5
Unit
MHZ
ns
ns
ns
External Clock Frequency
Width of External Clock Pulse
Data Setup Time
Data Hold Time
tSIH
Fig2
35
Clock Frequency
Clock Pulse Width
External Clock
fSCK
tSCKH, tSCKL
Fig3
Fig3
2.0
MHZ
ns
200
Rising Time,
tCLH, tCLL
Fig2
250
ns
Falling Time
Clock Interval Time
Reset Pulse Width
tSCI
tRSTb
Fig3
Fig4
10
10
µs
µs
Ver.2005-10-24
- 15 -
NJU3427
Preliminary
•
DC Characteristics 2
Parameter
(VDD=3.0V, VSS=0V, Ta=-40 ~ 85°C)
Symbol
VDD
VFDP
VIH
Conditions
MIN
2.7
-40
0.8VDD
-
TYP
MAX
3.6
VSS
Unit
V
V
Power Supply (1)
Power Supply (2)
H Level Input Voltage
L Level Input Voltage
VDD pin
-
-
-
-
VFDP pin and VDD as reference
XT, RSTb, CSb, SCK, SI pins
-
V
VIL
0.2VDD
CSb, SCK, SI pins
VDD=3.6V, VI=0 or 3.6V
Input off-leak current
IIZ
-
-
±1
µA
DR0 pin
DR1 ~ DR35 pin
RSTb pin, Ta=25°C, VI=VSS
DR0 ~ DR35 pins, Ta=25°C
VI=VDD, VFDP=VDD-40V
VDD=2.7V,VFDP=VDD-40
V, VOH=VDD-1.35V
-5.0
-2.5
100
-9.0
-4.0
-
-
-
mA
mA
kΩ
Display Current
IOH
Pull-up Resistance
Pull-down Resistance
RUR
RDST
300
75
-
195
kΩ
VSS pin
CR oscillation (R=4.7kΩ, C=100pF),
All Segment/Timing pins open, RSTb
open
Logic Circuit
Power Supply
ISS
-
0.25
0.35
mA
All Segment/Timing pins output display
OFF signal.
VFDP pin, VFDP=VDD-40V,
Operation Current
IFDP
fCR
-
12
16.5
1.21
mA
CR oscillation (R=4.7kΩ, C=100pF),
All driving pins output display ON signal
Ta=25°C
CR Oscillation Frequency
1.05
1.13
MHz
R=4.7kΩ, C=100pF
•
AC Characteristics 2
Parameter
(VDD=3.0V, VSS=0V, Ta=-40 ~ 85°C)
Symbol
fCL
tCLH, tCLL
tSIS
Conditions
Fig 1
Fig 1
Fig2
MIN
0.8
200
35
TYP
-
MAX
2.5
Unit
MHZ
ns
ns
ns
External Clock Frequency
Width of External Clock Pulse
Data Setup Time
Data Hold Time
tSIH
Fig2
35
Clock Frequency
Clock Pulse Width
External Clock
fSCK
tSCKH, tSCKL
Fig3
Fig3
2.0
MHZ
ns
200
Rising Time,
tCLH, tCLL
Fig2
250
ns
Falling Time
Clock Interval Time
Reset Pulse Width
tSCI
tRSTb
Fig3
Fig4
10
10
µs
µs
Ver.2005-10-24
- 16 -
Preliminary
NJU3427
fCL
tCLH
tCLL
VIH
VIH
VIH
XT
VIL
VIL
Fig1
tCLL
tSCKL
tCLH
tSCKH
VIH
VIH
SCK
VIL
VIL
tSIS
tSIH
VIH
VIL
VIH
VIL
SI
Fig2
VIH
RSTb
CSb
VIL
VIH
VIL
VIH
VIL
VIH
SCK
VIL
VIL
tSCI
fSCK tSCI
tSCI
Fig3
tRSTb
RSTb
VIL
VIL
Fig4
Ver.2005-10-24
- 17 -
NJU3427
Preliminary
ꢀ APPLICATION CIRCUIT (CR OSCILLATION)
C0
VFDP
VFDP
DR23
DR22
DR21
VDD
N.C.
VDD
N.C
VSS
DR20
DR19
DR18
DR17
C0
XT
R
C
XTb
N.C.
NJU3427F
DR16
DR15
DR14
DR13
DR12
N.C.
SCK
SI
CPU
N.C.
CSb
RSTb
VFD
* Pay careful attention to reduce the noise from power supply and interface pins.
Ver.2005-10-24
- 18 -
Preliminary
NJU3427
ꢀ QFP52 PACKAGE
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2005-10-24
- 19 -
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