NJU6417CFG1 [NJRC]
Liquid Crystal Driver, 64-Segment, CMOS, PQFP80, QFP-80;
| 型号： | NJU6417CFG1 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 64-Segment, CMOS, PQFP80, QFP-80 驱动 接口集成电路 |
| 文件： | 总10页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6417C
ꢀ PIN CONFIGURATION
41
40
64
65
SEG61
SEG62
SEG63
SEG64
V5
SEG36
SEG35
SEG34
SEG33
LM
V2
V3
LP
SCL
VSS
VDD
IOA1
IOB1
NC
NJU6417CFC1
IOB2
SHL1
SHL2
SEG32
SEG31
SEG30
SEG29
NC
IOA2
SEG1
SEG2
SEG3
SEG4
80
1
25
24
60
61
41
40
SEG39
SEG60
SEG61
SEG62
SEG63
SEG64
V5
V2
V3
VSS
VDD
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
LM
LP
SCL
IOA1
IOB1
NC
NJU6417CFG1
IOB2
SHL1
SHL2
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
NC
IOA2
SEG1
SEG2
SEG3
SEG4
SEG5
21
20
80
1
NJU6417C
ꢀ TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
LCD segment driving terminal.
FC1
FG1
1 28
37 68 34 65
77 80 74 80
1 25
Each terminal corresponds to each bit of shift register.
SEG1 SEG64
Data input/output terminals for 1st to 32nd bits shift register.
Display data is input (output) synchronized with clock pulse.
Input or output is selected by SHL1 terminal.
29
33
26
30
IOA2
IOA1
Data input/output terminals for 33rd to 64th bits shift register.
Display data is input (output) synchronized with clock pulse.
Input or output is selected by SHL2 terminal.
32
74
29
71
IOB1
IOB2
Shift register clock pulse input terminal.
The data is shifted in the shift register by the falling edge of the
clock pulse. A data setup time and hold time are required
between data input and SCL. Clock pulse rising time (TRS) and
falling time (TFS) should be set less than 50ns respectively.
Latch pulse input terminal.
The data in the shift register is latched to the latch by this signal.
“H” : Data writing, “L” : Data latch
Alternate signal input for LCD driving.
34
31
SCL
LP
35
36
32
33
LM
LCD driving power source terminals.
69,70, 66,67,
V5, V2, V3
VDD ≥ V2 ≥ V3 ≥ V5, VDD ≥ VSS ≥ V5
71
68
72
73
69
70
VSS
VDD
Power supply terminal (connect to the controller’s VSS terminal)
Power supply terminal (connect to the controller’s VDD terminal)
Shift direction and input/output control terminal (Pull-up R)
“H” or Open : Shift direction is from 1st bit to 32nd bit.
75
72
SHL1
“L”
: Shift direction is from 32nd bit to 1st bit.
Shift direction and input/output control terminal (Pull-up R)
76
73
SHL2
NC
“H” or Open : Shift direction is from 33rd bit to 64th bit.
“L”
Non connection.
: Shift direction is from 64th bit to 33rd bit.
30,31
27,28
NJU6417C
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
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