NJU6533FA2 [NJRC]
Liquid Crystal Driver, 36-Segment, CMOS, PQFP52, QFP-52;
| 型号： | NJU6533FA2 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 36-Segment, CMOS, PQFP52, QFP-52 驱动 接口集成电路 |
| 文件： | 总20页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6533
1/3, 1/4 Duty LCD Driver
ꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
NJU6533 is a 1/3 or 1/4 duty segment type LCD driver.
It incorporates 4 common driver circuits and 32 segment driver
circuits. NJU6533 can drive maximum 96 segments in 1/3
duty ratio and maximum 128 segments in 1/4 duty ratio.
Be addition, the NJU6533's useful functions and small
package meet a wide range of applications.
NJU6533C
NJU6533KQ1
NJU6533FA2
NJU6533FH2
NJU6533FR3
ꢀ FEATURES
ꢁ
ꢁ
LCD driving circuit
Programmable Duty Ratio
1/3 duty ratio
:Max. 32outputs (4 outputs as for general purpose ports)
:Driving max. 96 segments
:Driving max. 128 segments
1/4 duty ratio
ꢁ
ꢁ
ꢁ
Programmable Bias Ratio :1/2, 1/3 bias ratio
Serial Data Transfer
:Shift clock max. 2MHz
Built-in Oscillator
:CR oscillation with external resistor, or external oscillation signal input
ꢁ Display OFF
:INHb terminal
:3V / 5.0V
:P-Sub
ꢁ
ꢁ
ꢁ
Operating Voltage
C-MOS Technology
Package Outline
:Bare Chip, QFN48-Q1, QFP52-A2, LQFP52-H2, LQFP48-R3
ꢀ BLOCK DIAGRAM
COM1
COM4 SEG1
SEG8 SEG9
SEG16 SEG17
SEG24 SEG25
SEG32/P4
VDD
COM
Drivers
VLCD
Segment Drivers /General Purpose Output Ports
V1
V2
VSS
INHb
Data Latch Circuit
OSC1
OSC2
Oscillator
Display Data Register
CSb
SCK
SI
Decoder
Command Register
Power ON Reset Circuit
RSTb
Ver.2011-09-17
- 1 -
NJU6533
ꢀ PAD LOCATION
36
35
32 31
30 29 28 27 26 25
34 33
24
23
37
38
22
21
20
39
40
41
TOP VIEW
19
42
18
17
16
15
14
13
43
44
45
46
47
48
Chip Center
Chip Size
Chip Thickness
PAD Size
PAD Pitch
Sub Striate
: X=0µm, Y=0µm
: X= 2.60 mm, Y= 2.36 mm
: 625µm ± 25 µm
: 90.0 µm x 90.0 µm
: 126µm
: P
1
2
3 4
5
6
7
8
9 10 11
12
ꢀ PAD COORDINATES
Chip Size 2.60 x 2.36 mm(Chip Center X=0µm, Y=0µm)
PAD No. PAD NAME
PAD No. PAD NAME
X= µm
-686
-560
-434
-308
-182
-56
70
196
322
448
Y= µm
-1019
-1019
-1019
-1019
-1019
-1019
-1019
-1019
-1019
-1019
-1019
-1019
-739
-613
-487
-361
-235
-109
17
143
269
X= µm
784
658
532
406
280
154
28
-98
-356
-482
-837
-963
-1138
-1138
-1138
-1138
-1138
-1138
-1138
-1138
-1138
-1138
-1138
-1138
Y= µm
1019
1019
1019
1019
1019
1019
1019
1019
1019
1019
1019
1019
914
1
2
3
4
5
COM1
COM2
COM3
COM4
SEG1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29/P1
SEG30/P2
SEG31/P3
SEG32/P4
VLCD
6
SEG2
7
SEG3
8
SEG4
9
SEG5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SEG6
SEG7
SEG8
SEG9
574
700
1138
1138
1138
1138
1138
1138
1138
1138
1138
1138
1138
1138
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
V1
V2
VSS
INHb
RSTb
CSb
SI
SCK
790
557
432
236
112
-121
-245
-479
-603
-845
-971
395
521
647
VDD
OSC1
OSC2
Ver.2011-09-17
- 2 -
NJU6533
ꢀ PIN CONFIGURATION
• QFN48-Q1 / LQFP48-R3
• QFP52-A2 / LQFP52-H2
VLCD
37
38
39
40
24
23
22
21
SEG20 VLCD
N.C.
26
25
24
23
40
41
V1
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
V1
SEG20
SEG19
SEG18
V2
V2
42
43
VSS
VSS
INHb
RSTb
CSb
SI
41
42
43
44
20
19
18
17
INHb
RSTb
CSb
SI
44
45
22
21
SEG17
SEG16
NJU6533KQ1
NJU6533FR3
NJU6533FA2
NJU6533FH2
46
20
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
45
46
16
15
SCK
VDD
47
48
19
18
SCK
VDD
OSC1
OSC2
47
48
14
13
49
50
51
52
17
16
15
14
OSC1
OSC2
N.C.
SEG9
Ver.2011-09-17
- 3 -
NJU6533
ꢀ
TERMINAL DISCRIPTION
No.
Pad Name
Function
QFN48-Q1 QFP52-A2
LQFP48-R3 LQFP52-H2
Bare Chip
46
37
46
49
VDD
ꢁ Power supply: 3V /5V
LCD driving voltage
VLCD ≥ V1 ≥ V2 ≥ VSS, VLCD ≥VDD
Bias
At 1/3 bias ratio, keep V1- V2 open.
At 1/2 bias ratio, short V1- V2.
GND
37
40
VLCD
38,
39
38,
39
41,
42
V1,
V2
40
40
43
VSS
V
SS =0V
Display OFF *
When INHb is "H", display is ON, and when INHb is "L",
display is off.
41
41
44
INHb
When SEG29(P1)~SEG32 (P4) are selected as general
purpose output ports, even if input “0” to INHb terminal,
SEG29~32 will still be recognized as general purpose
output ports.
Reset
42
43
42
43
45
46
RSTb
CSb
When RSTb is “L", command register and latch circuit is
reset.
Chip select
When CSb is "L", data can be read in.
Serial data input (8 bit=1word)
Serial clock
44
45
44
45
47
48
SI
SCK
External resistor connection terminal for CR oscillation, or
external clock input terminal
47,
48
47,
48
50,
51
OSC1,
OSC2
When external clock is used, input the signal to OSC1 and
keep OSC2 open.
COM1 ~
COM4
Common driver outputs
1~4
1~4
1~4
Segment driver outputs
5~12,
14~25,
27~34
SEG1 ~
SEG28
5~32
5~32
Segment driver outputs/general purpose output ports
These 4 terminals can be used as segment outputs or
general purpose output ports by setting Command
Register.
SEG29/P1~
SEG32/P4
33~36
33~36
35~39
When selected as general purpose ports, data can be
outputted via these ports during COM1 timing.
According to transferred data, "H"=VDD or "L"=VSS will
be outputted.
Non Connection
13,26,
39,52
-
-
NC
These pins must be open.
*: For details about INHb, please refer to "ꢀFUNCTION DESCRIPTION (5) Display OFF function (INHb terminal)".
Ver.2011-09-17
- 4 -
NJU6533
ꢀ FUNCTION DESCRIPTION
(1) Block Function
• Oscillator
The oscillator includes a built-in capacitor and an external resistor. It generates clock signal for LCD driving. When
use external clock, input the clock signal to OSC1 and keep OSC2 open.
• Decoder
Input serial data is decoded and sent to the appropriate block.
• Command Register
Command data is written to this 8 bits command register to control NJU6533 operation.
• Display Data Register
Data is written to this 8 bits register as display data.
• Latch Circuit
Data stored in display data register is assigned to the corresponding SEG/port.
• Segment Driver/General Purpose Ports
Basing on display data, segment drivers output LCD SEG driving signal.
And, SEG29/P1 ~ SEG32/P4 terminals can be selected as segment driver output or general-purpose ports by instruction.
• Common Driver
Common drivers output LCD COM driving signal.
• Power On Reset
When power is on, NJU6533 is automatically initialized. And if RSTb=”L”, NJU6533 is reset too.
Ver.2011-09-17
- 5 -
NJU6533
(2) Serial Data Transfer
The transfer of an 8-bit/word serial data is conducted by synchronizing clock via interface with CPU. During CSb=”L”,
serial data is obtainable and will be read in at the rising edge of SCK signal.
After CSb becoming low, if the first word is address data, the after data can be transferred continually and interrupted as
display data even if CSb maintained low. In this case, every 8 bits data will be confirmed as a word either by the falling
edge of the8th SCK clock or by the rising edge of the CSb clock.
After CSb becoming low, if the first word is command data, the after data is invalid even though transfer can be
continued without changing the polarity of CSb.
At the falling edge of CSb, SCK can be either “H” or “L”, but, at the rising edge of CSb, SCK must be low.
At this falling edge, one word is confirmed
• SCK and SI
SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
Timing of Serial Data Transfer
At this rising edge of CSb, when
SCK=”Lo”, one word is confirmed.
CSb
SCK
SI
WORD n
WORD 1
WORD2
Serial Interface Format
Ver.2011-09-17
- 6 -
NJU6533
(3) Command Register
Command Register is used to set the duty ratio, the bias ratio, and the SEG driver/general purpose ports. When the D7
to D5 bits of the 1st word are (1,0,0), the D4 ~ D0 bits are recognized as command data.
The contents of Command Register will be initialized as following when applying Power On Reset or Reset.
The Default Value of Command Register
• Duty ratio
• Bias ratio
: 1/4
: 1/3
• SEG driver/General purpose ports : SEG drivers(SEG29, SEG30, SEG31, SEG32)
D7
1
D6
0
D5
0
D4
DS
D3
BS
D2
D1
D0
TSEL2
TSEL1
TSEL0
Flag bits
Duty ratio Bias ratio
SEG driver or general purpose ports
• Duty Ratio
DS
0
Duty ratio
1/4
1
1/3
*) Do not change the duty ratio during display ON.
• Bias ratio
BS
0
Bias ratio
1/3
1
1/2
• SEG driver or general purpose ports
TSEL2 TSEL1 TSEL0 SEG29/P1 SEG30/P2 SEG31/P3 SEG32/P4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
SEG29
SEG29
SEG29
SEG29
P1
SEG30
SEG30
SEG30
P2
SEG31
SEG31
P3
SEG32
P4
P4
P4
P4
P3
P3
P2
**) If TSEL2 ~ TSEL0 is set to (1, 0, 1), (1, 1, 0), (1, 1, 1) all outputs are used as segment drivers.
Ver.2011-09-17
- 7 -
NJU6533
(4) Output Address Counter
Output Address Counter will specify the addresses of the SEG and COM drivers for the display data.
When the MSB (D7 to D4) of the 1st data is “0111”, the LSB 4 bits (D3 to D0) specify the addresses of COM and SEG
drivers, and the 2nd data is the display data which will be sent to the 1st-data-specified drivers. At the same time, SEG
and COM driver addresses will be increased automatically in turn as shown in Table 1. In other words, as of the SEG
and COM driver addresses specified by the first data in the Output Address Counter, display data can be transferred to
the SEG and COM drivers without further address setting.
The address setting range is from "0000" to "1111", if transfer data outnumber the address number which are from D3 ~
D0 to “1111”, the SEG and COM driver address will be reset to “0000” and renew the auto-increment operation.
• Address Data
D7
D6
1
D5
1
D4
1
D3
C1
D2
C0
D1
S1
D0
S0
0
Flag bits
COM driver Address
SEG driver Address
Table 1. The Relationship Between Output Address and SEG/COM Drivers
COM
Driver
SEG Driver
C1 C0 S1 S0
D7
SEG1
D6
SEG2
D5
SEG3
D4
SEG4
D3
SEG5
D2
SEG6
D1
SEG7
D0
SEG8
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
COM1
COM2
COM3
COM4
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
ꢀ
ꢀ
ꢀ
If general purpose ports are selected by Command Register, under (C1, C0, S1, S0)=(0, 0, 1, 1), D3 ~ D0 bits
are the addresses of (P1, P2, P3, P4) ports which corresponds to (SEG29, SEG30, SEG31, SEG32).
When SEG29~SEG32 are set as general purpose output ports, data for SEG29~SEG32 during COM2~COM4
scanning will be ignored.
When duty ratio is 1/3, do not set address between"1100"~"1111".
Otherwise, unexpected address way be setup.
Ver.2011-09-17
- 8 -
NJU6533
(5) Display OFF Function (INHb)
When INHb="L"
• All segment and common terminal output VSS
(When general purpose output ports are selected, even INHb="L", these ports can output data)
• Suspending Oscillation (but, if RSTb="L", oscillator works)
• V1 and V2 beome “H” (no current pass through the bleeder resistors)
Even during INHb=”L”, interface can be accessed, and data can be written into the command register, address counter
and data register.
(6) Power ON Reset
After power ON, NJU6533 is initialized to the following values:
• Address counter
• Display Data Register
• Duty ratio
(C1, C0, S1, S0)=(0, 0, 0, 0)
all "0"
1/4duty
1/3 bias
• Bias ratio
• Segment/General purpose port:
Segment output(SEG29, SEG30, SEG31, SEG32)
Ver.2011-09-17
- 9 -
NJU6533
(7) Sequence of Initialization
(7-1) 1/3duty, SEG32 used as general purpose port, data written in from COM2.
Power on
Set INHb to "L"
Pixels off
D7 D6 D5 D4 D3 D2 D1 D0
Set Command Register
1
0
0
1
0
0
0
1
Duty ratio=1/3, SEG32 as
general purpose port
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
0
1
0
0
COM driver address=01
SEG driver address=00
Set output address
Display data written in
Display data writing
Pixels on
After the address is set, the
display data should be written
in the state of CS="L".
The address setting is reset by
CS="H".
Set INHb to "H"
(7-2) 1/4duty, SEG29 ~ 32 used as SEG drivers, data written in from COM1.
Power on
Set INHb to "L"
Pixels off
D7 D6 D5 D4 D3 D2 D1 D0
Set Command Register
1
0
0
0
0
0
0
0
Duty ratio =1/4
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
1
0
0
0
0
COM driver address =00
SEG driver address=00
Set output address
Display data written in
Display data writing
Pixels on
After the address is set, the
display data should be written
in the state of CS="L".
The address setting is reset by
CS="H".
Set INHb to "H"
Ver.2011-09-17
- 10 -
NJU6533
ꢀ ABSOLUTE MAXIMAM RATINGS
(VSS=0V, Ta=25°C)
CONDITIONS
PARAMETER
Supply Voltage 1
Supply Voltage 2
Supply Voltage 3
Input Voltage
SYMBOL
VDD
VLCD
V1, V2
VIN
RATINGS
-0.3 ~ +6.0
-0.3 ~ +6.0
-0.3 ~ VLCD+0.3
-0.3 ~ VDD+0.3
-40 ~ +85
UNIT
V
V
V
V
°C
°C
INHb, CSb, SCK, SI, RSTb, OSC1 applicable.
Operating Temp.
Storage Temp.
Topr
Tstg
-55 ~ +125
The power dissipation is value mounted on a glass
epoxy board in size:
50mm x50mm x1.6mm(QFN48-Q1),
76.2mm x114.3mm x1.6mm
710(QFN48-Q1)
900(QFP52-A2)
890(LQFP52-H2)
1000(LQFP48-R3)
Dissipation Power
PD
mW
(QFP52-A2, LQFP52-H2, LQFP48-R3).
Note-1)
Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is
also recommended that the IC be used within the range specified in the DC electrical characteristics, or the
electrical stress may cause mulfunctions and impact on the reliability.
Note-2)
Note-3)
All voltages are relative to VSS = 0V reference.
The following relationship shall be maintained.
VLCD ≥ V1 ≥ V2 ≥ VSS, VLCD ≥VDD, and VLCD shall be input after VDD
.
Note-4)
To stabilize the LSI operation, place decoupling capacitors between VDD-VSS and between VLCD-VSS.
Ver.2011-09-17
- 11 -
NJU6533
ꢀ ELECTRICAL CHARACTERISTICS
• DC characteristics 1
(VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to 85°C)
SYM
PARAMETER
BOL
CONDITIONS
MIN
TYP
MAX
UNIT Note
Power Supply
VDD
2.4
2.4
3.6
5.5
V
V
LCD Driving Voltage
VLCD
VLCD ≥VDD
Ta=25°C
Testing via COM/SEG terminals
COM/SEG without load
V1
V2
2/3 VLCD-0.2 2/3 VLCD 2/3 VLCD+0.2
1/3 VLCD-0.2 1/3 VLCD 1/3 VLCD+0.2
V
V
LCD Bias Voltage
"H" Level Input
Voltage
"L" Level Input
Voltage
Hysteresis Voltage
"H" Level Input
Current
"L" Level Input
Current
"H" Level Output
Voltage
"L" Level Output
Voltage
Driver-on Resistance
(COM)
Driver-on Resistance
(SEG)
INHb, CSb, SCK, SI, RESb, OSC1
VIH
0.8 VDD
0
VDD
V
INHb, CSb, SCK, SI, RESb, OSC1
VIL
VH
IIH
0.2 VDD
V
V
INHb, CSb, SCK, SI, RESb
VIN= VDD
INHb, CSb, SCK, SI, RESb
VIN= VSS
INHb, CSb, SCK, SI, RESb
VDD =3V, IO=5mA, P1 to P4
0.2VDD
1.0
1.0
µA
IIL
µA
V
VOH
VOL
RCOM
RSEG
VDD-0.6
VDD =3V, IO=5mA, P1 to P4
±Id=1µA, VLCD=3V/5.5V
±Id=1µA, VLCD=3V/5.5V
0.6
10
V
-
-
kΩ
5
5
-
-
10
kΩ
kHz
kHz
Oscillating Frequency fOSC
External Clock
Frequency
12.6
12.6
15.4
15.4
18.2
18.2
VDD =3V, ROSC=750kΩ, Ta=25°C
Input into OSC1
fCP
External Clock Duty
Bleeder Resistor
duty
RB
Input into OSC1
45
127
50
150
55
173
%
kΩ
V
LCD-VSS Ta=25°C
VDD =3V, INHb="L", RSTb="H",
Ta=25°C
VDD =3V, VLCD=5V, Ta=25°C,
Checker flag display, 1/3 bias
Using internal oscillator, no output
VDD=3V, VLCD=5V, RSTb="H",
INHb="L", Ta=25°C
VDD =3V, VLCD=5V, Ta=25°C,
Checker flag display, 1/3 bias
Using internal oscillator, no output
IDD1
1.7
7.0
0.1
34
8.0
µA
µA
µA
µA
IDD2
25
Operating Current
ILCD1
1.0
60
ILCD2
Note-5) Driver-On resistance (RSEG/RCOM) is measured from VLCD, VSS, V1 or V2 terminal to each SEG/COM terminal when Id
current flows through COM/SEG terminals.
Note-6) ["H" Level Input Voltage], ["L" Level Input Voltage], [Hysteresis Voltage], ["H" Level Input Current], ["L" Level
Input Current], [External Clock Frequency] and [External Clock Duty] are as the same as if VDD=4.5 to 5.5V.
Ver.2011-09-17
- 12 -
NJU6533
• DC characteristics 2
(VDD=4.5 to 5.5V, VSS=0V, Ta=-40 to 85°C)
SYM
BOL
VDD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT Note
Power Supply
LCD Driving Voltage
4.5
4.5
5.5
5.5
V
V
VLCD
VLCD ≥VDD
Ta=25°C
Testing via COM/SEG terminals
COM/SEG without load
V1
V2
2/3 VLCD-0.2 2/3 VLCD 2/3 VLCD+0.2
1/3 VLCD-0.2 1/3 VLCD 2/3 VLCD+0.2
V
V
LCD Bias Voltage
"H" Level Input
Voltage
"L" Level Input
Voltage
Hysteresis Voltage
"H" Level Input
Current
"L" Level Input
Current
"H" Level Output
Voltage
"L" Level Output
Voltage
Driver-on Resistance
(COM)
Driver-on Resistance
(SEG)
INHb, CSb, SCK, SI, RESb, OSC1
VIH
0.8VDD
0
VDD
V
INHb, CSb, SCK, SI, RESb, OSC1
VIL
VH
IIH
0.2 VDD
V
V
INHb, CSb, SCK, SI, RESb
VIN= VDD
INHb, CSb, SCK, SI, RESb
VIN= VSS
INHb, CSb, SCK, SI, RESb
VDD =5V, IO=5mA, P1 to P4
0.2VDD
1.0
1.0
µA
IIL
µA
V
VOH
VOL
RCOM
RSEG
VDD-1.0
VDD =5V, IO=5mA, P1 to P4
±Id=1µA, VLCD=3V/5.5V
±Id=1µA, VLCD=3V/5.5V
1.0
10
V
-
-
kΩ
7
7
-
-
10
kΩ
kHz
kHz
Oscillating Frequency fOSC
External Clock
Frequency
12.6
12.6
15.4
15.4
18.2
18.2
VDD =5V, ROSC=750kΩ, Ta=25°C
Input into OSC1
fCP
External Clock Duty
Bleeder Resistor
duty
RB
Input into OSC1
45
127
50
150
55
173
%
kΩ
V
LCD-VSS Ta=25°C
VDD =5V, INHb="L", RSTb="H",
Ta=25°C
VDD =5V, VLCD=5V, Ta=25°C,
Checker flag display, 1/3 bias
Using internal oscillator, no output
VDD =5V, VLCD=5V, INHb="L",
RSTb="H",Ta=25°C
VDD =5V, VLCD=5V, Ta=25°C,
Checker flag display, 1/3 bias
Using internal oscillator, no output
IDD1
3.2
15
10
35
1.0
60
µA
µA
µA
µA
IDD2
Operating Current
ILCD1
0.1
34
ILCD2
Note-7) Driver-On resistance (RSEG/RCOM) is measured from VLCD, VSS, V1 or V2 terminal to each SEG/COM terminal when Id
current flows through COM/SEG terminals.
Note-8) ["H" Level Input Voltage], ["L" Level Input Voltage], [Hysteresis Voltage], ["H" Level Input Current], ["L" Level
Input Current], [External Clock Frequency] and [External Clock Duty] are as the same as if VDD=2.4 to 3.6V.
Ver.2011-09-17
- 13 -
NJU6533
• AC characteristics
(VDD=VLCD=2.4 to 5.5V, VSS=0V, Ta=-40 to 85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT Note
"L" Level Clock Pulse Width
"H" Level Clock Pulse Width
Data Setup Time
Data Hold Time
CSb Wait Time
CSb Setup Time
CSb Hold Time
CSb"H" Level Pulse Width
Rising Time
Falling Time
tWCLL
tWCLH
tDS
tDH
tCP
230
230
20
20
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
tCS
tCH
tWCH
tr
20
20
tf
Note-9) tCP is the time when SCK is kept at “H” during CSb changed from “H” to “L”.
• Input Timing
tWCH
CSb
tCH
tCP tCS
tWCLH tWCLL
tf
tr
VIL
VIL
SCK
SI
tDS tDH
• Input condition when hardware reset circuit is used
(Ta=25°C)
PARAMETER
SYMBOL CONDITIONS
MIN
1.5
TYP
MAX
UNIT
ms
ns
Reset Input “L” Level Width
Reset Rising Time
Reset Falling Time
tRSL
trRS
tfRS
fOSC= 15.4kHz
100
100
ns
trRS
tfRS
tRSL
VIH
RSTb
VIL
• Power supply condition when hardware reset circuit is used
(Ta=-40 to 85°C)
PARAMETER
Power-on Rising Time
Power-off Time
SYMBOL
trDD
CONDITIONS
MIN
0.1
1
TYP
MAX
5
UNIT
ms
ms
tOFF
2.2V
0.2V
0.2V
VDD
trDD
tOFF
Note 10) tOFF is the off time when power-supply turns off suddenly or cycles on/off.
Ver.2011-09-17
- 14 -
NJU6533
ꢀ EXAMPLE of SERIAL DATA TRANSFER
Ver.2011-09-17
- 15 -
NJU6533
ꢀ LCD DRIVING WAVEFORM
fOSC/192 (Hz)
(a) 1/3 duty, 1/2 bias
VLCD
V1,V2
COM1
COM2
VSS
VLCD
V1,V2
VSS
VLCD
V1,V2
COM3
COM4
VSS
VLCD
V1,V2
VSS
VLCD
V1,V2
"OFF" segment output correspond to
VSS
COM1, 2 and 3.
VLCD
V1,V2
"ON" segment output correspond to
COM1.
VSS
VLCD
V1,V2
"ON" segment output correspond to
COM2.
VSS
VLCD
V1,V2
"ON" segment output correspond to
COM1 and COM2.
VSS
VLCD
V1,V2
"ON" segment output correspond to
COM3.
VSS
VLCD
V1,V2
"ON" segment output correspond to
COM1 and COM3.
VSS
VLCD
V1,V2
"ON" segment output correspond to
COM2 and COM3.
VSS
VLCD
V1,V2
"ON" segment output correspond to
COM1, 2 and COM3.
VSS
1/3 duty, 1/2 bias
Ver.2011-09-17
- 16 -
NJU6533
(b) 1/3 duty, 1/3 bias
COM1
fOSC/192 (Hz)
VLCD
V1
V2
VSS
VLCD
V1
COM2
V2
VSS
VLCD
V1
COM3
COM4
V2
VSS
VLCD
V1
V2
VSS
VLCD
V1
"OFF" segment output correspond to
COM1, 2 and 3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM2.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1 and COM2.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1 and COM3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM2 and COM3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1, 2 and COM3.
V2
VSS
1/3 duty, 1/3 bias
Ver.2011-09-17
- 17 -
NJU6533
fOSC/192 (Hz)
(c) 1/4 duty, 1/2 bias
VLCD
V1,V2
VSS
COM1
COM2
COM3
COM4
VLCD
V1,V2
VSS
VLCD
V1,V2
VSS
VLCD
V1,V2
VSS
VLCD
V1,V2
VSS
"OFF" segment output correspond to COM1,
2, 3 and 4.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM1.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM2.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM1 and 2.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM3.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM1 and 3.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM2 and 3.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM1, 2 and 3.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM4.
VLCD
V1,V2
VSS
"ON" segment output correspond to
COM2 and 4.
VLCD
V1,V2
"ON" segment output correspond to COM1,
2, 3 and 4.
VSS
1/4 duty, 1/2 bias
Ver.2011-09-17
- 18 -
NJU6533
fOSC/192 (Hz)
(d) 1/4 duty, 1/3 bias
COM1
VLCD
V1
V2
VSS
VLCD
V1
COM2
COM3
COM4
V2
VSS
VLCD
V1
V2
VSS
VLCD
V1
V2
VSS
VLCD
V1
"OFF" segment output correspond to
COM1, 2, 3 and 4.
V2
VSS
VLCD
V1
"ON" segment output correspond
to COM1.
V2
VSS
VLCD
V1
"ON" segment output correspond
to COM2.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1 and 2.
V2
VSS
VLCD
V1
"ON" segment output correspond
to COM3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1 and 3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM2 and 3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1, 2 and 3.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM4.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM2 and 4.
V2
VSS
VLCD
V1
"ON" segment output correspond to
COM1, 2, 3 and 4.
V2
VSS
1/4 duty, 1/3 bias
Ver.2011-09-17
- 19 -
NJU6533
ꢀ APPLICATION CIRCUIT
• 1/4 duty, 1/3 bias
VLCD
VDD
VLCD
VDD
VSS
SEG1
+
+
*Typical Capacitance:1µF
SEG32/P4
V1
V2
NJU6533
RSTb
COM1
COM2
COM3
COM4
INHb
CSb
SCK
SI
From MPU
LCD Panel
OSC1
OSC2
• 1/4 duty, 1/2 bias
VLCD
VLCD
VDD
VSS
SEG1
VDD
+
+
*Typical Capacitance:1µF
SEG32/P4
V1
V2
NJU6533
RSTb
COM1
COM2
COM3
COM4
INHb
CSb
SCK
SI
From MPU
LCD Panel
OSC1
OSC2
Note)
Because display data is not yet stable just after VDD on, if LCD panel is turned on, unexpected pattern will be
displayed, therefore, keep INHb terminal to “L” level until data transfer from MPU is over.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2011-09-17
- 20 -
相关型号：
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