NJU6679BCH_技术文档

NJU6679

PRELIMINARY

128-common x 132-segment

BIT MAP LCD DRIVER

GENERAL DESCRIPTION

PACKAGE OUTLINE

The NJU6679 is a 128-common x 132-segment bit map LCD driver to

display graphics or characters.

It contains 25,344 bits display data RAM, microprocessor interface cir-

cuits, instruction decoder, and common and segment drivers.

An image data from CPU through the serial or 8-bit parallel interface are

stored into the 25,344 bits internal display data RAM and are displayed

on the LCD panel through the commons and segments drivers.

The NJU6679 displays 128 x 132 dots graphics or 8-character 8-line by

16 x 16 dots character.

NJU6679CJ

The NJU6679 contains a built-in OSC circuit for reducing external com-

ponents. And it features Partial Display Function containing selectable

active display block(s) (two blocks max.) and optimizing the duty cycle

ratio. This function dramatically reduces the operating current, setting

the optimum boosted voltage combined with a programmable voltage

booster circuit and an electrical variable resister. As result, it reduces

the operating current.

The operating voltage from 2.4V to 3.6V and low operating current are

suitable for small size battery operation items.

FEATURES

Direct Correspondence of Display Data RAM to LCD Pixel

Display Data RAM - 25,344 bits ;(1.5 times over than display size)

LCD drivers - 128-common and 132-segment

Direct connection to 8-bit Microprocessor interface for both of 68 and 80 type MPU

Serial Interface

Partial Display Function Two limited active display blocks setting. Duty ratio set automatically.

Easy Vertical Scroll by setting the start line address of over size display data RAM

Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12 bias

Common Driver Order Assignment by mask option

Version

NJU6679A Com0 to Com127

NJU6679B Com127 to Com0

Useful Instruction Sets

C0 to C127(Pin name)

Display ON/OFF Cont, Display Start Line Set, Page Address Set, Column Address Set, Status Read,

Display Data Read/Write, Inverse Display, All On/Off, Partial Display, Bias Select, n-Line Inverse,

Voltage Booster Circuits Multiple Select(Maximum 6-time), Read Modify Write, Power Saving, ADC Select, etc.

Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(6-time Maximum, Voltage boosting

polarity:Negative voltage(VDD Common)),Regulator, Voltage Follower (x 4)

Precision Electrical Variable Resistance

Low Power Consumption

Operating Voltage

--- 2.4V to 3.6V

LCD Driving Voltage --- 6.0V to 18V

Package Outline

--- COF / TCP / Bumped Chip

C-MOS Technology (Substrate:N)

2001

Ver.4.8

NJU6679

PAD LOCATION

C₄₆

C₄₇

DUMMY19

DUMMY18

DUMMY17

DUMMY16

DUMMY15

DUMMY14

DUMMY13

DUMMY12

V_DD

C₆₃

S₀

V₁

V₂

V₃

V₄

V₅

VR

V_DD

-

C1

C1 ⁺

-

C2

C2⁺

-

C3

C3⁺

-

C4

C4⁺

X

-

C5

C5⁺

V_OUT

V_SS

D₇

D₆

D₅

Y

D₄

D₃

D₂

D₁

D₀

RD

WR

A0

CS

OSC₂

OSC₁

T₁

T₂

V_SS

RES

SEL68

P/S

V_DD

DUMMY11

DUMMY10

DUMMY9

DUMMY8

DUMMY7

DUMMY6

DUMMY5

DUMMY4

DUMMY3

DUMMY2

DUMMY1

S₁₃₁

C₁₂₇

1

DUMMY0

C₁₁₁

C₁₁₀

Chip Center

Chip Size

Chip Thickness

Bump Size

Pad pitch

: X=0um,Y=0um

: X=10.31mm,Y=3.13mm

: 675um + 30um

: 45um x 83um

: 60um(Min)

Bump Height

Bump Material

: 15um TYP.

: Au

Voltage boosting polarity :Negative voltage (VDD Common)

Substrate :N

NJU6679

TERMINAL DESCRIPTION

Chip Size 10.31 x 3.13mm (Chip Center X=0um,Y=0um)

PAD No.

1

Terminal

DUMMY0

DUMMY1

DUMMY2

DUMMY3

DUMMY4

DUMMY5

DUMMY6

DUMMY7

DUMMY8

DUMMY9

DUMMY10

DUMMY11

VDD

X= um

-4884

-4132

-4062

-3992

-3922

-3852

-3782

-3712

-3642

-3572

-3502

-3432

-3270

-3104

-2884

-2648

-2490

-2333

-2098

-1877

-1641

-1420

-1184

-954

Y= um

-1405

PAD No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Terminal

V2

X= um

2792

2862

2932

3315

3385

3455

3525

3595

3665

3735

4884

4995

Y= um

-1405

-1416

-1356

-1296

-1236

-1176

-1116

-1056

-996

-936

-876

-816

-756

-696

-636

-576

-516

-456

-396

-336

-276

-216

-156

-96

2

V1

3

VDD

4

DUMMY12

DUMMY13

DUMMY14

DUMMY15

DUMMY16

DUMMY17

DUMMY18

DUMMY19

C0

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

C1

P/S

C2

SEL68

RES

C3

C4

VSS

C5

T2

C6

T¹

C⁷

OSC¹

OSC2

CS

C⁸

C9

C10

A0

C11

WR

C12

RD

-717

C13

D0

-481

C14

D1

-260

C15

D2

-40

C16

D3

180

C17

D4

400

C18

D5

621

C19

D6(SCL)

D7(SI)

V^SS

841

C20

1061

1222

1398

1468

1538

1608

1678

1748

1818

1888

1958

2028

2098

2168

2327

2582

2652

2722

C21

C²²

VOUT

C5⁺

C5^-

C4⁺

C4^-

C3⁺

C3^-

C2⁺

C23

-36

C24

24

C25

84

C26

144

C27

204

C28

264

C29

324

C30

384

C2^-

C1⁺

C1^-

C31

444

C32

504

C33

564

V^DD

C³⁴

624

VR

C35

684

V5

C36

744

V4

C37

804

V3

C38

864

NJU6679

PAD No.

101

102

103

104

105

106

107

108

109

110

111

Terminal

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C60

C61

C62

C63

S0

X= um

4995

5010

4950

4890

4830

4770

4710

4650

4590

4530

4470

4410

4350

4290

4230

4170

4110

4050

3990

3930

3870

3810

3750

3690

3630

3570

3510

3450

3390

3330

3270

3210

3150

3090

3030

2970

2910

2850

2790

2730

2670

2610

2550

2490

Y= um

924

PAD No.

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Terminal

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

X= um

Y= um

1405

2430

2370

2310

2250

2190

2130

2070

2010

1950

1890

1830

1770

1710

1650

1590

1530

1470

1410

1350

1290

1230

1170

1110

1050

990

984

1044

1104

1164

1224

1284

1405

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

930

S1

870

S2

810

S3

750

S4

690

S5

630

S6

570

S7

510

S8

450

S9

390

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

330

270

210

150

90

30

-30

-90

-150

-210

-270

-330

-390

-450

-510

NJU6679

PAD No.

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

Terminal

S75

X= um

-570

Y= um

1405

PAD No.

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

Terminal

S125

S¹²⁶

S127

S128

S¹²⁹

S130

S131

C127

C126

C¹²⁵

C124

C123

C¹²²

C121

C120

C119

C118

C117

C116

C115

C114

C¹¹³

C112

C111

C¹¹⁰

C109

C¹⁰⁸

C107

C106

C¹⁰⁵

C104

C103

C¹⁰²

C101

C¹⁰⁰

C99

X= um

Y= um

1405

1284

1224

1164

1104

1044

984

-3570

-3630

-3690

-3750

-3810

-3870

-3930

-3990

-4050

-4110

-4170

-4230

-4290

-4350

-4410

-4470

-4530

-4590

-4650

-4710

-4770

-4830

-4890

-4950

-5010

-4995

S⁷⁶

-630

S77

-690

S78

-750

S⁷⁹

-810

S80

-870

S81

-930

S82

-990

S83

-1050

-1110

-1170

-1230

-1290

-1350

-1410

-1470

-1530

-1590

-1650

-1710

-1770

-1830

-1890

-1950

-2010

-2070

-2130

-2190

-2250

-2310

-2370

-2430

-2490

-2550

-2610

-2670

-2730

-2790

-2850

-2910

-2970

-3030

-3090

-3150

-3210

-3270

-3330

-3390

-3450

-3510

S⁸⁴

S85

S86

S⁸⁷

S88

S89

S90

S91

S92

S93

S94

S95

S⁹⁶

S97

S98

S⁹⁹

S100

S¹⁰¹

S102

S103

S¹⁰⁴

S105

S106

S¹⁰⁷

S108

S¹⁰⁹

S110

S111

S¹¹²

S113

S¹¹⁴

S115

S116

S¹¹⁷

S118

S119

S¹²⁰

S121

S122

S123

S124

924

864

804

744

684

C98

624

C⁹⁷

564

C96

504

C⁹⁵

444

C94

384

C93

324

C⁹²

264

C91

204

C90

144

C⁸⁹

84

C88

24

C87

-36

C86

-96

C85

-156

NJU6679

PAD No.

301

302

303

304

305

306

307

308

309

310

311

Terminal

C84

C83

C82

C⁸¹

C80

C79

C⁷⁸

C⁷⁷

C76

C75

C74

C73

C⁷²

C71

C70

C69

C⁶⁸

C67

C66

C⁶⁵

C⁶⁴

X= um

-4995

Y= um

-216

-276

-336

-396

-456

-516

-576

-636

-696

-756

-816

312

313

314

315

316

317

318

319

320

321

-876

-936

-996

-1056

-1116

-1176

-1236

-1296

-1356

-1416

NJU6679

BLOCK DIAGRAM

C

0

C

63

S

0

S

131

C

127

C₆₄

V_SS

V_DD

to V

5

C O M

S E G

D r i v e r

C O M

V

1

5

D r i v e r

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

S h i f t

Voltage

R e g i s t e r

COM SEG

Timing

Generator

D i s p l a y D a t a L a t c h

VR

T₁,T₂

Display Data RAM

192 x 132

Culumn Address Decoder

Culumn Address Counter

Display

Timing

Generator

Culumn Address Register

M u l t i p l e x e r

OSC1

OSC2

OSC.

Instruction Decoder

B F

B u s H o l d e r

S t a t u s

I n t e r n a l B u s

M P U I n t e r f a c e

R e s e t

RES

SEL68

RD

D₀to D₇(SI,SCL)

CS

WR

A0

P/S

NJU6679

TERMINAL DESCRIPTION

No.

Symbol I/O

F u n c t i o n

DUMMY0

to

1 to 12,

54 to 61

Dummy Terminals.

These are open terminals electrically.

DUMMY19

Power

VDD

13,46,53

17,34

Power Supply Terminal (+2.4V - +3.6V)

VSS

GND Ground Terminal (0V)

Power

52

51

50

49

48

V1

V2

V3

V4

V5

LCD Driving Voltage Supplying Terminals. In case of the external power supply

operation without internal power supply operation, each level of LCD driving

voltage is supplied from outside fitting with following relation.

VDD>V1>V2>V3>V4>V5>VOUT

In case of the internal power supply, LCD driving voltages V1-V4 depending on

the Bias selection are supplied as shown in follows;

Bias

V1

V2

V3

V4

V

5+3/4VLCD

V5+2/4VLCD

V5+3/5VLCD

V5+4/6VLCD

V5+5/7VLCD

V5+6/8VLCD

V5+7/9VLCD

V5+2/4VLCD

V5+2/5VLCD

V5+2/6VLCD

V5+2/7VLCD

V5+2/8VLCD

V5+2/9VLCD

V5+1/4VLCD

V5+1/5VLCD

V5+1/6VLCD

V5+1/7VLCD

V5+1/8VLCD

V5+1/9VLCD

1/4Bias

1/5Bias

1/6Bias

1/7Bias

1/8Bias

1/9Bias

1/10Bias

1/11Bias

V5+4/5VLCD

V5+5/6VLCD

V5+6/7VLCD

V5+7/8VLCD

V5+8/9VLCD

V5+9/10VLCD

V5+8/10VLCD V5+2/10VLCD V5+1/10VLCD

V5+10/11VLCD V5+9/11VLCD V5+2/11VLCD V5+1/11VLCD

V5+11/12VLCD V5+10/12VLCD V5+2/12VLCD V5+1/12VLCD

1/12Bias

(VLCD=VDD-V5)

44,45

42,43

40,41

38,39

36,37

C1⁺,C1^-

C2⁺,C2^-

C3⁺,C3^-

C4⁺,C4^-

C5⁺,C5^-

O

Capacitor connecting terminals for Internal Voltage Booster.Boosting time is

programmed by instruction (2 to 6 times )

35

VOUT

O

I

Boosted voltage output terminal. Connects the capacitor between VOUT

terminal and VSS.

47

VR

VLCD voltage adjustment terminal. The gain of VLCD setup circuit for V5 level is

adjusted by external resistors.

19

18

T1

T2

I

LCD bias voltage control terminals.

Voltage

T1

T2

Voltage Adj.

V/F Cir.

booster Cir.

Available

L

H

L/H

L

Available

Not Avail.

Available

Not Avail.

H

26 to 33

D0 to

D7

I/O Data Input/Output terminals.

In Pararel Interface Mode (P/S="H")

I/O terminals of 8-bit bus.

(SI)

(SCL)

In Serial Interface Mode (P/S="L")

D7: Input terminal of serial data ( SI ).

D6: Input terminal of serial data clock ( SCL ).

D0 to D5 terminals are Hi-impedance.

When CS="H", D0 to D7 terminals are Hi-impedance.

23

A0

I

Data discremination signal input terminal. The signal from MPU discreminates

transmoitted data between Display data and Instruction.

A0

H

L

Distin. Display Data Instruction

16

22

RES

CS

I

Reset terminal.

Reset operation is executing during "L" state of RES.

Chip select signal input terminal.

Data Input/Output are available during CS ="L".

NJU6679

No

Symbol I/O

F u n c t i o n

25

24

RD(E)

I

RD(80 type) or E(68 type) signal input terminal.

<In 80 type MPU mode >( SEL68="L" )

RD signal from 80 type MPU input terminal. Active "L".

D0 to D7 terminals are output during "L" level.

<In 68 type MPU mode >( SEL68="H" )

Enable signal from 68 type MPU input terminal. Active "H".

WR(RW)

I

WR(80 type) or R/W(68 type) signal input terminal

<In 80 type MPU mode >( SEL68="L" )

WR signal from 80 type MPU input terminal. Active "L".

The data transmitted during WR="L" are fetched at the rising edge of WR.

<In 68 type MPU mode > ( SEL68="H" )

R/W signal from 68 type MPU input terminal.

R/W

H

L

State

Read

Write

15

14

SEL68

P/S

I

MPU interface type selection terminal. This terminal must connect to V DD or

VSS.

SEL68

State

H

L

68 Type

80 Type

Parallel or Serial interface selection signal input terminal.

Data/Command

Chip Select

CS

Read/Write serial Clock

P/S

"H"

"L"

Data

D0 to D7 RD,WR

SI(D7)

A

-

CS

A0

-

SCL(D6)

In case of serial interface( P/S="L")

RAM data and status read operation do not work in mode of the serial

interface. RD and WR terminals must fix to "H" or "L". D0 to D5 terminals are

Hi-impedance.

20

21

I

External clock input terminal. In Internal oscillation operation, OSC1 and OSC2

terminals should be Open.In External clock operation, the external clock input to

OSC1 terminal.

OSC1

OSC2

62 to 125

C0 to

C63

O

LCD driving signal output terminals.

Common output terminals:C 0 to C127

Segment output terminals:S 0 to S131

Common output terminal

Following output voltage is selected by the combination of alternating (FR)

signal and Common scanning data.

Scan data

H

FR

H

L

Output Voltage

V5

VDD

V1

126 to 257 S0

O

toS131

H

L

V4

Segment output terminal

Following output voltage is selected by the combination of alternating (FR)

signal and display data in the DD RAM.

321 to 258 C64 to

C127

Output Voltage

RAM

Data

FR

Normal

Reverse

V2

H

L

VDD

V5

H

L

V3

H

L

V2

VDD

V5

V3

NJU6679

Functional Description

(1) Description for each blocks

(1-1) Busy Flag (BF)

The Busy Flag (BF) is set to logical ”1” in busy of internal execution by an instruction, and any instruction

excepting for the “Status Read” is disable at this time. Busy Flag is outputted through D7 terminal by “Status

Read” instruction. Although another instructions should be inputted after check of Busy Flag, no need to check

Busy flag if the system cycle time (tCYC) as shown in AC Characteristics is secured completely.

(1-2)Display Start Line Register

The Display Start Line Register is a register to set a display data RAM address corresponding to the COM0

display line (the top line normally) for the vertical scroll on the LCD, Page address change and so forth. The

Display Start Line Address set instruction sets the 8-bit display start address into this register.

(1-3) Line Counter

Line Counter is reset when the internal FR signal is switched and outputs the line address of the display data

RAM by count up operation synchronizing with common cycle of NJU6679.

(1-4) Column Address Counter

Column Address Counter is the 8-bit preset-able counter to point the column address of the display data RAM

(DD RAM) as shown in Figure 1. The counter is incremented automatically after the display data read/write

instructions execution. When the Column address counter reaches to the maximum existing address by the

increment operations, the count up operation (increment) is frozen. However, when new address is set to the

column address counter again, it restarts the count up operation from a set address. The operation of Column

Address Counter is independent against Page Address Register.

By the address inverse instruction (ADC select) as shown in Figure 1, Column Address Decoder reverses the

correspondence between Column address and Segment output of display data RAM.

(1-5) Page address Register

Page Address Register assigns the page address of the display data RAM as shown in Figure 1. In case of

accessing from the MPU with changing the page address, Page Address Set instruction is required.

(1-6) Display Data RAM

The Display data RAM (DD RAM) is the bit map RAM consisting of 25,344 bits to store the display data corre-

sponding to the LCD pixel on LCD panel.

The DD RAM data and the state of the LCD:

In Normal Display : “1”=Turn-On Display, “0” =Turn-Off Display

In Reveres Display : “1”=Turn-Off Display, “0” =Turn-On Display

DD RAM output 132 bits parallel data addressed by line address counter then the data latched in the display data

latch. Asynchronous data access to the DD RAM is available due to the access to the DD RAM from the CPU

and latch to the display data latch operation are done independently.

(1-7) Common Driver Assignment

This circuit determines the scanning direction of the common output.

Table 1

C O M O utputs Terminals

62

125

258

321

P A D N o .

P in na m e

Ver.A

C 0

C 63

C O M 63

C O M 64

C 127

C 64

C O M 64

C O M 63

C O M 0

C O M 127

C O M 0

Ver.B

The Mask fixes the common scanning direction between version A and B that can not be changed by the instruction.

NJU6679

F o r example the

Line

P a g e A d d ress

D A TA

D ispla y P a tte rn

D ispla y start line

Address

is 10H

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

0 0

0 1

0 2

0 3

0 4

0 5

0 6

0 7

0 8

0 9

0 A

0 B

0C

0D

0 E

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(0,0,0,0,0)

P e g e 0

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(0,0,0,0,1)

P e g e 1

0 F

1 0

11

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

C n Out

C 0

C 1

C 2

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(0,0,0,1,0)

C 3

P e g e 2

C 4

C 5

C 6

C 7

C 8

C 9

:

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

8 6

8 7

8 8

8 9

8 A

8 B

8C

8D

8 E

8 F

9 0

9 1

9 2

9 3

9 4

9 5

9 6

9 7

9 8

9 9

C 118

C 119

C 1 2 0

C 1 2 1

C 1 2 2

C 1 2 3

C 1 2 4

C 1 2 5

C 1 2 6

C 1 2 7

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(1,0,0,0,1)

P e g e 1 7

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(1,0,0,1,0)

P e g e 1 8

:

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

B 6

B 7

B 8

B 9

B A

B B

B C

B D

B E

B F

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(1,0,1,1,1)

P e g e 2 3

|

0 0

0 1 0 2 0 3 0 4 0 5

0 6

0 7 0 8 0 9

7 A 7 B 7 C 7 D 7 E 7 F 8 0

8 1 8 2 8 3

D 0="0"

D 0="1"

A

D

C

C o lum n

A d d ress

8 3 8 2

8 1 8 0 7 F 7 E 7 D 7 C 7 B 7 A

0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0

S e g m e nt

Output

1 2 2

1 2 3

1 2 4

1 2 5

1 2 6

1 2 7

1 2 8

1 2 9

1 3 0

1 3 1

0

1

2

3

4

5

6

7

8

9

Fig.1 Correspondence with Display Data RAM Address

NJU6679

(1-8) Reset Circuit

When the input signal to RES terminal goes to “L”, the reset circuit executes initialization as below;

The Initialization state (default)

1

2

Display Off

Normal Display (not inverse)

3

4

ADC Select : Normal (ADC Instruction D0 =”0”)

Read Modify Write Mode Off

5

6

Voltage Booster off, Voltage Regulator off, Voltage follower off

Static Drive Off

7

Driver Output Off

8

9

Clear the data of serial interface register

Set the Column Address Counter to 00H

Set the Display Start Line Register to 00H

Set the Page Address Register to page “0”

Set the EVR register to FFH

Set the Partial Display(1/128 duty)

Set the Bias select(1/12 Bias)

Set the Voltage Booster(6 times)

Set the n-line inverse register to 0H

10

11

12

13

14

15

16

The RES terminal connects to the reset terminal of the MPU synchronization with the MPU initialization as shown

in “ the MPU interface “ in the Application Circuit section. The “L” level input signal as reset signal must keep the

period over than 10us as shown in DC Characteristics. The NJU6679 takes 1us for the reset operation after the

rising edge of the RES signal.

The reset operation by RES =”L” initializes each resister setting as above reset status, but the internal oscillation

circuit and output terminals (D0 to D7) are not affected.

To avoid the lock-up, the reset operation by the RES terminal must be required every time when power terns on.

The reset operation by the reset instruction, function 9 to 16 operations mentioned above is performed.

The RES terminal must be keep “L” level when the power terns on in not use of the built-in LCD power supply circuit

for no affect to the internal execution.

(1-9) LCD Driving Circuit

(a) LCD Driving Circuits

LCD driver is 260 sets of multiplexer consisting of 132 segments and 128 commons drivers to output LCD driving

voltage. The common driver outputs the common scan signals formed with the shift register. The segment driver

outputs the segment driving signal determined by a combination of display data in the DD RAM, common timing, FR

signal, and alternating signal for LCD. The output wave forms of segment/common are shown in LCD DRIVING

WAVEFORM.

(b) Display Data Latch Circuits

Display Data Latch Circuit latches the 132-bit display data outputted from the DD RAM addressed by the Line

address counter to LCD driver at every common signal cycle temporarily. The original data in the DD RAM is not

changed because of the Normal/Reverse display, Display On/Off, Static drive On/Off instruction processes only

stored data in this Display Data Latch Circuit.

(c) Signal forming to Line Counter and Display Data Latch Circuit

The count clock to Line Counter and the latch clock to Display Data Latch Circuit are formed using the internal

display clock (CL). The display data of 132 bits from Display Data RAM pointed by the line address synchroniz-

ing with the internal display clock are latched into the Display Data Latch Circuit and are outputted to LCD

driving circuits.

The display data read out operation from DD RAM to the LCD Driver Circuit is completely independent operation with

an access to the display data RAM from MPU.

(d) Display Timing Generation Circuit

The display timing generation circuit generates the internal timing of the display system by the master clock and the

internal FR signal. As for it, the internal FR signal and the LCD alternating signal generate the wave form of 2-frame

alternating drive wave form or the n-line inverse drive method for the LCD Driving circuit.

NJU6679

(e)Common Timing Generator

The Common Timing Generator generates the common timing signal from the display clock (CL ).

-2-frame alternating drive mode

127 128 1

2

3

4

5

6

7

8

125 126 127 128 1

2

3

4

5

CL

FR

V

DD

V

1

C0

C1

V

4

V

5

V

DD

V1

V

4

V

5

RAM DATA

Sn

V

2

DD

V

3

V

5

Fig.2

-n-line inverse drive mode (n=7, line inverting register sets to 6)

127 128 1

2

3

4

5

6

7

8

125 126 127 128 1

2

3

4

5

CL

FR

V

DD

V

1

C0

C1

V

4

V

5

V

DD

V

1

V

4

V

5

RAM DATA

Sn

V

2

DD

V

3

V

5

Fig.3

NJU6679

(f) Oscillation Circuit

The Oscillation Circuit is a low power type CR oscillator using an internal resistor and capacitor. The oscillator

output is using for the display timing clock and for the voltage booster circuit. And the display clock(CL) is generated

from this oscillator output frequency by dividing.

-The relation between duty and divide

Table 2

Duty

1/8

1/16 1/24 1/32 1/40 1/48 1/56 1/64 1/72 1/80,88 1/96,104 1/112,120,128

1/9 1/8 1/7 1/6 1/5 1/4

Divide

1/64 1/32 1/21 1/16 1/12 1/10

(g) Power Supply Circuit

The internal power supply circuit generates the voltage for driving LCD. It consists of voltage booster circuits (from 2

times to 6 times), voltage regulator circuits, and voltage followers.

The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction.

When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator circuits,

voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4,V5 and VOUT for the LCD

should be supplied from outside, terminals C1⁺, C1^-, C2⁺, C2^-, C3⁺, C3^-, C4⁺, C4^-, C5⁺, C5^-, and VR should be

open. The status of internal power supply is selected by T1 and T2 terminal. Furthermore the external power

supply operates with some of internal power supply function.

Table 3

Voltage

Booster

C1+,C1- to

C5+,C5-

T1

T2

Voltage Adj.

Buffer(V/F) Ext.Pow Supply

VR Term.

L

L/H

L

ON

OFF

ON

-

H

VOUT

Open

H

OFF

V5,VOUT

Open

When (T1, T2)=(H, L), C1⁺, C1^-, C2⁺, C2^-,C3⁺, C3^-, C4⁺, C4^-, C5⁺, C5^-terminals for voltage booster circuits are

open because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal

should be supplied from outside.

When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster circuits

and Voltage adjust circuits do not operate.

The internal power supply Circuits is designed specially for a small-size LCD like as normal cellular phone size

LCD panel. When NJU6679 apply to the large size LCD panel application (large capacitive load), external power

supply is required to keep good display condition..

To keep good display condition, external component of the capacitors connecting to the V1 to V5 terminals and

voltage booster circuits and the feedback resistors for the V5 operational amplifier must fix each optimized con-

stant after checking various display patterns on LCD panel actually in the application.

NJU6679

(2) Instruction

The NJU6679 distinguishes the data on the data bus D0 to D7 as an instruction by combination of A0, RD, and WR(R/W)

signals. The decoding of the instruction and exection performes with only high speed internal timing without relation to

the external clock. Therefore, no busy flag check required normally. In case of the serial interface, the data input as

MSB(D7) first serially. Table.4 shows the instruction codes of the NJU6679.

(*:Don't Care)

Table 4. Instruction Code

C o d e

In s truc tio n

D e s c rip tio n

A 0 R D W R D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

0 /1

(a )

(b )

D i s p la y O N /O F F

0

1

0

1

0

1

0

1

L C D D i s p la y O N /O F F

0 :O F F 1 :O N

D i s p la y S ta rt L ine S e t

H ig h O r d e r 4 b i t s

0

1

0

1

0

1

H ig h O r d e r

A d d re s s

D e te rm ine the D isp la y L i n e o f

R A M to the C O M 0 .

(S e t th e H ig h e r o rd e r 4 b its )

D i s p la y S ta rt L ine S e t

L o w e r O rd e r 4 b its

0

1

0

1

0

L o w e r O rd e r

A d d re s s

D e te rm ine the D isp la y L i n e o f

R A M to the C O M 0 .

(S e t th e L o w e r o rd e r 4 b its )

H i.

(c)

(d )

P a g e A d d re s s S e t

H ig h O r d e r 1 b i t s

*

S e t th e H ig h e r o rd e r 1 b it p a g e

o f D D R A M to the P a g e

A d d re s s R e g iste r

P a g e A d d re s s S e t

L o w e r O rd e r 4 b its

L o w e r O rd e r

P a g e A d d re s s o f D D R A M to the P a g e

S e t th e L o w e r o rd e r 4 b it p a g e

A d d re s s R e g iste r

C o lum n A d d re s s S e t

H ig h O r d e r 4 b i t s

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

H ig h O r d e r

C o lum n A d d .

S e t th e H ig h e r o rd e r 4 b its

C o lum n A d d re s s to the R e g .

C o lum n A d d re s s S e t

L o w e r O rd e r 4 b its

L o w e r O rd e r

C o lum n A d d .

S e t th e L o w e r o rd e r 4 b its

C o lum n A d d re s s to the R e g .

(e )

(f)

S ta tus R e a d

S ta tus

0

R e a d o ut the inte rna l S ta tus

W rite D i s p la y D a ta

R e a d D i s p la y D a ta

W rite D a ta

R e a d D a ta

W rite the d a ta into the D isp la y

D a ta R A M

(g )

(h)

R e a d the d a ta fro m the D isp la y

D a ta R A M

0 /1

N o rm a l o r Inve rs e

O N /O F F S e t

1

0

1

0

1

Inve r s e t h e O N a n d O F F

D i s p la y

0 :N o rm a l 1 :Inve rse

0 /1

0

(i)

(j)

S ta tic D rive O N

/N o rm a l D i s p la y

0

1

0

1

0

1

0

1

0

1

0

W h o le D i s p la y Turns O N

0 :N o rm a l 1 :W h o le D isp . O N

S u b i n s truc tio n ta b le

m o d e

S e t th e S ub instruc tio n ta b le .

(k)P a rtia l D isp la y

1 s t B lo c k , S e t

0

1

0

1

0

S ta rt d i s p la y

unit

S e t th e S ta rt d i s p lay unit of 1st

B lo c k .

S ta rt d i s p lay unit

1 s t B lo c k ,

S e t The n u m b e r o f

d isp la y units

num b e r o f d i s p la y

units

S e t the num b e r o f d i s p lay units

o f 1 s t B lo c k .

2 n d B lo c k , S e t

0

1

0

1

0

1

0

S ta rt d i s p la y

unit

S e t th e S ta rt d i s p lay unit of 2nd

B lo c k .

S ta rt d i s p lay unit

2 n d B lo c k ,

S e t The n u m b e r o f

d isp la y units

num b e r o f d i s p la y

units

S e t the num b e r o f d i s p lay units

o f 2 n d B lo c k .

P a rtia l d i s p la y o n

0

1

0

1

0

It c o m e s o ff the m o d e to s e t

a n d a d i s p la y is e xe c ute d .

Sub

Inst.

(l)n-line Inve rse D rive S e t

R e g iste r S e t

H ig h e r o rd e r 2 b its

0

1

0

1

0

1

0

1

*

hig h e r S e t the num b e r o f inve rse d rive

o rd e r

line .

R e g iste r S e t

L o w e r o rd e r 4 b its

L o w e r o rd e r

S e t the num b e r o f inve rse d rive

line .

n-lin e Inve r s e D rive

S e t is e xe c ute d .

0

T h e e xe c uti o n o f the line inve rse

d rive .

(m )E V R R e g iste r S e t

E V R R e g iste r S e t

H ig h e r o rd e r 4 b its

0

1

0

1

0

1

E V R D a ta

H ig h e r o rd e r

S e t th e V 5 o u tp u t le v e l to the

E V R re g iste r. (H i g h e r o r d e r 4

b its )

E V R R e g iste r S e t

L o w e r o rd e r 4 b its

E V R D a ta

L o w e r o rd e r

S e t th e V 5 o u tp u t le v e l to the

E V R re g iste r. (L o w e r o rd e r 4

b its )

E V R R e g iste r S e t

is e xe c ute d .

0

1

0

1

0

1

0

1

0

1

T h e e xe c uti o n o f the E V R .

(n)

E n d o f s u b i n s truc tio n

ta b le m o d e

It e n d s the s e tting o f sub

instruc tio n ta b le .

NJU6679

(*:Don't Care)

C o d e

Instruc tio n

D e s c rip ti o n

A 0 R D W R D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

(o )

(p )

(q )

(r)

B i a s S e le c t

0

1

0

1

0

1

0

1

0

1

0

B i a s

S e le c t th e b i a s

(9 P a tte rns)

B o o s t L e vel S e le c t

B o o s t

0

S e t th e B o o s te r circuits

M ultiple

0

0 /1

R e a d M o d ify W rite

/E nd

0

R e a d M o d ify W rite m o d e

D 0 = 0 :O n D 0 = 1 :E nd

R e s e t

1

0

1

0

Initia lize the inte rna l C ircuits

0 /1

(s)

(t)

Inte rna l P o w e r S u p p ly

O N /O F F

0 :Int. P o w e r S u p p ly O F F

1 :Int. P o w e r S u p p ly O N

0 /1 D 0 = 0 : L C D D rive r Outouts OFF

D 0 = 1 : L C D D rive r Outputs ON

D rive r O utputs

O N /O F F

(u)

P o w e r S a ve

(C o m p le x C o m m a n d )

S e t th e P o w e r S a ve M o d e

(L C D D i s p la y O F F

+ W h o le D isp lay Turns O N )

0 /1

(v)

A D C S e le c t

0

1

0

1

0

1

0

S e t th e D D R A M vs S e g m e nt

D 0 = 0 :N o r m a l D 0 = 1 :Inve rse

NJU6679

(2-1) Explanation of Instruction Code

(a) Display On/Off

It executes the ON/OFF control of the whole display without relation to the DD RAM or any internal conditions.

A 0

0

RD

1

W R

0

D 7

1

D 6

0

D 5

1

D 4

0

D 3

1

D 2

1

D 1

1

D 0

D

D 0:Display Off

1:Display On

(b) Display Start Line

It sets the DD RAM line address corresponding to the COM0 terminal (normally assigned to the top display line).

In this instruction execution, the display area is automatically set by the lines that correspond to the display duty

ratio to the upward direction of the line address. Changing the line address by this instruction performs smooth

scrolling to a vertical direction. In this time, the DD RAM data are unchanged.

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

0

D 4

1

D 3

A 7

D 2

A 6

D 1

A 5

D 0

A 4

0

1

0

1

0

A3

A2

A1

A0

A7

0

A6

A5

A4

0

A3

0

A2

0

A1

A0

Line Address(HEX)

0

1

00

01

0

:

1

0

1

BF

(c) Page Address Set

When MPU access to the DD RAM, a page address is set by page Address Set instruction before writing the

data. (Note: the change of page address is not affected to the display.)

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

0

D 4

0

D 3

*

D 2

*

D 1

*

D 0

A 4

0

1

0

1

0

A3

A2

A1

A0

(*:Don't Care)

A4

A3

A2

0

A1

0

A0

0

Page

0

1

0

1

:

1

0

1

23

NJU6679

(d) Column Address

When MPU accesses to the DD RAM , the row address set by Page Address Set instruction is required with the

column address before writing the data. The column address set requires twice address set which are higher

order 4 bits address set and lower order 4 bits.

When the MPU access to the DD RAM continuously, the column address increments automatically from the set

address after each data access. Therefore, the MPU can transmit only the Data continuously without setting the

column address at every transmission time. The increment of column address is stopped at the maximum column

address plus 1 limited by each display mode. When the column address count up is stopped, the row address is

not changed.

A 0

0

RD

1

W R

0

D 7

0

D 6

0

D 5

0

D 4

1

D 3

A 7

D 2

A 6

D 1

A 5

D 0

A 4

Higher Order

Lower Order

0

1

0

A3

A2

A1

A0

A7

0

A6

A5

0

A4

A3

A2

0

A1

A0

Column Address(HEX)

0

:

0

1

0

1

:

0

:

1

0

1

83

(e) Status Read

This instruction reads out the internal status of "BUSY", “ADC", "ON/OFF" and "RESET" described as follows.

A 0

0

RD

0

W R

1

D 7

D 6

D 5

D 4

D 3

0

D 2

0

D 1

0

D 0

0

ON/OFF

R E S E T

BUSY

A D C

BUSY : BUSY=1 indicate the operating or the Reset cycle.

All instructions can be input after the BUSY status change to "0".

ADC

: Indicate the output correspondence of column (segment) address and segment driver.

0 :Counterclockwise Output (Inverse)

1 :Clockwise Output

(Normal)

(Note) The data "0=Inverse" and "1=Normal" of ADC status is inverted with the ADC select

Instruction of "1=Inverse" and "0=Normal".

ON/OFF : Indicate the whole display On/Off status.

0 : Whole Display "On

1 : Whole Display "Off"

(Note) The data "0=On" and "1=Off" of Display On/Off status is inverted with the Display On/Off

instruction data of "1=On" and "0=Off".

RESET : Indicate the initializing by RES terminal signal or reset instruction.

0 : Not Reset status

1 : In the Reset status

NJU6679

(f) Write Display Data

It writes the data on the data bus into the DD RAM. column address increments automatically after data writing,

therefore, the MPU can write the data into the DD RAM continuously without the address setting at every writing

time once the starting address is set.

A 0

1

RD

1

W R

0

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

W R ITE DATA

(g) Read Display Data

This instruction reads out the 8-bit data from DD RAM addressed by the column and the page address. The

column address automatically increments after the 8-bit data read out, therefore, the MPU can read the data from

the DD RAM continuously without the address setting at every reading time once the starting address is set.

Note that the dummy read is required just after setting the column address (see “(4-4) Access to the DD RAM

and the Internal Register”).

In the serial interface mode, the display data is unable to read out.

A 0

1

RD

0

W R

1

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

R E A D D ATA

(h) Normal or Inverse On/Off Set

It changes the display condition of normal or reverse for entire display area. The execution of this instruction does

not change the display data in the DD RAM.

A 0

0

RD

1

W R

0

D 7

1

D 6

0

D 5

1

D 4

0

D 3

0

D 2

1

D 1

1

D 0

D

D 0 : Normal

1 : Inverse

RAM data "1" correspond to "On"

RAM data "0" correspond to "On"

(i) Static Drive

This instruction turns all the pixels ON regardless the data stored in the DD RAM. In this time, the data in DD

RAM are remained and unchanged. This instruction is executed prior to the "Normal or Inverse On/Off Set"

Instruction.

A 0

0

RD

1

W R

0

D 7

1

D 6

0

D 5

1

D 4

0

D 3

0

D 2

1

D 1

0

D 0

D

D 0 : Normal Display

1 : Whole Display turns On

When the “Static Drive ON” instruction is executed at Display OFF status, the NJU6679 operates in

Power Save Mode. (Refer “ Power Save Mode “)

NJU6679

(j) Sub Instruction table mode

This instruction switches the instruction table from the main to the sub. The sub instruction table contains instruc-

tions of partial display, n-line inverse drive set and EVR register set as mentioned in (k), (l) and (m).

The instruction of sub instruction table mode must be executed before above 3 sub instructions execution. The

instruction of end of sub instruction table mode (n) switches the instruction table from the sub to the main. If any

main instructions are written in the sub instruction mode, the NJU6679 will malfunction.

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

0

-Set sub Instruction table flow is shown below:

Sub Instruction table

mode

Switches to Sub instruction table mode.

Switches to Main instruction mode.

Set sub instructions.

End of Sub Instruction

table mode.

(k) Partial Display

It selects two active display areas on the LCD Panel partially. The display area is divided to 16 units with four

commons each and selected two display blocks by setting Unit number and number of Unit required (not overlap,

not over than 16 units) to display on the LCD panel. These two display blocks are assigned optionally on the LCD

panel. Duty selects an adapted ratio number corresponding to the total number of two display blocks automati-

cally.

Partial Display function adjusts the LCD driving voltage, Voltage boosting times and E.V.R level by the instruction

to generate the optimum LCD driving voltage for display quality. As result, the operating current is reduced.

· Display Unit Structure

UNIT

0

1

2

3

4

5

6

7

(8 commons)

128-common

8

9

10

11

12

13

14

15

(8 commons)

132-segment

NJU6679

Partial display instruction

When Partial Display functions, both of Top Unit Number of display area (the Start Unit) and the number of the

effective continuous unit (Display Unit) from the Start Unit for the first display block and the second. Attention that

the first display block and the second definition must not be overlap of display area and not be over than 16 units

in total.

In case of whole display (1/128 duty), the first display block defines Start Unit=0 (0,0,0,0) and Display Unit = 16

(1,0,0,0,0) for all of display area selection. In this time, the definition of the second display block is ignored.

In case of only the first block display, the second display block defines Start Unit=0 (0,0,0,0) and Display Unit = 0

(0,0,0,0,0) for no display area.

A 0

0

RD

1

W R

0

D 7

0

D 6

0

D 5

0

D 4

0

D 3

D

D 2

D

D 1

D

D 0

D

Start unit

1^stBlock

2^ndBlock

The display unit

number

0

1

0

1

0

1

0

1

D

0

D

Start unit

The display unit

number

D

By input following instruction, the duty ratio is changed automatically and executes

the partial display function.

Partial display

on

0

1

0

1

0

D :unit number (Hex.)

Notes)

Attention followings due to prevent from mulfunction

· The input order of Partial Display instructions must follow above.

· Prohibits the overlap of the 1^stpartial display block and the 2^nd.

· The Start Unit of the 1^stpartial display block must not be over 15.

· The total Display Unit Number (the sum of the 1^stand 2^ndpartial display block Unit Num

ber) must not be over 16.

· On the LCD panel, no active display area inserts between the 1^stdisplay block and the 2^nd.

However, the display data of the 1^stdisplay block and the 2^ndmust store continuously in

the display data RAM.

NJU6679

Example of the Partial Display setting.

UNIT 0

1^stBlock

UNIT 1

UNIT 2

UNIT 3

UNIT 4

UNIT 5

UNIT 6

UNIT 7

UNIT 8

UNIT 9

UNIT 10

UNIT 11

UNIT 12

UNIT 13

UNIT 14

UNIT 15

2^ndBlock

active display-block

The above partial display condition is set as follows:

1)Set sub instruction mode

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

D 0

0

Set sub instruction

mode.

0

2)Set partial display conditions

A 0

0

RD

1

W R

0

D 7

0

D 6

0

D 5

0

D 4

0

D 3

0

D 2

0

D 1

0

D 0

0

1^stBlock, Set start unit

to ”0”

1^stBlock, Set the display

unit number to ”2”

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2^ndBlock, Set start unit

to ”4”

2^ndBlock, Set the display

units number to ”5”

Execute Partial display.

The Duty is changed to 1/56 automatically.

3)End sub instruction mode

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

1

End sub instruction

mode. Back to main

instruction mode.

Duty is changed automatically when Partial Display execution. But LCD Driving Voltage, Bias, Driving form like as

2-frame alternating driving or n-line inverse are not changed. Therefore, Display Off should operate before Partial

Display execution for prevention of unexpected display, and Voltage Booster Select instruction, E.V.R Register

Set, Bias Select and n-line Inverse Driving Set should set optimum conditions for good display in the mean time of

Partial Display instruction execution. The optimum conditions should fix refering the result of actual display

eveluation.

NJU6679

-Set Partial Display flow is shown below:

Inte rna l P o w e r S up p ly O F F

S u b In s tru c tio n Ta b le M o d e

S e t a S ta rt U n i t o f t h e f i r s t d i s p l a y u n i t

S e t a n u m b e r o f D i s p la y Unit of the first

S e t a S ta rt U n i t o f t h e s e c o n d d i s p la y unit

S e t a n u m b e r o f D i s p la y U n i t o f t h e s e c o n d

E xe c ute s P a rtia l D i s p la y func tio n

n-lin e Inve rs e D rive S e t

E V R R e g i s te r S e t

E n d S u b In s tru c tio n Ta b le

M o d e

B i a s S e le c t

V o lta g e B o o s te r Tim e s S e le c t

W a it Tim e

Inte rna l P o w e r S up p ly O N

(l) n-line Inverse Drive Mode

n-Line Inverse Register Set (refer +Functional Description Fig.3 n-line Inverse alternative drive mode)

It sets a line number to inverse the polarity of common driver and segment.

The instructions must be input in order of followings. These instructions are sub instruction sets and must be set

after (j)Sub instruction table mode.

1)Set sub instruction mode

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

0

Set sub instruction

mode.

2)Set n-line Inverse number

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

0

D 4

1

D 3

*

D 2

*

D 1

A 5

D 0

A 4

Higher order

Low order

0

1

0

1

0

A3

A2

A1

A0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

0

Inverse line

(*:2-frame alternating

drive mode.)

-(*)

2

0

1

:

1

64

3)Execute the n-line Inverse

A 0

0

RD

1

W R

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

0

4)End sub instruction mode

A 0

RD

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

1

End sub instruction

mode. Back to main

instruction mode.

0

1

NJU6679

(m) EVR Register Set

It controls the voltage regulator circuit of the internal LCD power supply to adjust the LCD display contrast by

changing the LCD driving voltage “V5”. By data setting into the EVR register, the LCD driving voltage “V5” selects

out of 201 steps of regulated voltage. The voltage adjustable range of “V5” is fixed by the external resistors. For

details, refer the section “(3-2) Voltage Adjust Circuits”.

1)Set sub instruction mode

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

0

Set sub instruction

mode.

2)Set EVR Register

A 0

0

RD

1

W R

0

D 7

1

D 6

0

D 5

0

D 4

0

D 3

A 7

D 2

A 6

D 1

A 5

D 0

A 4

0

1

0

1

0

1

A3

A2

A1

A0

A7

0

A6

0

A5

1

A4

1

A3

0

A2

1

A1

1

A0

VLCD

1

Low

:

1

High

VLCD=VDD-V5

When EVR doesn't use, set the EVR register to (1,1,1,1,1,1,1,1).

3)Execute the EVR

A 0

RD

1

W R

0

D 7

1

D 6

0

D 5

1

D 4

0

D 3

0

D 2

0

D 1

0

D 0

0

4)End sub instruction mode

A 0

RD

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

1

End sub instruction

mode. Back to main

instruction mode.

0

1

(n) End of Sub instruction table mode

"End of sub instruction table mode" instruction switches instruction table from sub to main.

(k)Partial display, (l)n-line inverse drive mode, and (m)EVR are sub instruction sets on the sub instruction table.

The instruction of “END of sub instruction mode” must be set after these sub instruction sets. The NJU6679 may

occur incorrect operation if any main instructions on the main instruction table are input in mode of sub instruction

table.

A 0

0

RD

1

W R

0

D 7

0

D 6

1

D 5

1

D 4

1

D 3

0

D 2

0

D 1

0

D 0

1

NJU6679

(o) Bias Select

This instruction sets the bias voltage.

A0

0

RD

1

W R

0

D 7

1

D 6

0

D 5

1

D 4

1

D 3

A 3

D 2

A 2

D 1

A 1

D 0

A 0

(*:Don't Care)

A3

0

A2

0

1

*

A1

0

1

0

1

*

A0

0

1

0

1

0

1

0

1

*

Bias

1/4

1/5

0

1/6

0

1/7

0

1/8

0

1/9

0

1/10

1/11

1/12

0

1

(p) Boost Level Select

This instruction sets the boost level (2 to 6 times). When “Partial Display Instruction” execution, the “Boost Level

Select” also must be executed. If the external capasitors are connected as the lower than 6 times boost level,

don’t set the boost level by the instruction over than the boost level by conecting capasitors. If set the boost level

over than it, the device will make malfunction.

A0

0

RD

1

W R

0

D 7

0

D 6

0

D 5

1

D 4

1

D 3

0

D 2

A 2

D 1

A 1

D 0

A 0

Command

A1

Booster Multiple

6times external 5times external 4times external 3times external 2times external

A2

A0

capacitors

connections

0

1

0

1

*

0

1

0

1

*

2-time

3-time

4-time

5-time

6-time

2-time

3-time

4-time

5-time

2-time

3-time

4-time

2-time

3-time

2-time

NJU6679

(q) Read Modify Write/End

This instruction sets the Read Modify Write controlling the page address increment. In this mode, the Column

Address only increments when execute the display data “Write” instruction; but no change when the display data

“Read” Instruction. This status is continued until the End instruction execution. When the End instruction is

executed, the Column Adddress goes back to the start address before the execution of this “Read Modify Write”

instruction. This function reduces the load of MPU for repeating display data change of the fixed area (ex. cursor

blink).

A 0

0

RD

1

W R

0

D 7

1

D 6

1

D 5

1

D 4

0

D 3

0

D 2

0

D 1

0

D 0

D

D 0 : Read Modify Write On

1 : End

Note) In this “Read Modify Write” mode, out of display dara “Read”/”Write”, any instructions except

“Column Address Set” can be executed.

- The Example of Read Modify Write Sequence

Page Address Set

Set to the Start

Address of Cursor

Display

Column Address Set

Read Modify Write

Dummy Read

Start the Read Modify Write

The data is ignored

Column Counter doesn't increase

Data Read

Column Counter

doesn't increase

Data inverse by MPU

Data Write

Column Counter increase

Dummy Read

Data Read

Data Write

Column Counter doesn't increase

Column Counter increase

Dummy Read

Data Read

Data Write

Column Counter doesn't increase

Column Counter increase

End

End the Read Modify Write

NO

Finish?

YES

NJU6679

(r) Reset

This instruction executes the following initialization.

The reset by the reset signal input to the RES terminal (hardware reset) is required when power turns on. This

reset instruction does not use instead of this hardware reset when power turns on.

Initialization

1

2

Set the Column Address Counter to 00H

Set the Display Start Line Register to 00H

Set the Page Address Register to page “0”

Set the EVR register to FFH

Set the Partial Display(1/128 duty)

Set the Bias select(1/12 Bias)

3

4

5

6

7

8

Set the Voltage Booster(6 times)

Set the n-line inverse register to 0H

The DD RAM is not affected by this initialization.

A 0

0

RD

1

W R

0

D 7

1

D 6

1

D 5

1

D 4

0

D 3

0

D 2

0

D 1

1

D 0

0

(s) Internal Power Supply ON/OFF

This instruction control ON and OFF for the internal Voltage Converter, Voltage Regulator and Voltage Follower

circuits. For the Booster circuits operation, the oscillation circuits must be in operation.

A 0

0

RD

1

W R

0

D 7

0

D 6

0

D 5

1

D 4

0

D 3

0

D 2

0

D 1

0

D 0

D

D 0 : Internal Power Supply Off

1 : Internal Power Supply On

The internal Power Supply must be Off when external power supply using.

*1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer

capacitors, VDD and VLCD.

Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the

(3-4) Fig.5)

NJU6679

(t) Driver Outputs ON/OFF

This instruction controlls ON/OFF of the LCD Driver Outputs.

A 0

0

RD

1

W R

0

D 7

0

D 6

0

D 5

1

D 4

0

D 3

0

D 2

0

D 1

1

D 0

D

D 0 : LCD driving waveform output Off

1 : LCD driving waveform output On

The NJU6679 implements low power LCD driving voltage generator circuit and requires the following Power Supply

ON/OFF sequence.

- LCD Driving Power Supply ON/OFF Sequences

The sequences below are required when the power supply turns ON/OFF.

For the power supply turning on operation after the power-save mode, refer the ”power save release sequence”

mentioned after.

Turn ON sequence

Turn OFF sequence

EVR Register Set

Display OFF

Internal Power Supply ON

Whole Display ON

or

External Power supply

ON

Internal Power Supply OFF

or

External Power Supply OFF

(Wait Time) *1

Driver Outputs OFF

Drivier Outputs ON

NJU6679 Power OFF

*1 The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5,

External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time correctly,

test by using the actual LCD module.

NJU6679

(u) Power Save (complex comand)

When Static Drive ON at the Display OFF status (inverse order also same), the internal circuits goes to the Power

Save Mode and the operating current is dramatically reduced, almost same as the standby current.

The internal status in the Power Save Mode is shown as follows;

1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation.

2: LCD driving is stopped. Segment and Common drivers output VDD level voltage.

3: The display data and the internal operating condition are remained and kept as just before enter the

Power Save Mode.

4: All the LCD driving bias voltage (V1 to V5) is fixed to the VDD level.

The power save and its release perform according to the following sequences.

Power Save Sequence

Display OFF

Power Save Release Sequence

(Static Drive ON)

Normal Display

Display ON

Static Drive ON

(Wait Time)

Driver Outputs OFF

Driver Outputs ON

The NJU6679 constantly spends the current without the execution of the Driver Outputs OFF instruction. The LCD drive

waveform is not output until the Driver Outputs ON instruction is executed.

*1 In the Power Save sequence, the Power Save Mode starts after the Static Drive ON command is executed.

*2 In the Power Save Release sequence, the Power Save Mode releases just after the Static Drive OFF instruction

execution. The Display ON instruction is allowed to execute at any time after the Static Drive OFF instruction

is completed.

*3 The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5,

External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time cor

rectly, test by using the actual LCD module.

*4 LCD driving waveform is output after the exection of the Driver Outputs ON instruction execution.

*5 In case of the external power supply operation, the external power supply should be turned off before the Power

Save Mode and connected to the VDD for fixing the voltage. In this time, VOUT terminal also should be made

codition like as disconection or connection to VSS

.

(v) ADC Select

This instruction determines the correspondence of Column in the DD RAM with the Segment Driver Outputs.

Segment Driver Output order is inversed when this instruction executes, therefore, the placement the NJU6679

against the LCD panel becomes easy.

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

1

D4

0

D3

0

D2

0

D1

0

D0

D

0

D 0 : Clockwise Output (Normal)

Segment Driver S

0

to S131

1 : Counterclockwise Output (Inverse) Segment Driver S131 to S

0

NJU6679

(3) Internal Power Supply

(3-1) 6-time voltage booster circuits

The 6-time voltage booster circuit outputs the negative Voltage(VDD Common) boosted 6 times of VDD-VSS from the

VOUT terminal with connecting the six capacitors between C and C , C , C

⁺and C ^-, C ^{+ -}, C ⁺and C ^{- +}and C ^{- +}and

^-, and VSS and VOUT. The boosting time is selected out of 2 times to 6 by the combination of changing the external

1

2

3

4

5

C

5

capacitors connection and “Booster Level Select” instruction. (refer (2-1)Instruction (p)Voltage Boost time select)

Voltage Booster circuits requires the clock signals from internal oscillation circuit or the external clock signal,

therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is

in operation.

The boosted voltage of VDD-VOUT must be 18V or less.

The boost voltage and the capacitor connection are shown below.

The boosted voltage and VDD,VSS

VDD=+3V

VSS=+0V

VOUT=-VDD=-3V

VOUT=-2VDD=-6V

VOUT=-3VDD=-9V

VOUT=-4VDD=-12V

VOUT=-5VDD=-15V

2-time voltage

3-time voltage

4-time voltage

5-time voltage

4-time voltage

6-time voltage

Example of the external capacitor connection to the voltage booster circuits

6-time voltage 5-time voltage

VSS

+

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

+

V

OUT

V

OUT

V

OUT

3-time voltage

SS

2-time voltage

V

VSS

+

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

+

V

OUT

V

OUT

NJU6679

(3-2)Voltage Adjust Circuits

The boosted voltage of VOUT outputs V5 for LCD driving through the voltage adjust circuits. The output voltage of V5

is adjusted by Ra and Rb within the range of |V5| < |VOUT|.

The output is calculated by the following formula(1).

VLCD = VDD-V5 = (1+Rb/Ra)VREG

(1)

The VREG voltage is a reference voltage generated by the built-in bleeder registance. VREG is adjustable by EVR

functions (see section 3-3).

For minor adjustment of V5, it is recommended that the Ra and Rb is composed of R2 as variable resistor and R1

and R3 as fixed resistors, constant should be connected to VDD terminal,VR and V5 ,as shown below.

V

DD

V

REG

Ra

R1

R2

VR

V

5

V

OUT

R3

Rb

Fig. 4

< Design example for R1, R2 and R3 /Reference >

·R1+R2+R3=6MW

(Determind by the current between VDD-V5)

·Variable voltage range by the R2. -7V to -11V (VLCD=VDD-V5 : 10V to 12V)

(Determind by the LCD electrical characteristics)

·VREG=3V

(In case of VDD=3V and EVR=FFh)

R1,R2 and R3 are calculated by above conditions and the fomula of (1) to below;

R1=1.5MW

R2=0.3MW

R3=4.2MW

Note) V5 voltage is generated referencing with VREG voltage beased on the supply voltage (VDD and VSS) as shown

in above figure. Therefore, VLCD (VDD-V5) is affected including the gain (Rb/Ra) by the fluctuation of VREG voltage

based on the supply voltage. The power supply voltage should be stabilized for V5 stable operation.

NJU6679

(3-3) Contrast Adjustment by the EVR function

The EVR selects the VREG voltage out of the following 201 conditions by setting 8-bit data into the EVR register. With

the EVR function, VREG is controlled, and the LCD display contrast is adjusted. The EVR controls the voltage of VREG

by instruction and changes the voltage of V5.

A step with EVR is set like table shown below.

37H to 4FH available for use. If keeping 3% precision, sets EVR over 4FH.

EVR register

(0,0,1,1,0,1,1,1)

VREG[V]

(100/300) x (VDD-VSS)

:

VLCD

Low

3FH

:

4FH

(0,1,0,0,1,1,1,1)

(124/300) x (VDD-VSS)

:

FDH

FEH

FFH

(1,1,1,1,1,1,0,1)

(1,1,1,1,1,1,1,0)

(1,1,1,1,1,1,1,1)

(298/300) x (VDD-VSS)

(299/300) x (VDD-VSS)

(300/300) x (VDD-VSS)

High

In use of the EVR function, the voltage adjustment circuit must turn on by the power supply instruction.

Adjustable range of the LCD driving voltage by EVR function

The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors

Ra and Rb.

[ Design example for the adjustable range / Reference ]

- Condition VDD=3.0V, VSS=0V

Ra=1MW, Rb=4MW ( Ra:Rb=1:4 )

The adjustable range and the step voltage are calculated as follows in the above condition.

In case of setting 4FH in the EVR register,

VLCD = ((Ra+Rb)/Ra)VREG

= (5/1) x [(124/300) x 3.0]

= 6.2V

In case of setting FFH in the EVR register,

VLCD = ((Ra+Rb)/Ra)VREG

= (5/1) x [(300/300) x 3.0]

= 15.0V

Min.4FH

6.2 - - - - - - - - - - - - - - - - - - -

50

Max.FFH

15.0 [V]

Adjustable Range

Step Voltagre

[mV]

* In case of VDD=3V

NJU6679

(3-4) LCD Driving Voltage Generation Circuits

The LCD driving bias voltage of V1,V2,V3,V4 are generated by dividing the V5 voltage with the internal bleeder

resistance and is supplied to the LCD driving circuits after the impedence conversion by the voltage follower.

As shown in Figure 5, five external capacitors are required to connect to each LCD driving voltage terminal for voltage

stabilization. The value of capacitors (C6 to C10) should be determined after the actual LCD panel display evaluation.

Using the internal Power Supply

Using the external Power Supply

VSS

C1+

+

C1

C1-

C2+

+

C2

C3

C4

C_OUT

C2-

C3+

+

C3-

C4+

C4-

C5+

C4-

C5+

+

C5

C5-

*2

VOUT

NJU6679

R3

V5

*1

R2

VR

R1

VDD

V1

C6

C7

+

V1

V2

V3

V4

V5

External

V2

V3

V4

V5

C8

C9

Voltage

Generator

C10

Reference set up valueVLCD=VDD-V5 = 10 to 12V

COUT

C1 to C4, C9

C5 to C8

R1

to 1uF

0.1 to 0.47uF

1.5MW

R2

0.3MW

R3

4.2MW

Fig.5

*1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR terminal.

*2 Following connection of VOUT is required when external power supply using.

When VSS > V5 --- VOUT=V5

When VSS < V5 --- VOUT=VSS

NJU6679

(4-4) Access to the Display Data RAM and Internal Register.

The NJU6679 transfers data to the CPU through the bus holder with the internal data bus.

In case of reading out the display data contents in the DD RAM, the data which was read in the first data read cycle

(= the dummy read ) is memorized in the bus holder. Then the data is read out to the system bus from the bus holder

in the next data read cycle. Also, In case that the MPU writes into DD RAM, the data is temporarily stored in the bus

holder and is then written into DD RAM by the next data write cycle.

Therefore, the limitation of the access to NJU6679 from MPU side is not access time (tACC,tDS) of Display Data RAM

and the cycle time becomes dominant. With this, speed-up of the data transfer with the MPU becomes possible. In

case of cycle time isn’t met, the MPU inserts NOP operation only and becomes an equivalent to an execution of wait

operation on the sutisfy condition in MPU.

When setting an address, the data of the specified address isn’t output immediately by the read operation after

setting an address, and the data of the specified address is output at the the 2nd data read operation. Therefore, the

dummy read is always necessary once after the address set and the write cycle. (See Fig. 7)

The exsample of Read Modify Write operaion is mentioned in (2-1)Instruction –(q)The sequence of Inverse Display.

Write Operation

MPU

WR

DATA

N

N+1

N+2

N+3

Internal

Timing

Bus holder

WR

N+1

N+2

N+3

N

Read Operation

MPU

WR

RD

N

n

n+1

DATA

N

Address Set N

Data Read n

Data Read n+1

Dummy Read

Internal

Timing

WR

RD

Column Address

Bus holder

N+1

N+2

n+1

N

n

n+2

N

Fig.7

(4-6) Chip Select

CS is the Chip Select terminal. In case of CS=”L”, the interface with MPU is available.

In case of CS=”H” (Chip is not selected), the terminals of D to D are high impedance and A0, RD, WR, D

(SCL) inputs are ignored. If the serial interface is selected when CS=”H”, the shift register and the counter for the

serial interface are reset.

However, the reset signal is always input and executed in any conditions of CS.

0

7

(SI) and

D

6

NJU6679

ABSOLUTE MAXIMUM RATINGS

P A R A M E T E R

(Ta=25°C)

SYMBOL

VDD

R A T I N G S

-0.3 to +5.0

UNIT

Supply Voltage (1)

V

Supply Voltage (2)

Supply Voltage (3)

Input Voltage

V5

V1 to V4

VIN

VDD-18.0 to VDD+0.3

V5 to VDD+0.3

V

-0.3 to VDD+0.3

-30 to +80

V

Operating Temperature

Topr

°C

-55 to +125 (Chip)

-55 to +100 (TCP)

Storage Temperature

Tstg

°C

VDD

VSS

VDD

V5

Note 1) All voltage values are specified as VSS=0V.

Note 2) The relation of VDD³ V1³ V2³ V3³ V4³ V5>VOUT;VDD>VSS³ VOUT must be maintained.

In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to

NJU6679 at the mean time of turning on VDD power supply or after turned on VDD

.

In use of the voltage boost circuit, the condition that the supply voltage: 18.0V³ VDD-VOUT is necessary.

Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed.

Using LSI within electrical characteristics is strongly recommended for normal operation.

Use beyond the erectric characteristics conditions will cause malfunction and poor reliability.

Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the

voltage converter.

NJU6679

ELECTRICAL CHARACTERISTICS (1)

(VDD=2.7V to 3.3V, VSS=0V, Ta=-30 to +80°C)

SYMBOL

VDD

Note

5

P A R A M E T E

C O N D I T I O N S

MIN.

2.4

TYP.

MAX.

3.6

UNIT

V

Operating Voltage(1)

V5

VDD-18.0

VDD-6.0

VDD-0.5VLCD

OperatingVoltage(2)

V

6

V1,V2 VLCD= VDD-V5

V3,V4

VDD

VDD-0.5VLCD

V5

High Level VIHC1 D0...D7,A0, CS,RES,RD,WR,SEL68,

P/S Terminals

0.8VDD

VSS

VDD

0.2VDD

VDD

V

Input

Voltage

Low Level

VILC1

High Level VOHC11 D0...D7

Terminals

IOH=-0.5mA

IOL= 0.5mA

0.8VDD

VSS

Output

Voltage

Low Level VOLC11

0.2VDD

All Input terminals

Input Leakage

ILIO

- 1.0

1.0

uA

Current

RON1

RON2

IDDQ

VLCD=15.0V

VLCD=8.0V

2.0

3.0

4.5

5

Ta=25°C

Driver On-resistance

Stand-by Current

Operating Current

kW

uA

7

during Power save Mode

0.05

40

8

9

IDD12 Display VLCD=15.0V

IDD21 Accessing f CYC=200kHz

A0,CS,RES,RD,WR,SEL68,

80

650

850

Input Terminal

Capacitance

P/S,T1,T2,D0...D7

CIN

10

39

pF

10

Ta=25°C

Oscillation Frequency

fOSC

31.7

46.3

kHz

Ta=25°C

Reset time

tR

RES Terminal

1.0

10

us

11

12

Reset "L" Level Pulse

Width

tRW

Output Volt.

VSS-Vout, 6-time voltage booster,

VDD=3V

VOUT1

RTRI

VDD-15.0V

VDD-14.5V

4000

V

VDD=3V;COUT=4.7uF

6-time voltage booster

On-resistance

2000

W

Adjustment

range of

LCD

Voltage Booster Circuit "OFF"

VOUT2

V5

VDD-18.0V

VDD-6.0V

V

Voltage

Booster

13

14

Driving Volt.

Voltage

Voltage Adjustment Circuit "OFF"

Follower

VDD=3V, VLCD=12V

COM/SEG Terminals Open

No Access

IOUT1

IOUT2

250

45

450

90

70

3

Operating

Current

uA

%

IOUT3

35

Display Checkered pattern

Voltage Reg.

VREG%

VDD=3V,Ta=25°C, VREG=4F to FFH

Note 5) Although the NJU6679 can operate in wide range of the operating voltage, it shall not be guaranteed in

a sudden voltage fluctuation during the access with MPU.

Note 6) The operating voltage when using external power supply.

Note 7) RON is the resistance values in supplying 0.1V voltage-difference beteen power supply terminals

(V1,V2,V3,V4) and each output terminals (common/ segment). This is specified within the range of

Operating Voltage(2).

Note 8,9) The value of after Driver Output On instruction execution.

Note 8,9) Refers to the current consumption of the IC itself; external power supply is used for the LCD driving. In

case of not use internal power supply circuit,meaning current of IC’s. LCD driving power supply are

external power supply.

Note 8) Applicable in case of not accessing to the MPU.

Note 9) The operating current when writing a vertical stripe pattern on the tcyc. Current consumption during the

access is approximately proportional to the access frequency. When not accessed, it consumpts only IDD01

Note 10) Apply to A0, D

0

-D

7

, RD,WR,CS,RES,SEL68,P/S,T

1

,T2 terminals.

NJU6679

Note 11) t

R

( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the RES

signal.

Note 12) Apply minimum pulse width of the RES signal. To reset, the “L” pulse over tRW shall be input. .

Note 13) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage.

Note 14) Each operating current shall be defined as being measured in the following condition.

Status

T2

Operating Condition

External Voltage

Supply

(Input Terminal)

SYMBOL

Internal

Oscillator

Voltage

Booster

Voltage

Adjustment

Voltage

Follower

T1

IOUT1

IOUT2

IOUT3

L

L/H

L

Validity

Invalidity

Validity

Invalidity

Validity

Unuse

H

Use(VOUT)

Use(VOUT,V5)

H

MEASUREMENT BLOCK DIAGRAM

:IOUT1

VR

V5

VDD

T1

T2

A

NJU6679

VOUT

VSS

C1-C2+ C2-C3+ C3-C4+ C4-C5+ C5-

C1+

+

:IOUT2

VR

V5

VDD

T1

T2

A

NJU6679

VOUT

C5+

C5-

VSS

C1-C2+ C2-C3+ C3-C4+ C4-

C1+

:IOUT3

VR

V5

VDD

T1

T2

A

NJU6679

VOUT

C1-C2+ C2-C3+ C3-C4+ C4-C5+ C5-

VSSC1+

NJU6679

BUS TIMING CHARACTERISTICS

- Read/Write operation sequence (80 Type MPU)

t

CYC8

A0,CS

t

AW8

t

AH8

tCCL

WR,RD

t

CCH

tDH8

t

DS8

D

(Write)

0

to D

7

t

f

tr

tACC

t

OH8

D

0

to D

7

(Read)

(VDD=2.4V to 3.6V,Ta=-30 to +80°C)

SYMBO-

L

CONDITION

P A R A M E T E R

MIN.

TYP.

MAX.

UNIT

Address Hold Time

Address Set Up Time

System Cycle WR

tAH8

tAW8

10

0

ns

A0,CS

Terminals

tCYC8 (W)

270

350

50

220

Time

RD

tCYC8 (R)

tCCL(W)

tCCL(R)

tCCH(W)

tCCH(R)

tDS8

WR,"L"

WR,RD

RD,"L" Terminals

200

220

150

35

Control

WR,"H"

Pulse Width

160

RD,"H"

Data Set Up Time

Data Hold Time

tDH8

15

D0 to D7

Terminals

RD Access Time

Output Disable Time

tACC8

120

50

CL=100pF

tOH8

0

CS, WR, RD,

A0, D0 to D7

Terminals

Rise Time, Fall Time

tr,tf

15

ns

Note 15) All timing based on 20% and 80% of VDD voltage level.

NJU6679

- Read/Write operation sequence (68 Type MPU)

t

CYC6

tEWL

E

t

AW6

t

EWH

t

f

R/W

t

r

t

AH6

A0,CS

tDH6

t

DS6

D

0

to D

7

(Write)

t

OH6

t

ACC6

D

0

to D

7

(Read)

(VDD=2.4V to 3.6V,Ta=-30 to +80°C)

SYMBOL

tAH6

CONDITION

P A R A M E T E R

MIN.

10

TYP.

MAX.

UNIT

ns

Address Hold Time

Address Set Up Time

System Cycle Time(W)

tAW6

0

A0,CS,R/W

Terminals

tCYC6(W)

tCYC6(R)

270

350

200

50

220

System Cycle Time(R)

Read"H"

tEWH

tEWL

Write"H"

Enable

E Terminal

Pulse Width

Read"L"

Write"L"

220

150

35

160

Data Set Up Time

Data Hold Time

Access Time

tDS6

tDH6

15

D0 to D7

Terminals

tACC6

tOH6

200

50

CL=100pF

Output Disable Time

0

A0, CS, R/W,

E, D0 to D7

Terminals

Rise Time, Fall Time

tr,tf

15

ns

Note 16) All timing are based on 20% and 80% of VDD voltage level.

Note 17) tCYC6 shows the cycle of the E signal in active CS.

NJU6679

- Write operation sequence (Serial Interface)

t

CSS

t

CSH

CS

A0

t

SAS

t

SAH

t

SCYC

t

SLW

SCL

SI

t

SHW

tSDS

t

SDH

t

f

t

r

(VDD=2.4V to 3.6V,Ta=-30 to +80°C)

P A R A M E T E R

SYMBOL

tSCYC

tSHW

tSLW

MIN.

60

TYP.

MAX.

CONDITION UNIT

Serial Clock cycle

SCL "H" pulse width

SCL "L" pulse width

Address Set Up Time

Address Hold Time

Data Set Up Time

Data Hold Time

ns

SCL

Terminal

30

tSAS

25

A0 Terminal

SI Terminal

CS Terminal

tSAH

150

25

tSDS

tSDH

10

tCSS

10

CS-SCL Time

tCSH

300

SCL, A0,

CS, SI

Rise Time, Fall Time

tr,tf

15

ns

Terminals

Note 18) All timing are based on 20% and 80% of VDD voltage level.

Note 19) When inputting an instruction continuously, keep 450nS as the cycle of SCL between the instructions as

follows

SCL 8th clock

SCL 1st clock

SCL

450 ns

SCL"L"pulse width

(Between the

Instruction N+1

Instruction N

instruction and next)

NJU6679

LCD DRIVING WAVEFORM

127

126

127

0 1 2 3 4 5

126

0

1

2

3

4

V_DD

FR

V

SS

V_DD

COM₀

V

1

COM

1

V

2

COM₀

V

3

COM

3

V

4

COM

V

5

6

V_DD

COM

7

V

1

V

2

COM₁

V

3

COM

8

V

4

COM

9

V

5

COM

10

COM

11

COM

12

COM

13

V_DD

COM

14

COM

15

V

1

V

2

COM₂

V

3

V

4

V

5

V_DD

V

1

V

2

SEG₀

V

3

V

4

V

5

V_DD

V

1

V

2

SEG₁

V

3

V

4

V

5

V₅

V₄

V

3

V₂

V₁

V

DD

COM₀-SEG₀

-

V₁

V₂

V₃

V₄

V₅

-

V

5

V

4

V

3

V₂

V₁

V

DD

COM₀-SEG₁

-

V₁

V₂

V₃

V₄

V₅

-

NJU6679

APPLICATION CIRCUIT

MPU Interface (examples)

The NJU6679 is connectable to 80-type MPU or 68-type. In use of Serial Interface, it is possible to be controlled by

the signal line with the more small being.

*:SEL68 terminal shall be connected to VDD or VSS

.

- 80 Type MPU

VDD

VCC

A0

SEL68

A1 to A7

IORQ

CS

Decoder

MPU

NJU6678

NJU6679

D0 to D7

RD

D0 to D7

RD

WR

P/S

RES

GND

VSS

RESET

- 68 Type MPU

VCC

VDD

A0

SEL68

A1 to A15

VMA

CS

Decoder

NJU6679

NJU6678

MPU

D0 to D7

E

R/W

RES

P/S

RES

GND

VSS

RESET

- Serial Interface

VCC

VDD

A0

SEL68

A1 to A7

CS

Decoder

VDD

OR GND

NJU6679

NJU6678

MPU

SI

Port1

Port2

SCL

P/S

RES

GND

VSS

RESET

NJU6679

LCD Panel Interface Example

LCD Panel

(128 x 132)

NJU6679

BOTTOM VIEW

CAUTION

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.


型号：	NJU6679BCH
厂家：	NEW JAPAN RADIO
描述：	Liquid Crystal Driver, 260-Segment, CMOS, BUMP, DIE-321 驱动接口集成电路
文件：	总45页 (文件大小：451K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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