NJU6854CJ_技术文档

NJU6854

132COMMON x 132RGB LCD DRIVER

FOR 65,536-COLOR STN DISPLAY

ꢀ GENERAL DESCRIPTION

PACKAGE

The NJU6854 is a 132COMMON x 132RGB LCD driver for

65,536-color STN display. It contains common drivers, RGB drivers, a

serial and a parallel MPU interface circuit, an internal LCD power supply,

grayscale palettes and 278,784-bit display data RAM. The segment

drivers for RGB (Red, Green, Blue) independently produce optimum 64

or 32 grayscales from a built-in grayscale palette, and the LSI achieves

65,536 colors (64x32x32).

In addition, the NJU6854 operates with a low voltage of 1.7V and a

low operating current, therefore it is ideally suited for battery-powered

handheld applications.

BUMP CHIP

ꢀ FEATURES

ꢁ

65,536-color STN LCD driver

Built-in LCD Drivers

Built-in Display Data RAM (DDRAM) : 278,784 bits for Graphic Display

Programmable Display Mode

: 132-common x 132RGB (396-segment drivers)

- 64 grayscales(Green)

- 32 grayscales(Red, Blue)

3 Areas Partial Display

8-/16-bit Parallel Interface Selectable

8-/16-bit Bus Length for Display Data Selectable

3-/4-line Serial Interface Selectable

Programmable Duty Ratio and Bias Ratio

Programmable Internal Voltage Booster : Maximum 6 times

Programmable Contrast Control

Various Useful Instructions

Low Operating Current

Low Logic Voltage

ꢁ

: 128-step Electronic Volume Register (EVR)

: 1.7V to 3.3V

: 5.0V to 18.0V

Wide LCD Voltage Range

C-MOS Technology

Slim Chip for COG

Package

: Bump Chip

Ver.2004-06-29

- 1 -

NJU6854

TABLE OF CONTENTS

ꢀ

GENERAL DESCRIPTION

PACKAGE........................................................................................... 1

FEATURES ................................................................................................................................................... 1

PAD LOCATION............................................................................................................................................ 4

PAD COORDINATES.................................................................................................................................... 6

BLOCK DIAGRAM ..................................................................................................................................... 12

LCD POWER SUPPLY BLOCK DIAGRAM............................................................................................... 13

TERMINAL DESCRIPTION........................................................................................................................ 14

FUNCTIONAL DESCRIPTION ................................................................................................................... 17

(1) MPU INTERFACE.................................................................................................................................... 17

(1-1) Selection of Parallel/Serial Interface Mode....................................................................................................................17

(1-2) Selection of MPU Mode.................................................................................................................................................17

(1-3) Data Recognition...........................................................................................................................................................17

(1-4) Selection of 3-/4-line Serial Interface Mode...................................................................................................................17

(1-5) 4-line Serial Interface Mode...........................................................................................................................................17

(1-6) 3-line Serial Interface Mode...........................................................................................................................................18

(1-7) Data Write......................................................................................................................................................................19

(1-8) Data Read .....................................................................................................................................................................21

(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) ..........................................................................................22

(2) INITIAL DISPLAY LINE............................................................................................................................ 22

(3) DDRAM.................................................................................................................................................... 23

(3-1) DDRAM Address Range................................................................................................................................................23

(3-2) Window Area for DDRAM Access..................................................................................................................................23

(3-3) DDRAM Access Direction..............................................................................................................................................24

(3-4) Segment Shift Direction.................................................................................................................................................26

(3-5) Block Diagram of DDRAM and Peripheral Circuit..........................................................................................................26

(3-6) DDRAM Mapping...........................................................................................................................................................27

(3-6-1)

(REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "84H“ (1/132 Duty), FVC = "00H", HCT = “00H”,

SSC1 and SSC2 = “0”, EN3PTL = “0”................................................................................................................................27

(3-6-2)

(REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "70H“ (1/112 Duty), FVC = "00H", HCT = “0AH”,

SSC1 and SSC2 = “0”, EN3PTL = “0”................................................................................................................................28

(3-7) The Relationship among Bit Assignment, X address and Segment Driver ....................................................................29

(4) PWM CONTROL...................................................................................................................................... 36

(5) FRAME RATE CONTROL(FRC) ............................................................................................................. 36

(6) DISPLAY TIMING GENERATOR............................................................................................................. 36

(7) DATA LATCH CIRCUIT............................................................................................................................ 36

(8) COMMON DRIVERS AND SEGMENT DRIVERS .................................................................................. 37

(9) OSCILLATOR........................................................................................................................................... 38

(10) LCD POWER SUPPLY............................................................................................................................ 38

(10-1) Voltage Booster ...........................................................................................................................................................39

(10-2) Electrical Volume Register (EVR)................................................................................................................................39

(10-3) Voltage Converter........................................................................................................................................................40

(10-3-1) Voltage Regulator .............................................................................................................................................40

(10-3-2) Reference Voltage Generator...........................................................................................................................41

(10-3-3) LCD Bias Voltage Generator.............................................................................................................................41

(10-4) External Components for LCD Power Supply..............................................................................................................42

(10-5) Power ON/OFF............................................................................................................................................................45

(10-6) Discharge Circuit.........................................................................................................................................................45

(10-7) Reset Function ............................................................................................................................................................46

(11) INSTRUCTION TABLES.......................................................................................................................... 47

(12) INSTRUCTION DESCRIPTIONS............................................................................................................ 51

(12-1) 8-bit Access Mode .......................................................................................................................................................51

(12-1-1) Instruction Register...........................................................................................................................................51

Ver.2004-06-29

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NJU6854

(12-1-2) Auto-increment of Instruction Register Address................................................................................................52

(12-2) 16-bit Access Mode .....................................................................................................................................................53

(12-2-1) Instruction Register...........................................................................................................................................53

(12-2-2) Auto Increment of Instruction Register Address................................................................................................53

(12-3) Oscillation Control .......................................................................................................................................................54

(12-4) Display Data Assignment/ Window Area ONOFF/Increment Control...........................................................................54

(12-5) Display Line Number ...................................................................................................................................................55

(12-6) Blank Line Number......................................................................................................................................................55

(12-7) X Address....................................................................................................................................................................56

(12-8) Y Address ....................................................................................................................................................................56

(12-9) Window End X Address...............................................................................................................................................56

(12-10) Window End Y Address .............................................................................................................................................56

(12-11) Display Mode/Grayscale Mode..................................................................................................................................56

(12-12) Oscillating Frequency Adjustment/Frequency Dividing..............................................................................................60

(12-13) Header COM .............................................................................................................................................................61

(12-14) Initial Display Line......................................................................................................................................................61

(12-15) Scan Start COM 1......................................................................................................................................................62

(12-16) Scan Start COM 2......................................................................................................................................................62

(12-17) Line Number of Partial Display 1...............................................................................................................................62

(12-18) Line Number of Partial Display 2...............................................................................................................................62

(12-19) N-Line Inversion ........................................................................................................................................................62

(12-20) Power Control 1.........................................................................................................................................................63

(12-21) Electronic Volume Control .........................................................................................................................................64

(12-22) Display Timing Signal Monitor/PBX Palette...............................................................................................................64

(12-23) Power Control 2.........................................................................................................................................................65

(12-24) Booster Level/Amplifier Gain.....................................................................................................................................66

(12-25) Voltage Booster Clock ...............................................................................................................................................67

(12-26) Display Control..........................................................................................................................................................68

(12-27) PWM Control.............................................................................................................................................................69

(12-28) Three Partial Display Areas/ LED Driver Control/REV Bit..........................................................................................70

(12-29) Discharge ON/OFF....................................................................................................................................................72

(12-30) LED Driver Data ........................................................................................................................................................72

(12-31) Instruction Table/Address ..........................................................................................................................................72

(12-32) Scan Start COM 3......................................................................................................................................................73

(12-33) Line Number of Partial Display 3...............................................................................................................................73

(12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31) ..........................................................................................74

(13) PARTIAL DISPLAY FUNCTION............................................................................................................... 89

(14) RELATIONSHIP BETWEEN LOGICAL COM NUMBER AND PHYSICAL COMMON DRIVER............. 90

(15) TYPICAL INSTRUCTION SEQUENCES ................................................................................................ 95

ABSOLUTE MAXIMUM RATINGS............................................................................................................. 98

RECOMMENDED OPERATING CONDITIONS......................................................................................... 98

DC CHARACTERISTICS............................................................................................................................ 99

AC CHARACTERISTICS.......................................................................................................................... 101

(1) Write operation (80-type MPU).............................................................................................................. 101

(2) Read operation (80-type MPU).............................................................................................................. 102

(3) Write operation (68-type MPU).............................................................................................................. 103

(4) Read operation (68-type MPU).............................................................................................................. 104

(5) Serial interface....................................................................................................................................... 105

(6) Display control timing............................................................................................................................. 106

(7) Reset input timing.................................................................................................................................. 107

INPUT/OUTPUT BLOCK DIAGRAM ....................................................................................................... 108

MPU CONNECTIONS............................................................................................................................... 110

ꢀ

Ver.2004-06-29

- 3 -

NJU6854

ꢀ PAD LOCATION

DUMMY

COMB26

COMB27

COMB28

COMB29

COMB30

COMB31

COMB32

COMB59

COMB60

COMB61

COMB62

COMB63

COMB64

COMB65

DUMMY

SEGA0~SEGC131, COMA0~COMA25, COMB0~COMB25, DUMMY

23

COMA26~COMA65, COMB26~COMB65, DUMMY

140

23

15

CPU interface pads and other pads

50

15

115

180

245

15, 40, 65, 115, 120

Bump Material : Au (gold)

Ver.2004-06-29

- 4 -

NJU6854

DUMMY

COMA26

COMA27

COMA28

COMA29

COMA30

COMA31

COMA32

COMA59

COMA60

COMA61

COMA62

COMA63

COMA64

COMA65

DUMMY

Note 1) The pads with the same name are connected within the chip.

Note 2) Dummy pads are kept open..

UNIT: um

SIZE

ITEMS

Chip size

PAD pitch / space

(bump)

REMARK / PAD NO.

X

Y

2,180

With scribe lane (100 um)

Driver pads pitch

Interface pads

Driver sides

17,643

38

70~170

9

23

50

126

96

140

115

PAD open side

Interface sides

Driver sides

Interface sides

All pads

PAD size (bump)

BUMP height

17.5

ALIGN MARK DESIGN

pattern

forbidden

area

bump

metal only

bump

metal only

25

50

left bottom align mark

right bottom align mark

Coordinates LEFT BOTTOM : X= -8157.92 Y= -515.62

RIGHT BOTTOM : X= 8157.92 Y= -515.62

Ver.2004-06-29

- 5 -

NJU6854

ꢀ PAD COORDINATES

PAD

chip size 17,643×2,180 µm²( chip center = 0:0 )

PAD

No.

PAD

Pad name

X(µm)

Y(µm)

Pad name

X (µm)

Y (µm)

Pad name

X (µm) Y (µm)

No.

1

DUMMY

VSSH

LDAT

LSCK

LREQ

LRESb

TEST

SEL68

PS

-8620.0 -935.5

-8530.0 -935.5

-8465.0 -935.5

-8400.0 -935.5

-8335.0 -935.5

-8270.0 -935.5

-8205.0 -935.5

-8140.0 -935.5

-8075.0 -935.5

-8010.0 -935.5

-7945.0 -935.5

-7880.0 -935.5

-7815.0 -935.5

-7750.0 -935.5

-7685.0 -935.5

-7620.0 -935.5

-7555.0 -935.5

-7490.0 -935.5

-7375.0 -935.5

-7260.0 -935.5

-7145.0 -935.5

-7030.0 -935.5

-6915.0 -935.5

-6800.0 -935.5

-6685.0 -935.5

-6570.0 -935.5

-6455.0 -935.5

-6340.0 -935.5

-6225.0 -935.5

-6110.0 -935.5

-5995.0 -935.5

-5880.0 -935.5

-5765.0 -935.5

-5650.0 -935.5

-5535.0 -935.5

-5420.0 -935.5

-5305.0 -935.5

-5190.0 -935.5

-5075.0 -935.5

-4960.0 -935.5

-4845.0 -935.5

-4730.0 -935.5

-4615.0 -935.5

-4500.0 -935.5

-4385.0 -935.5

-4270.0 -935.5

-4155.0 -935.5

-4040.0 -935.5

-3925.0 -935.5

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

D15

LP

-3695.0 -935.5

-3580.0 -935.5

-3465.0 -935.5

-3350.0 -935.5

-3235.0 -935.5

-3120.0 -935.5

-3005.0 -935.5

-2940.0 -935.5

-2875.0 -935.5

-2810.0 -935.5

-2745.0 -935.5

-2680.0 -935.5

-2615.0 -935.5

-2525.0 -935.5

-2460.0 -935.5

-2395.0 -935.5

-2330.0 -935.5

-2265.0 -935.5

-2200.0 -935.5

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

VSSHA

VREG

VOUT

C1+

-20.0

45.0

-935.5

2

3

M

110.0

175.0

340.0

405.0

470.0

535.0

600.0

690.0

755.0

820.0

885.0

950.0

4

FLM

5

OSCO

OSCI

VSS

6

7

8

VSS

9

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

VSS

VDD

VEE

1015.0 -935.5

1105.0 -935.5

1170.0 -935.5

1235.0 -935.5

1300.0 -935.5

1365.0 -935.5

1430.0 -935.5

1520.0 -935.5

1585.0 -935.5

1650.0 -935.5

1715.0 -935.5

1780.0 -935.5

1845.0 -935.5

1935.0 -935.5

2000.0 -935.5

2065.0 -935.5

2130.0 -935.5

2195.0 -935.5

2260.0 -935.5

2350.0 -935.5

2415.0 -935.5

2480.0 -935.5

2545.0 -935.5

2610.0 -935.5

2675.0 -935.5

2765.0 -935.5

2830.0 -935.5

2895.0 -935.5

2960.0 -935.5

3025.0 -935.5

3090.0 -935.5

3180.0 -935.5

3245.0 -935.5

3310.0 -935.5

3375.0 -935.5

3440.0 -935.5

C1+

-2110.0

-935.5

C1+

VEE

-2045.0 -935.5

-1980.0 -935.5

-1915.0 -935.5

-1850.0 -935.5

-1785.0 -935.5

-1720.0 -935.5

-1655.0 -935.5

-1590.0 -935.5

-1525.0 -935.5

-1460.0 -935.5

-1395.0 -935.5

-1330.0 -935.5

-1265.0 -935.5

-1200.0 -935.5

C1+

VEE

C1-

VEE

C1-

VEE

C1-

VEE

C1-

VDDA

RESb

CSb

RS

WRb

RDb

VEE

C1-

VEE

C1-

VEE

C2+

VEE

C2+

VEE

C2+

VEE

C2+

VDDA

VSSA

D0

VEE

C2+

VEE

C2+

VEE

C2-

D1

VBA

-1110.0

-935.5

C2-

D2

VBA

-1045.0 -935.5

C2-

D3

VBA

-980.0

-915.0

-850.0

-760.0

-695.0

-630.0

-565.0

-500.0

-410.0

-345.0

-280.0

-215.0

-150.0

-85.0

-935.5

C2-

D4

VBA

C2-

D5

VBA

C2-

D6

VREF

VSSHA

C3+

D7

C3+

VDDA

VSSA

D8

C3+

D9

C3+

D10

C3-

D11

C3-

D12

C3-

D13

D14

C3-

-3810.0 -935.5 100

Ver.2004-06-29

- 6 -

NJU6854

chip size 17,643×2,180 µm2 (chip center = 0:0 )

PAD

No.

PAD

No.

PAD

Pad name

X(µm)

Y(µm)

Pad name

X (µm)

Y (µm)

Pad name

X (µm) Y (µm)

No.

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

C3-

C4+

C4-

C5+

C5-

V0

V1

V2

3505

3595

3660

3725

3790

3855

3920

4010

4075

4140

4205

4270

4335

4425

4490

4555

4620

4685

4750

4840

4905

4970

5035

5100

5165

5335

5400

5465

5530

5595

5660

5750

5815

5880

5945

6010

6075

6165

6230

6295

6360

6425

6490

6660

6725

6790

6855

6920

6985

7075

-935.5

V4

VSSH

7140

7205

7270

7335

7400

7490

7555

7620

7685

7750

7815

7880

7945

8010

8075

8140

8205

8270

8335

8400

8465

8530

8620

8652

-935.5

-794

-756

-718

-680

-642

-604

-566

-528

-490

-452

-414

-376

-338

-300

-262

-224

-186

COMA39

COMA38

COMA37

COMA36

COMA35

COMA34

COMA33

COMA32

COMA31

COMA30

COMA29

COMA28

COMA27

COMA26

DUMMY

COMA25

COMA24

COMA23

COMA22

COMA21

COMA20

COMA19

COMA18

COMA17

COMA16

COMA15

COMA14

COMA13

COMA12

COMA11

COMA10

COMA9

COMA8

COMA7

COMA6

COMA5

COMA4

COMA3

COMA2

COMA1

COMA0

DUMMY

SEGA0

8652

8607

8569

8531

8493

8455

8417

8379

8341

8303

8265

8227

8189

8151

8113

8075

8037

7999

7961

7923

7885

7847

7809

7771

7733

7695

7657

7619

7581

7543

7505

7467

7429

7391

7353

7315

232

270

308

346

384

422

460

498

536

574

612

650

688

726

764

920.5

VSSH

DUMMY

COMA65

COMA64

COMA63

COMA62

COMA61

COMA60

COMA59

COMA58

COMA57

COMA56

COMA55

COMA54

COMA53

COMA52

COMA51

COMA50

COMA49

COMA48

COMA47

COMA46

COMA45

COMA44

COMA43

COMA42

COMA41

COMA40

-148

-110

-72

-34

4

42

80

118

V2

V3

V4

SEGB0

SEGC0

SEGA1

SEGB1

156

194

SEGC1

Ver.2004-06-29

- 7 -

NJU6854

chip size 17,643×2,180 µm2 (chip center = 0:0 )

PAD

No.

PAD

Pad name

No.

X(µm)

Y(µm)

Pad name

X (µm)

Y (µm)

Pad name

X (µm) Y (µm)

No.

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

SEGA2

SEGB2

SEGC2

SEGA3

SEGB3

SEGC3

SEGA4

SEGB4

SEGC4

SEGA5

SEGB5

SEGC5

SEGA6

SEGB6

SEGC6

SEGA7

SEGB7

SEGC7

SEGA8

SEGB8

SEGC8

SEGA9

SEGB9

SEGC9

SEGA10

SEGB10

SEGC10

SEGA11

SEGB11

SEGC11

SEGA12

SEGB12

SEGC12

SEGA13

SEGB13

SEGC13

SEGA14

SEGB14

SEGC14

SEGA15

SEGB15

SEGC15

SEGA16

SEGB16

SEGC16

SEGA17

SEGB17

SEGC17

SEGA18

SEGB18

7277

7239

7201

7163

7125

7087

7049

7011

6973

6935

6897

6859

6821

6783

6745

6707

6669

6631

6593

6555

6517

6479

6441

6403

6365

6327

6289

6251

6213

6175

6137

6099

6061

6023

5985

5947

5909

5871

5833

5795

5757

5719

5681

5643

5605

5567

5529

5491

5453

5415

920.5

SEGC18

SEGA19

SEGB19

SEGC19

SEGA20

SEGB20

SEGC20

SEGA21

SEGB21

SEGC21

SEGA22

SEGB22

SEGC22

SEGA23

SEGB23

SEGC23

SEGA24

SEGB24

SEGC24

SEGA25

SEGB25

SEGC25

SEGA26

SEGB26

SEGC26

SEGA27

SEGB27

SEGC27

SEGA28

SEGB28

SEGC28

SEGA29

SEGB29

SEGC29

SEGA30

SEGB30

SEGC30

SEGA31

SEGB31

SEGC31

SEGA32

SEGB32

SEGC32

SEGA33

SEGB33

SEGC33

SEGA34

SEGB34

SEGC34

SEGA35

5377

5339

5301

5263

5225

5187

5149

5111

5073

5035

4997

4959

4921

4883

4845

4807

4769

4731

4693

4655

4617

4579

4541

4503

4465

4427

4389

4351

4313

4275

4237

4199

4161

4123

4085

4047

4009

3971

3933

3895

3857

3819

3781

3743

3705

3667

3629

3591

3553

3515

920.5

SEGB35

SEGC35

SEGA36

SEGB36

SEGC36

SEGA37

SEGB37

SEGC37

SEGA38

SEGB38

SEGC38

SEGA39

SEGB39

SEGC39

SEGA40

SEGB40

SEGC40

SEGA41

SEGB41

SEGC41

SEGA42

SEGB42

SEGC42

SEGA43

SEGB43

SEGC43

SEGA44

SEGB44

SEGC44

SEGA45

SEGB45

SEGC45

SEGA46

SEGB46

SEGC46

SEGA47

SEGB47

SEGC47

SEGA48

SEGB48

SEGC48

SEGA49

SEGB49

SEGC49

SEGA50

SEGB50

SEGC50

SEGA51

SEGB51

SEGC51

3477

3439

3401

3363

3325

3287

3249

3211

3173

3135

3097

3059

3021

2983

2945

2907

2869

2831

2793

2755

2717

2679

2641

2603

2565

2527

2489

2451

2413

2375

2337

2299

2261

2223

2185

2147

2109

2071

2033

1995

1957

1919

1881

1843

1805

1767

1729

1691

1653

1615

920.5

Ver.2004-06-29

- 8 -

NJU6854

chip size 17,643×2,180 µm2 (chip center = 0:0 )

PAD

No.

PAD

No.

PAD

Pad name

X(µm)

Y(µm)

Pad name X (µm)

Y (µm)

Pad name X (µm) Y (µm)

No.

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

SEGA52

SEGB52

SEGC52

SEGA53

SEGB53

SEGC53

SEGA54

SEGB54

SEGC54

SEGA55

SEGB55

SEGC55

SEGA56

SEGB56

SEGC56

SEGA57

SEGB57

SEGC57

SEGA58

SEGB58

SEGC58

SEGA59

SEGB59

SEGC59

SEGA60

SEGB60

SEGC60

SEGA61

SEGB61

SEGC61

SEGA62

SEGB62

SEGC62

SEGA63

SEGB63

SEGC63

SEGA64

SEGB64

SEGC64

SEGA65

SEGB65

SEGC65

SEGA66

SEGB66

SEGC66

SEGA67

SEGB67

SEGC67

SEGA68

SEGB68

1577

1539

1501

1463

1425

1387

1349

1311

1273

1235

1197

1159

1121

1083

1045

1007

969

931

893

855

817

779

741

703

665

627

589

551

513

475

437

399

361

323

285

247

209

171

133

95

920.5

SEGC68

SEGA69

SEGB69

SEGC69

SEGA70

SEGB70

SEGC70

SEGA71

SEGB71

SEGC71

SEGA72

SEGB72

SEGC72

SEGA73

SEGB73

SEGC73

SEGA74

SEGB74

SEGC74

SEGA75

SEGB75

SEGC75

SEGA76

SEGB76

SEGC76

SEGA77

SEGB77

SEGC77

SEGA78

SEGB78

SEGC78

SEGA79

SEGB79

SEGC79

SEGA80

SEGB80

SEGC80

SEGA81

SEGB81

SEGC81

SEGA82

SEGB82

SEGC82

SEGA83

SEGB83

SEGC83

SEGA84

SEGB84

SEGC84

SEGA85

-323

-361

-399

-437

-475

-513

-551

-589

-627

-665

-703

-741

-779

-817

-855

-893

-931

920.5

SEGB85

SEGC85

SEGA86

SEGB86

SEGC86

SEGA87

SEGB87

SEGC87

SEGA88

SEGB88

SEGC88

SEGA89

SEGB89

SEGC89

SEGA90

SEGB90

SEGC90

SEGA91

SEGB91

SEGC91

SEGA92

SEGB92

SEGC92

SEGA93

SEGB93

SEGC93

SEGA94

SEGB94

SEGC94

SEGA95

SEGB95

SEGC95

SEGA96

SEGB96

SEGC96

SEGA97

SEGB97

SEGC97

SEGA98

SEGB98

SEGC98

SEGA99

SEGB99

SEGC99

SEGA100

SEGB100

SEGC100

SEGA101

SEGB101

SEGC101

-2223

-2261

-2299

-2337

-2375

-2413

-2451

-2489

-2527

-2565

-2603

-2641

-2679

-2717

-2755

-2793

-2831

-2869

-2907

-2945

-2983

-3021

-3059

-3097

-3135

-3173

-3211

-3249

-3287

-3325

-3363

-3401

-3439

-3477

-3515

-3553

-3591

-3629

-3667

-3705

-3743

-3781

-3819

-3857

-3895

-3933

-3971

-4009

-4047

-4085

920.5

-969

-1007

-1045

-1083

-1121

-1159

-1197

-1235

-1273

-1311

-1349

-1387

-1425

-1463

-1501

-1539

-1577

-1615

-1653

-1691

-1729

-1767

-1805

-1843

-1881

-1919

-1957

-1995

-2033

-2071

-2109

-2147

-2185

57

19

-19

-57

-95

-133

-171

-209

-247

-285

Ver.2004-06-29

- 9 -

NJU6854

chip size 17,643×2,180 µm2 (chip center = 0:0 )

PAD

No.

PAD

Pad name

No.

X(µm)

Y(µm)

Pad name

X (µm)

Y (µm)

Pad name

X (µm) Y (µm)

No.

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

SEGA102

SEGB102

SEGC102

SEGA103

SEGB103

SEGC103

SEGA104

SEGB104

SEGC104

SEGA105

SEGB105

SEGC105

SEGA106

SEGB106

SEGC106

SEGA107

SEGB107

SEGC107

SEGA108

SEGB108

SEGC108

SEGA109

SEGB109

SEGC109

SEGA110

SEGB110

SEGC110

SEGA111

SEGB111

SEGC111

SEGA112

SEGB112

SEGC112

SEGA113

SEGB113

SEGC113

SEGA114

SEGB114

SEGC114

SEGA115

SEGB115

SEGC115

SEGA116

SEGB116

SEGC116

SEGA117

SEGB117

SEGC117

SEGA118

SEGB118

-4123

-4161

-4199

-4237

-4275

-4313

-4351

-4389

-4427

-4465

-4503

-4541

-4579

-4617

-4655

-4693

-4731

-4769

-4807

-4845

-4883

-4921

-4959

-4997

-5035

-5073

-5111

-5149

-5187

-5225

-5263

-5301

-5339

-5377

-5415

-5453

-5491

-5529

-5567

-5605

-5643

-5681

-5719

-5757

-5795

-5833

-5871

-5909

-5947

-5985

920.5

651

652

653

654

655

656

657

658

659

660

661

662

663

664

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

682

683

684

685

686

687

688

689

690

691

692

693

694

695

696

697

698

699

700

SEGC118

SEGA119

SEGB119

SEGC119

SEGA120

SEGB120

SEGC120

SEGA121

SEGB121

SEGC121

SEGA122

SEGB122

SEGC122

SEGA123

SEGB123

SEGC123

SEGA124

SEGB124

SEGC124

SEGA125

SEGB125

SEGC125

SEGA126

SEGB126

SEGC126

SEGA127

SEGB127

SEGC127

SEGA128

SEGB128

SEGC128

SEGA129

SEGB129

SEGC129

SEGA130

SEGB130

SEGC130

SEGA131

SEGB131

SEGC131

DUMMY

-6023

-6061

-6099

-6137

-6175

-6213

-6251

-6289

-6327

-6365

-6403

-6441

-6479

-6517

-6555

-6593

-6631

-6669

-6707

-6745

-6783

-6821

-6859

-6897

-6935

-6973

-7011

-7049

-7087

-7125

-7163

-7201

-7239

-7277

-7315

-7353

-7391

-7429

-7467

-7505

-7543

-7581

-7619

-7657

-7695

-7733

-7771

-7809

-7847

-7885

920.5

701

702

703

704

705

706

707

708

709

710

711

712

713

714

715

716

717

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

744

745

746

747

748

749

750

COMB8

COMB9

-7923

-7961

-7999

-8037

-8075

-8113

-8151

-8189

-8227

-8265

-8303

-8341

-8379

-8417

-8455

-8493

-8531

-8569

-8607

-8652

920.5

764

726

688

650

612

574

536

498

460

422

384

346

308

270

232

194

156

COMB10

COMB11

COMB12

COMB13

COMB14

COMB15

COMB16

COMB17

COMB18

COMB19

COMB20

COMB21

COMB22

COMB23

COMB24

COMB25

DUMMY

COMB26

COMB27

COMB28

COMB29

COMB30

COMB31

COMB32

COMB33

COMB34

COMB35

COMB36

COMB37

COMB38

COMB39

COMB40

COMB41

COMB42

COMB43

COMB44

COMB45

COMB46

COMB47

COMB48

COMB49

COMB50

COMB51

COMB52

COMB53

COMB54

COMB55

118

80

42

4

-34

-72

-110

-148

-186

-224

-262

-300

-338

-376

DUMMY

COMB0

COMB1

COMB2

COMB3

COMB4

COMB5

COMB6

COMB7

Ver.2004-06-29

- 10 -

NJU6854

chip size 17,643×2,180 µm2 (chip center = 0:0 )

PAD

No.

PAD

No.

PAD

Pad name

X(µm)

Y(µm)

Pad name

X (µm)

Y (µm)

Pad name

X (µm) Y (µm)

No.

751

752

753

754

755

756

757

758

759

760

761

COMB56

COMB57

COMB58

COMB59

COMB60

COMB61

COMB62

COMB63

COMB64

COMB65

DUMMY

-8652

-414

-452

-490

-528

-566

-604

-642

-680

-718

-756

-794

Ver.2004-06-29

- 11 -

NJU6854

ꢀ BLOCK DIAGRAM

VEE

VSS

VSSHA

Driver Power

Segment Driver

Common Driver

V0

V1

V2

V3

V4

LCD

Bias

132

396

Decoder

Driver Control

Grayscale Control Circuit

Data Latch Circuit

Voltage

Generator

Grayscale

Palettes

VOUT

C1+

C1-

Voltage

Booster

Display Data RAM

132RGB x 132

278.784bit

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

X address decoder

X address counter

X address register

Display

Control

RAM

Voltage

Regulator

Generator

VREG

VREF

VBA

Interface

Duty

Manager

LP

FLM

M

Display

Timing

Data manager

Generator

Instruction

Decoder

Register

Control

Bus Holder

Register

OSCI

Oscillator

Circuit

OSCO

TEST

VDD

MPU Interface

Bus I/O Buffer

VDDA

VSSA

VSS

Ver.2004-06-29

- 12 -

NJU6854

ꢀ LCD POWER SUPPLY BLOCK DIAGRAM

Temp Coefficient

Setting Register

VEE

+

VBA

-

LCD Bias

setting

register

BG

+

-

VREG

+

-

V0

V1

V2

V3

V4

VREF

+

-

+

-

This point is

1/2 VREG

+

-

+

-

VOUT

VREG

gain

Electric

C1+

C1-

setting

register

volume

Register

+

-

C2+

C2-

C3+

C3-

C4+

C4-

DC/DC

booster

Voltage

converter

step setting

register

C5+

C5-

VEE

Note) When external V_REFis used, keep Reference Voltage Circuit open (VGOFF=”0”, VBON=”0”).

Ver.2004-06-29

- 13 -

NJU6854

ꢀ TERMINAL DESCRIPTION

Power Supply

No.

Terminal

V_DD

I/O

Description

64-69

Power

Power Supply for Logic Circuits

V_DDAis internally connected to V_DDto fix SEL68 or P/S to “H” if necessary, and

cannot be used as main power supply.

26,32,42

V_DDA

Power

• V_DDAshould be open if not used

V_SSAis internally connected to V_SSto fix SEL68 or P/S to “L” if necessary, and

cannot be used as main GND.

33,43

57-63

V_SSA

V_SS

Power

• V_SSAshould be open if not used.

GND for logic circuits

95-104

V_SSHA

V_SSH

Power

GND for voltage converter circuits

206-222

GND for voltage booster

LCD Bias Voltages

V₀

V₁

V₂

V₃

V₄

• When the internal LCD power supply is used, internal LCD bias voltages (V₀-V₄)

are activated by the “Power Control” instruction. Stabilizing capacitors are required

176-205

Power/O

between each bias voltage and V_SS.

• When the external LCD power supply is used, LCD bias voltages are externally

supplied on V₀, V₁, V₂, V₃and V₄individually, with the following relation

maintained: V_SSH<V₄<V₃<V₂<V₁<V₀

C₁₊

C₁-

C₂₊

C₂-

C₃₊

C₃-

C₄₊

C₄-

C₅₊

C₅-

116-127

128-139

140-151

152-163

164-175

85-89

Power

Capacitor Connection for Voltage Booster

Reference-Voltage Generator Output

(typically 1.9V at 25℃, with temperature compensation function)

Voltage Booster Input

V_BA

70-84

V_EE

V_REF

V_REG

Power

• V_EEis normally connected to V_DD

.

90-94

Voltage Regulator Input

Voltage Regulator Output

105-109

• Connect this pin to V_SSwith a stabilizing capacitor

Voltage Booster Output

110-115

V_OUT

Power

• Connect this pin to V_SSwith a stabilizing capacitor

Ver.2004-06-29

- 14 -

NJU6854

MPU Interface

No.

Terminal

I/O

I

Description

Reset

• Active “L”

27

RESb

Parallel Interface

D0/SCL

D₇to D₀: 8-bit Bi-directional Bus(P/S=“H”)

D1/SDA

D2

Serial Interface

34-41

I/O

D3/SMODE

D4/SPOL

D5~D7

SDA: Serial Data

SCL: Shift Clock

SMODE: 3-/4-line Serial Mode Select

SPOL: RS Polarity Select (3-line Serial Interface Mode)

8-bit Bi-directional Bus

• In the 16-bit bus length mode, D₁₅-D₈are assigned to upper 8-bit data bus.

44-51

28

D8~D15

CSb

I/O

I

• In the serial interface mode or the 8-bit parallel interface mode, D₁₅-D₈should be

fixed to “H” or “L”.

Chip Select

• Active “L”

Register Select

• This signal interprets transferred data as display data or instruction.

29

31

RS

I

RS

H

L

Data

Instruction

Display Data

80-series MPU Interface (P/S=“H”, SEL68=“L”)

Data Read (RDb) Signal

• Active “L”

RDb(E)

68-series MPU Interface (P/S=“H”, SEL68=“H”)

Enable Signal

• Active “H”

80-series MPU Interface (P/S=“H”, SEL68=“L”)

Data Write (WRb) Signal

• Active “L”

68-series MPU Interface (P/S=“H”, SEL68=“H”)

Data Read or Write (R/W) Signal

WRb

30

24

I

(R/W)

R/W

H

L

Status

Read

Write

MPU Mode Select

SEL86

MPU

H

L

SEL68

68-series

80-series

Parallel/Serial Interface Mode Select

Display /

P/S Chip Select

Instruction

Read

/Write

Data

Serial Clock

25

23

PS

I

H

L

CSb

RS

D₀~ D₇

SDA (D₁)

RDb, WRb

Write Only

-

SCL (D₀)

In the serial interface mode (P/S=“L”), RDb, WRb, D₂and D₅-D₁₅should be fixed to

“H” or “L”,.

Maker test terminal

TEST

This terminal must be fixed to “H” in the user’s application.

Ver.2004-06-29

- 15 -

NJU6854

LCD Output

No.

Terminal

I/O

Description

Segment Drivers Output

REV Mode

Normal

Reverse

Turn-off

Turn-on

0

1

0

SEGA₀~

SEGA₁₃₁

SEGB₀~

SEGB₁₃₁

SEGC₀~

,

M signal

295-690

O

Display RAM Data

SEGC₁₃₁

Nomal mode

V2

V0

V2

V3

VSS

V3

Reverse mode

54

FLM

O

Normally open.

53

52

M

LP

Common Divers Output

Data

H

FR

Output level

H

L

V_SSH

V₁

COMA₀~

COMA₆₅

COMB₀~

COMB₆₅

L

225-292

O

H

V₀

V₄

L

Oscillator

56

OSCI

I

When using the internal resistor, connect OSCI to “L” and keep OSCO open

When using an external resistor, connect OSCI and OSCO with the external

55

OSCO

O

resistor, and if using external clock, input 50% duty signal into the OSCI.

White LED Driver Ports

19

20

21

22

LDAT

I/O

O

White LED control port: data input/output

White LED control port: shift clock output

White LED control port: data request output

White LED control port: reset output

LSCK

LREQ

LRESb

O

Ver.2004-06-29

- 16 -

NJU6854

ꢀ FUNCTIONAL DESCRIPTION

(1) MPU INTERFACE

(1-1) Selection of Parallel/Serial Interface Mode

The P/S selects a parallel or a serial interface mode, as shown in Table 1. In the serial interface mode, neither

display data in the DDRAM nor instruction data in the registers can be read out.

Table 1 Selection of Parallel/Serial Interface Mode

P/S

H

I/F Mode

Parallel I/F

Serial I/F

CSb

RS

RDb WRb

SEL68

-

SDA

SCL

Data

D₇-D₀(D₁₅-D₀)

-

L

-

NOTE) “ -” : Fix to “H” or “L”.

(1-2) Selection of MPU Mode

In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 2.

Table 2 Selection of MPU Mode

SEL68

MPU Mode

68-series MPU

80-series MPU

CSb

RS

RDb

E

WRb

R/W

Data

D₇-D₀(D₁₅-D₀)

H

L

RDb

WRb

(1-3) Data Recognition

In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the

combination of the RS, RDb and WRb (R/W) signals, as shown in Table 3.

Table 3 Data Recognition (Parallel Interface Mode)

68-series

80-series

RS

Function

R/W

H

RDb

L

WRb

H

L

H

Read Instruction

L

H

L

Write Instruction

Read Display Data

Write Display Data

H

L

H

L

H

(1-4) Selection of 3-/4-line Serial Interface Mode

In the serial interface mode, the SMODE selects 3- or 4-line serial interface mode, as shown in Table 4.

Table 4 Selection of 3-/4-line Serial Interface Mode

SMODE

Serial Interface Mode

H

L

3-line

4-line

(1-5) 4-line Serial Interface Mode

While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is inactive

(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.

8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D₇, D₆,…, and D₀, and converted

into 8-bit parallel data at the timing of the internal signal produced from the 8^thSCL signal. The data on the SDA is

interpreted as display data or instruction according to the RS.

Table 5 Data Recognition (4-line Serial Interface)

RS

H

Data Recognition

Instruction

L

Display Data

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NJU6854

Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface

is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)

temporary whenever 8-bit data transmission is completed. Fig 1 illustrates the interface timing of the 4-line serial

interface mode.

CSb

RS

VALID

D₀

SDA

D₇

D₆

D₅

D₄

D₃

D₂

D₁

SCL

1

2

3

4

5

6

7

8

Fig 1 4-line Serial Interface Timing

(1-6) 3-line Serial Interface Mode

While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is not active

(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.

9-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of RS, D₇, D₆,…, and D₀, and then

converted into 9-bit parallel data at the timing of the internal signal produced from the 9^thSCL signal. The data on the

SDA is interpreted as display data or instruction according to the combination of the RS bit and the SPOL status, as

follows.

Table 6 Data Recognition (3-line Serial Interface)

SPOL=L

SPOL=H

Data Recognition

Instruction

RS

0

Data Recognition

Display Data

Instruction

RS

0

1

Display Data

Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface

is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)

temporary whenever 9-bit data transmission is completed. Fig 2 illustrates the interface timing of the 3-line serial

interface mode.

CSb

SDA

SCL

RS

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

2

3

4

5

6

7

8

9

Fig 2 3-line Serial Interface Timing

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NJU6854

(1-7) Data Write

While the chip select is active (CSb=“L”), the data from MPU can be written into the DDRAM or the instruction

register. When the RS is “L”, the data is interpreted as display data which is stored in the DDRAM. The display data is

latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the

68-series MPU mode.

Table 7 Data Recognition

RS

L

Data Recognition

Display Data

Instruction

H

8-bit access to DDRAM

DATA0

DATA1

DATA2

DATA3

D0~D7

WRb

RS

Accessing to DDRAM

Accessing to Instruction Register

8-bit access to Instruction Register

MSB=0/Table Address

/Register Address

MSB=1/Table Address

/Counter Number

Data

1^stAccess

D0~D7

Data

1^stAccess

Datat₀

Datat

n-1

Datat₀

WRb

RS

Fig 3 Data Write Operations in 8-bit

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NJU6854

16-bit access to DDRAM

DATA0

DATA1

DATA2

DATA3

D8~D15

D0~D7

WRb

RS

Accessing to DDRAM

Accessing to Instruction Register

16-bit access to Instruction Register

MSB=0/Table

MSB=1/Table

Address/Counter

Number(n)

Address/Register Address/Register

Address

op code

DATA0

Address

D8~D15

DATA0

DATA1

DATAn-2

op code

invalid

op code

D0~D7

WRb

DATA0

RS

Fig 4 Data Write Operations in 16-bit

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(1-8) Data Read

Just after address setting or data write operation, make sure to conduct dummy read operation once. The reason lies

below, data from CPU is temporarily held in the built-in bus holder, and then released to the internal data bus, therefore a

dummy data will be read out by the 1^st“Display Data Read” instruction, the wanted data will be read out by the 2^nd

instruction.

Display Data Read in 8-bit

WRb

dummy read

D

~ D

7

0

op code

address set(AX,AY)

address= n

address= n+1

RDBb

RS

Display Data Read in 16-bit

WRb

dummy read

D

~ D

8

15

7

op code

n

n+1

n+2

D

~ D

0

n

n+1

n+2

data read

address set(AX,AY)

address=n

address = n address = n+1 address = n+2

RDb

RS

Instruction Data Read in 8-bit

WRb

1D_H

Set “ RA ” instruction

data

address

D0~D7

Table address

/register address

Data read

RDb

RS

Instruction Data Read in 16-bit

WRb

Data read

data

D

~ D

8

0

15

7

data

1 D

1 D_H

H

Set “ RA ” instruction

invalid

address

Table address

register address

address

/

RDb

RS

Fig 5 Data Read Operations

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(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode)

Either 8- or 16-bit bus length can be selected by the D₀(SWIF) bit of the CFG register.

SWIF = “0” : 8-bit bus

D₀

D₁

D₂

D₃

D₄

D₅

D₆

D₇Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

D₇D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅

SWIF = “1” : 16-bit bus

D₀D₁D₂D₃

Bit assignment is determined by the D₁(UDS) bit of the CFG register.

16-bit access

UDS = “0”

Internal BUS D₀D₁D₂D₃D₄D₅D₆D₇D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅

IO PAD

D₀D₁D₂D₃D₄D₅D₆D₇D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅

UDS = “1”

Internal BUS D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅D₀D₁D₂D₃D₄D₅D₆D₇

IO PAD D₀D₁D₂D₃D₄D₅D₆D₇D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅

8-bit access

UDS = “0”

Internal

D₀D₁D₂D₃D₄D₅D₆D₇D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅

BUS

D₀D₁D₂D₃D₄D₅D₆D₇D₀D₁D₂

D₀D₁D₂D₃D₄D₅D₆

D₃

D₇

D₄

D₅

D₆

D₇

IO PAD

1^st

access

IO PAD

2^nd

D₀D₁D₂D₃D₄D₅D₆

D₇

access

UDS = “1”

Internal BUS D₀D₁D₂D₃D₄D₅D₆D₇D₈D₉D₁₀D₁₁D₁₂D₁₃D₁₄D₁₅

D₀D₁D₂D₃D₄D₅D₆D₇D₀D₁D₂D₃D₄D₅D₆D₇

1^st

D₇

IO PAD

D₀D₁D₂D₃D₄D₅D₆

access

2^nd

D₀D₁D₂D₃D₄D₅D₆D₇

access

During 8-bit access, D15~D8 pins become high impedance, make sure fix them to H” or ”L”.

(2) INITIAL DISPLAY LINE

The Initial Display Line register(HST) specifies a DDRAM Y address, and display data corresponding to this

address will be displayed by the Scan Start COM 1.

The Y address specified by the Initial Display Line register is preset into the line counter whenever the FLM

becomes “H”. At the rising edge of the LP signal, the line counter is counted-up, then display data is latched into the data

latch circuit. At the falling edge of the LP signal, the latch data is released to the grayscale control circuit to decide a

grayscale level, then the segment drivers Ai, Bi and Ci (i=0 to 131) generate LCD waveforms.

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(3) DDRAM

(3-1) DDRAM Address Range

The DDRAM is capable of 132 bits for Y address and 2,112 bits (16-bit

x

132-segment) for X address. The x and

Y address are from 00_Hto 83 _H. Address setting outside these ranges is not allowed, otherwise it may cause malfunctions.

When auto-increment(auto-decrement) function is used during DDRAM access, Y address and/or X address will be

automatically increased(decreased). This operation is independent from line counter count-up (count-down).

X-address

0_H

83_H

16bit

0 _H

16bit

Y-address

83_H

16bit

(3-2) Window Area for DDRAM Access

Besides the normal DDRAM access discussed previously, it is possible to access only a specified window area by

using CFG, ADRH, ADRL, EADRH and EADRL registers to define a start point and an end point.

When auto-increment(auto-decrement) function enabled, Y address and/or X address will be automatically

increased(decreased) whenever DDRAM is accessed. And, the start point is specified by the X address Register (ADRH)

and Y address Register(ADRL), the end point by the Window End X address Register(EADRH) and Window End Y

address Register(EADRL). For the details, refer to the Instruction Table. The typical sequence of the window area setting

is listed below.

1. Set D₇(AIM1), D₆(AIM0), D₅(VWR), D₄(IDSY), D₃(IDSX), and D₂(WIN) bit of CFG register.

2. Set start point by ADRH and ADRL register.

3. Set end point by EADRH and EADRL register.

4. Window area is set up, and DDRAM can be accessed.

X Address

Start Point

(X, Y)

End Point

Window Area

(X, Y)

DDRAM Area

NOTE1) The following relationship should be maintained to avoid malfunctions.

- AX (Window Start X address) < EX (Window End X address) < Maximum X address

- AY (Window Start Y address) < EY (Window End Y address) < Maximum Y address

NOTE2)

Auto-increment in the window area

Start

End

Start

End

Ad d r e ss

Address

Column Address

NOTE3) When AIM[1:0]=(0,1), read-modify-write operation is valid.

Row Address

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(3-3) DDRAM Access Direction

Registers setting

DDDRAM Access Direction

Remark

00,00 01,00

83,00

00

X

00

X

0

1

00

0

1

0

1

0

1

0

1

0

1

0

1

0

(H) (H) (H) (H)

00,83

00,00

83,83

82,00 83,00

83

X

00

X

(H) (H) (H) (H)

00,83

00,00

83,83

83,00

00

X

83

X

(H) (H) (H) (H)

00,83 01,83

00,00

83,83

83,00

83

X

83

X

(H) (H) (H) (H)

00,83

82,83 83,83

Window Area

06,10 07,10

06,6A

7D,10

7D,6A

06 7D 10 6A

(H) (H) (H) (H)

06,10

06,6A

7C,10 7D,10

7D 06 10 6A

(H) (H) (H) (H)

7D,6A

06,10

7D,10

7D,6A

06 7D 6A 10

(H) (H) (H) (H)

06,6A 07,6A

06,10

06,6A

7D,10

7D 06 6A 10

(H) (H) (H) (H)

7C,6A 7D,6A

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Registers setting

DDDRAM Access Direction

Remark

00,00

00,01

83,00

83,83

00

X

00

X

0

1

00

0

1

0

1

0

1

0

1

0

1

0

1

(H) (H) (H) (H)

00,83

00,00

83,00

83,01

83

X

00

X

(H) (H) (H) (H)

00,83

00,00

83,83

83,00

00

X

83

X

(H) (H) (H) (H)

00,82

00,83

83,83

83,00

00,00

83

X

83

X

(H) (H) (H) (H)

83,82

83,83

00,83

Window Area

06,10

7D,10

7D,6A

06 7D 10 6A

(H) (H) (H) (H)

06,11

06,6A

06,10

06,6A

7D,10

7D,11

7D 06 10 6A

(H) (H) (H) (H)

7D,6A

06,10

7D,10

7D,6A

06 7D 6A 10

(H) (H) (H) (H)

06.69

06,6A

06,10

06,6A

7D,10

7D 06 6A 10

(H) (H) (H) (H)

7D,69

7D,6A

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(3-4) Segment Shift Direction

The DDRAM access direction can be selected through setting the D₇(REF) bit of the Display Control register

(DISPLAY), This function enables to reverse segment shift direction to reduce the restriction on the IC location on an

LCD module.

(3-5) Block Diagram of DDRAM and Peripheral Circuit

SEGMENT OUTPUT I/F

Grayscale Control Circuit

Internal Data Bus

Data Latch

REF,SWAP

Segment data

Data

write

Read

data

Display Data RAM

X-Address (00_H-83_H)

REF

X Address Counter

X Register

MPU I/F

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(3-6) DDRAM Mapping

(3-6-1) (REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "84H“ (1/132 Duty), FVC = "00H", HCT =

“00H”, SSC1 and SSC2 = “0”, EN3PTL = “0”

HST=00H

HST=05H

COM output

RAM Address

X address

----------

X=00H

X=83H

Y address

----------

COMA0

COMA1

COMA2

00H

01H

02H

03H

04H

05H

06H

07H

COMA63

COMA64

COMA65

COMB0

COMB1

COMB2

COMB3

3FH

40H

41H

42H

43H

44H

45H

46H

47H

48H

49H

----------

COMB63

COMB64

COMB65

81H

82H

83H

SEGA0

SEGB0

SEGC0

SEGA131

SEGB131

SEGC131

Segment Output

----------

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(3-6-2) (REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "70H“ (1/112 Duty), FVC = "00H", HCT =

“0AH”, SSC1 and SSC2 = “0”, EN3PTL = “0”

HST=00H

HST=05H

COM output

RAM Address

X address

----------

X=00H

X=83H

Y address

----------

COMA0

COMA1

COMA2

COMA3

COMA4

COMA5

COMA6

COMA7

COMA8

COMA9

COMA10

COMA11

COMA12

00H

01H

02H

03H

04H

05H

06H

07H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

COMA63

COMA64

COMA65

COMB0

COMB1

COMB2

COMB3

COMB4

COMB5

COMB6

COMB7

COMB8

COMB9

COMB10

COMB11

COMB12

----------

6DH

6EH

6FH

70H

71H

72H

73H

74H

75H

76H

77H

78H

79H

7AH

7BH

7CH

7DH

7EH

7FH

80H

81H

82H

83H

COMB63

COMB64

COMB65

SEGA0

SEGB0

SEGC0

SEGA131

SEGB131

SEGC131

Segment Output

----------

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(3-7) The Relationship among Bit Assignment, X address and Segment Driver

Three sub pixels(R, G, B) individually driven by 3 segment drivers (SEGAi, SEGBi, SEGCi) consist one pixel of

the color STN panel. In the 65k display mode, 5-bit display data for SEGAi and SEGCi can output 32-level grayscale

respectively, and 6-bit display data for SEGBi can output 64-level grayscale, so the total quantity of possible colors is

65,536(32x32x64). In 4k-color mode, 4-bit display data for every SEGAi, SEGBi and SEGCi, so the total quantity of

possible colors is 4,096(16x16x16).

Weighting value of display data is dependent on the status of the SWAP bit and the REF bit of DISPLAY register.

16-bit Bus Access (65k-color Mode)

(REF,SWAP)=(0,0) or (1,1)

MODED = 0 (65,536 color display)

SEGCi

SEGBi

SEGAi

i = 0 to 131

Grayscale Palette

j = 0 to 31

Palette Cj

Palette Bj

Palette Aj

Grayscale control

PWMM[1:0]=00 for 64 level

PWMM[1:0]=01 for 32 level

PWMM[1:0]=11 for 128 level

PWM control

+ 2 FRC

PWM control

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Display data

MSB

LSB

MPU Write Data

X Address : nH

Note Internal Access X Address : nH (REF = 0)

:83H - nH (REF = 1)

MODE[1:0] = 00

(REF,SWAP)=(0,1) or (1,0)

MODED = 0 (65,536 color display)

SEGCi

SEGBi

SEGAi

i = 0 to 131

Grayscale Palette

j = 0 to 31

Palette Aj

Palette Bj

Palette Cj

Grayscale control

PWMM[1:0]=00 for 64 level

PWMM[1:0]=01 for 32 level

PWMM[1:0]=11 for 128 level

PWM control

+ 2 FRC

PWM control

Display data

D4 D3 D2 D1 D0 D10 D9 D8 D7 D6 D5 D15 D14 D13 D12 D11

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

MPU Write Data

X Address : nH

Note Internal Access X Address : nH (REF= 0)

:83H - nH (REF= 1)

MODE[1:0] = 00

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NJU6854

16-bit Bus Access (4k-color Mode 1)

(REF,SWAP)=(0,0) or (1,1)

MODED = 1 (4,096 color display)

SEGCi

SEGBi

SEGAi

i = 0 to 131

Grayscale Palette

j = 1, 3, 5 ... 29, 31

Palette Cj

Palette Bj

Palette Aj

Grayscale control

PWMM[1:0]=00 for 64 level

PWMM[1:0]=01 for 32 level

PWMM[1:0]=10 for 16 level

PWMM[1:0]=11 for 128 level

PWM

control

Display data

D15 D14 D13 D12

D10 D9 D8 D7

D4 D3 D2 D1

MSB

LSB

MPU Write Data

X Address : nH

Note Internal Access X Address : nH (REF = 0)

MODE[1:0] = 01

:83H - nH (REF = 1)

(REF,SWAP)=(0,1) or (1,0)

MODED = 1 (4,096 color display)

SEGCi

SEGBi

SEGAi

i = 0 to 131

Grayscale Palette

j = 1, 3, 5 ... 29, 31

Palette Aj

Palette Bj

Palette Cj

Grayscale control

PWMM[1:0]=00 for 64 level

PWMM[1:0]=01 for 32 level

PWMM[1:0]=10 for 16 level

PWMM[1:0]=11 for 128 level

PWM

control

Display data

D4 D3 D2 D1

D15 D14 D13 D12

D10 D9 D8 D7

D15 D14 D13 D12

D4 D3 D2 D1

MSB

LSB

MPU Write Data

X Address : nH

Note Internal Access X Address : nH (REF = 0)

:83H - nH (REF = 1)

MODE[1:0] = 01

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NJU6854

16-bit Bus Access (4k-color Mode 2)

(REF,SWAP)=(0,0) or (1,1)

MODED = 1 (4,096 color display)

SEGCi

SEGBi

SEGAi

i = 0 to 131

Grayscale Palette

j = 1, 3, 5 ... 29, 31

Palette Cj

Palette Bj

Palette Aj

Grayscale control

PWMM[1:0]=00 for 64 level

PWMM[1:0]=01 for 32 level

PWMM[1:0]=10 for 16 level

PWMM[1:0]=11 for 128 level

PWM

control

Display data

D11 D10 D9 D8

D7 D6 D5 D4

D3 D2 D1 D0

MSB

LSB

MPU Write Data

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X Address : nH

MODE[1:0] = 10

(upper 4 bit invalid)

Note Internal Access X Address : nH (REF = 0)

:83H - nH (REF = 1)

(REF,SWAP)=(0,1) or (1,0)

MODED = 1 (4,096 color display)

SEGCi

SEGBi

SEGAi

i = 0 to 131

Grayscale Palette

j = 1, 3, 5 ... 29, 31

Palette Aj

Palette Bj

Palette Cj

Grayscale control

PWMM[1:0]=00 for 64 level

PWMM[1:0]=01 for 32 level

PWMM[1:0]=10 for 16 level

PWMM[1:0]=11 for 128 level

PWM

control

D3 D2 D1 D0

D7 D6 D5 D4

D11 D10 D9 D8

Display data

MSB

LSB

MPU Write Data

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X Address : nH

MODE[1:0] = 10

upper 4 bit invalid

Note Internal Access X Address : nH (REF = 0)

:83H - nH (REF = 1)

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NJU6854

Relationship among Display Data, X address and Segment Drivers(16-bit Access Mode)

65k-color mode, MODE[1:0]=0_H

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

1

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

X = 83_H

0

1

Palette A

SEGA0

Palette B

SEGB0

Palette C

SEGC0

Palette A

Palette B

SEGB131

Palette C

SEGC131

SEGA131

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

X = 83_H

0

1

Palette C

SEGA0

Palette B

SEGB0

Palette A

SEGC0

Palette C

SEGA131

Palette B

SEGB131

Palette A

SEGC131

4k-color mode 1, MODE[1:0]=1_H

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

1

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette A

SEGA0

Palette B

SEGB0

Palette C

SEGC0

Palette A

Palette B

SEGB131

Palette C

SEGA131

SEGC131

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette C

SEGA0

Palette B

SEGB0

Palette A

SEGC0

Palette C

SEGA131

Palette B

SEGB131

Palette A

SEGC131

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NJU6854

4k-color mode, MODE[1:0]=2_H

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

1

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette A

SEGA0

Palette B

SEGB0

Palette C

SEGC0

Palette A

Palette B

SEGB131

Palette C

SEGC131

SEGA131

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette C

SEGA0

Palette B

SEGB0

Palette A

SEGC0

Palette C

SEGA131

Palette B

SEGB131

Palette A

SEGC131

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NJU6854

Relationship among Display Data, X address and Segment Drivers(8-bit Access Mode)

1^stwrite in data

2^ndwrite in data

D01 D11 D21 D31 D41 D51

D02 D12 D22 D32 D42 D52

D61 D71

D62 D72

65k-color mode, MODE[1:0]=0_H

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

1

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

X = 83_H

0

1

Palette A

SEGA0

Palette B

SEGB0

Palette C

SEGC0

Palette A

Palette B

SEGB131

Palette C

SEGC131

SEGA131

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

X = 83_H

0

1

Palette C

SEGA0

Palette B

SEGB0

Palette A

SEGC0

Palette C

SEGA131

Palette B

SEGB131

Palette A

SEGC131

4k-color mode, MODE[1:0]=1_H

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

1

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette A

SEGA0

Palette B

SEGB0

Palette C

SEGC0

Palette A

Palette B

SEGB131

Palette C

SEGA131

SEGC131

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette C

SEGA0

Palette B

SEGB0

Palette A

SEGC0

Palette C

SEGA131

Palette B

SEGB131

Palette A

SEGC131

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NJU6854

4k-color mode, MODE[1:0]=2_H

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

1

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette A

SEGA0

Palette B

SEGB0

Palette C

SEGC0

Palette A

Palette B

SEGB131

Palette C

SEGC131

SEGA131

IDSX

REF

SWAP

X Address / Display Data / Grayscale Palette / Segment Driver

0

1

0

1

0

00_H→83_H00_H←83_H

X = 00_H

X = 83_H

X = 00_H

83_H←00_H83_H→00_H

0

1

Palette C

SEGA0

Palette B

SEGB0

Palette A

SEGC0

Palette C

SEGA131

Palette B

SEGB131

Palette A

SEGC131

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NJU6854

(4) PWM CONTROL

There are three variable grayscale modes and one fixed grayscale mode for NJU6854.

In the 65k variable grayscale mode ((PWMM1,PWMM0)=(1,1)), every Aj, Bj and Cj(j=0-31) grayscale palette can

select one of 32 PWM values from 128 levels(0/127~127/127).

In the 4k mode, every Aj, Bj and Cj(j=0-31) grayscale palette can select one of 16 PWM values from 128 levels

(0/127~127/127).

Table 8 PWM and Grayscale mode

PWMM1 PWMM0

Grayscale Mode

Variable

Grayscale Display Mode

32 options from 64 levels

32 options from 32 levels

（

65k-color mode

）

, or 16 options

（

4k-color mode

）

0

1

0

1

0

1

（

）

（

Variable

Fixed

Variable

16 options from 16 levels

（4k-color mode

）

32 options from 128 levels 65k-color mode

（

）

, or 16 options

（

4k-color mode

）

(5) FRAME RATE CONTROL(FRC)

FRC (Frame Rate control) is the method which averages PWM value (grayscale level) by changing this value by the

frame. The FRC is used for the SEGBi (palette Bj) in combination with PWM control in the 65K mode, so that the

SEGBi can generate 64 grayscales (32 grayscales x 2) by total 6 bits data (5-bit PWM data and 1-bit FRC data).

(6) DISPLAY TIMING GENERATOR

The display timing generator generates timing clocks such as the LP (Latch Pulse), M (Frame Rate) and FLM (First

Line Maker) by dividing an oscillation frequency.

The LP is used for the line counter and the data latch circuit. At the rising edge of the LP signal, the line counter is

counted up, then display data is latched into the data latch circuit. At the falling edge of the LP signal, the latch data is

released to the grayscale control circuit, then segment drivers Ai, Bi and Ci (i=0~131) produce LCD driving waveforms.

The internal data-transmission timing between the DDRAM and segment drivers is completely independent of external

data-transmission timing, so that MPU makes access to the LSI without concern for the LSI’s internal operation.

The M toggles once every frame in the default status, and can be programmed to toggle once every N lines. And the

FLM is used to specify an initial display line, which is preset whenever the FLM becomes “H”.

(7) DATA LATCH CIRCUIT

The data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. The

display data in this circuit is updated in synchronization with the LP. The “Display ON/OFF” and “Reverse Display

ON/OFF” instructions control the data in this circuit, but does not change the data in the DDRAM.

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NJU6854

(8) COMMON DRIVERS AND SEGMENT DRIVERS

The LSI includes 132-common drivers and 396-segment drivers. The common drivers generate LCD driving

waveforms formed on the V₀, V₁, V₄and V_SSHlevels. The segment drivers generate waveforms formed on the V₀, V₂, V₃

and V_SSHlevels.

LP

COMA0

FLM

COMA1

M

COMA2

COMA0

COMA1

COMA2

SEGA

COMA0

COMA1

COMA2

SEGB

COMA0

COMA1

COMA2

SEGC

Fig 6 LCD Driving Waveforms (1/132Duty)

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NJU6854

(9) OSCILLATOR

The oscillator consists of a resistor and a capacitor, and generates internal clocks for the display timing generator

and the voltage booster. Through Oscillation Control register(CR), oscillating signal can be generated by using the

internal resistor or an external resistor. Besides, external clock can be used too.

If using the internal resistor, ground OSCI pin and keep OSCO pin open. Frequency can be adjusted or divided by

using Frequency Control register(MDIV). If using the external resistor, connect OSCI and OSCO with an resistor. If

using external clock, input 50% duty signal to the OSCI pin.

(10) LCD POWER SUPPLY

The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage

converter consists of the reference voltage generator with temperature compensation circuit, the voltage regulator with

EVR control and the LCD bias voltage generator. Furthermore the configuration of the LCD power supply can be

arranged by setting Power Control 1 register(TCBI) and Power Control 2 register (POW2). It is possible to use part of

the internal LCD power supply with an external supply, as shown in Table 17.

Table 9 Configuration of LCD Power Supply

Voltage Converter

Voltage

Reference Voltage

Generator

External Power Supply

Note

Voltage Regulator

(V_REGoutput)

LCD Bias

Generator

Booster

(V_BAoutput)

V

_OUT, V₀, V₁, V₂, V₃and V₄are

supplied

0

1

X

0

1

0

1

0

X

0

X

1

0

X

1

DISABLE

ENABLE

DISABLE

ENABLE

DISABLE

ENABLE

DISABLE

ENABLE

DISABLE

ENABLE

DISABLE

1

2

3

4

5

6

V_OUT, V_REFare supplied

V_OUT, V_REGare supplied

DISABLE

ENALBLE

ENABLE

V

_OUTis supplied

V_REFis supplied

V_REGis supplied

1

ENABLE

NOTE1) The LCD bias voltages are externally supplied, and C1±, C2±, C3±, C4±, C5±, V_REF, V_REGand V_EEare open.

NOTE2) The V_OUTand V_REFare externally supplied, and the C1±, C2±, C3±, C4±, C5± and V_EEare open.

NOTE3) The V_OUTand V_REGare externally supplied, and the C1±, C2±, C3±, C4±, C5± and V_EEare open.

NOTE4) The V_OUTis externally supplied, and the C1±, C2±, C3±, C4± and C5± are open.

NOTE5) The V_REFis externally supplied.

NOTE6) The V_REGis externally supplied

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NJU6854

(10-1) Voltage Booster

The internal voltage booster generates up to 6xV_EEvoltage. The boost level is selected from 2x~6x by setting the

Boost Level register(GVU). The boost voltage V_OUTmust not exceed 18.0V, otherwise the voltage stress may cause a

permanent damage to the LSI.

V_OUT=18.0V

V

_OUT=9V

V

_EE=3V

V

_EE=3V

V_SSH=0V

6-time boost

3-time boost

Fig 7 Boost Voltage

5-time Boost

6-time Boost

C₁₊

C₁-

C₁₊

C₁-

+

C₂₊

C₂-

C₂₊

C₂-

C₃₊

C₃-

C₃₊

C₃-

C₄₊

C₄-

C₄₊

C₄-

C₅₊

C₅-

C₅₊

C₅-

V_OUT

V_SSH

V_OUT

V_SSH

+

4-time Boost

3-time Boost

2-time Boost

C₁₊

C₁-

C₁₊

C₁-

C₁₊

C₁-

+

C₂₊

C₂-

C₂₊

C₂-

C₂₊

C₂-

C₃₊

C₃-

C₃₊

C₃-

C₃₊

C₃-

C₄₊

C₄-

C₄₊

C₄-

C₄₊

C₄-

C₅₊

C₅-

C₅₊

C₅-

C₅₊

C₅-

V_OUT

V_SSH

V_OUT

V_SSH

+

V_OUT

V_SSH

+

Fig 8 External Capacitor Connection of Voltage Booster

(10-2) Electrical Volume Register (EVR)

The EVR is used to fine-tune the V₀voltage to optimize display contrast. The EVR value is controlled in 128 steps

by setting the Electrical Volume register(EVOL).

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NJU6854

(10-3) Voltage Converter

(10-3-1) Voltage Regulator

The voltage regulator consists of an operational amplifier with gain control and EVR. The V_REFvoltage is

multiplied to obtain the V_REGvoltage, and gain control is set by the GSEL bit of the Boost Level register (GVU). When

GSEL=0, boost level is determined by VU₂~VU₀bits value. When GSEL=1, booster level is determined by RG₂~RG₀bit

value.

The relationship of V_REGand LCD driving voltage(V₀) is shown as below:

available V₀voltage range by control V_REGgain

18

16

14

Volt

H

EVR =7F

H

EVR =7F

V_REF=2.7V external reference

V_REF=1.9V internal reference

12

10

H

EVR =00

H

EVR =00

8

6

4

2

V_REG

gain

2 x

3 x

4 x

5 x

6 x 6.45 x 7 x 7.3 x 8.0 x

Fig 9 Relationship of V₀and V_REG

Table 10 V_REGgain

GSEL = ‘0’

GSEL = ‘1’

RG1

V_REGGain

Remark

VU2

0

VU1

0

VU0

0

RG2

RG0

-

2

default VU[2:0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

default RG[2:0]

0

1

4

1

0

5

1

0

1

6

6.45

7

7.3

8.0

-

1

0

1

-

V

_REGcan be calculated by the following equation:

V_REG= V_REF

x

N

(N: Boost Level)

Note) To stabilize the V_REG, connect a capacitor to the V_REGpin.

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NJU6854

(10-3-2) Reference Voltage Generator

The reference voltage generator outputs about 1.9V reference voltage. When using the internal LCD power supply,

connect the V_BAand the V_REF. When using an external LCD power supply, input external power into V_REFpin and keep

V

_BAopen.

The temperature compensating circuit is built in, compensation coefficient can be selected from the following

shown 4 levels by setting TCV1~TVC0 bits of Power Control 1 register(TCBI).

reference voltage

-0.24% /°C

-0.20% / °C

-0.13% / °C

1.9

-0.0% / C

30

Fig 10 Temperature Compensation

temperature

0

60

-30

Table 11 Temperature Coefficient Selection

TCV[1]

TCV[0]

V_BAOutput

0.0 % /°C

- 0.13 % /°C

- 0.20 % /°C

- 0.24 % /°C

Remark

Default setting

0

1

0

1

0

1

(10-3-3) LCD Bias Voltage Generator

The LCD bias voltage generator consists of buffer amplifiers and bleeder resistors, and the bias ratio can be selected

from1/5~1/12 through setting B2~B0 bits of Power Control 1 register(TCBI).

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NJU6854

(10-4) External Components for LCD Power Supply

Using External Power Supply

Only Using Internal Power Supply

DD

V

EE

V

DD

EE

V

BA

V

BA

V

3

CA

REF

V

REF

3

CA

SS

V

REG

V

REG

V

SS

V

1

C +

1

C +

1

CA

1

C -

1

C -

2

C +

2

C +

2

C -

2

C -

3

C +

3

C +

3

C -

3

C -

4

C +

4

C +

1

CA

4

C -

4

C -

5

C +

5

C +

1

5

C -

5

C -

1

CA

OUT

V

OUT

V

SS

V

2

CA

0

V

0

V

2

CA

1

2

1

2

1

2

External

power

circuit

3

4

3

4

3

4

V

Fig 11

Fig 12

Reference guide values of capacitor

CA

1

2

3

0.47 ~ 4.7 uF

0.47 ~ 2.2 uF

0~0.1uF

NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular

application.

NOTE2) Parasitic resistance on the power supply lines (V_DD, V_SS, V_EE, V_SSH, V_OUT, V₀, V₁, V₂, V₃and V₄) reduces step-up

efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this

impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.

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NJU6854

Using Internal Power Supply

without Reference Voltage

Generator(1)

Using Internal Power Supply

without Reference Voltage

Generator(2)

DD

EE

V

DD

EE

V

BA

V

BA

V

REF

V

3

CA

REF

V

3

CA

3

CA

REG

V

3

CA

REG

V

SS

V

SS

V

1

C +

1

CA

1

C +

1

C -

1

CA

1

C -

2

C +

2

C +

2

C -

2

C -

3

C +

3

C +

3

C -

3

C -

4

C +

1

CA

4

C +

4

C -

1

CA

4

C -

5

C +

1

5

C +

5

C -

1

5

C -

1

CA

OUT

V

1

CA

OUT

V

SS

V

2

CA

SS

V

0

V

2

CA

2

0

V

1

2

CA

1

2

3

4

3

4

SS

Fig 11

Fig 12

Reference guide values of capacitor

CA

1

2

3

0.47 ~ 4.7 uF

0.47 ~ 2.2 uF

0~0.1uF

NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular

application.

NOTE2) Parasitic resistance on the power supply lines (V_DD, V_SS, V_EE, V_SSH, V_OUT, V₀, V₁, V₂, V₃and V₄) reduces step-up

efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this

impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.

.

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NJU6854

Using Internal Power Supply

Without Voltage Booster

DD

V

EE

V

BA

V

REF

V

3

CA

REG

V

SS

V

1

C +

1

C -

2

C +

2

C -

3

C +

3

C -

4

C +

4

C -

5

C +

5

C -

External

power

OUT

V

circuit

2

CA

0

V

1

V

2

V

2

CA

2

CA

2

CA

3

4

2

CA

SS

V

Fig 15

Reference guide values of capacitor

CA

1

2

3

0.47 ~ 4.7 uF

0.47 ~ 2.2 uF

0~0.1uF

NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular

application.

NOTE2) Parasitic resistance on the power supply lines (V_DD, V_SS, V_EE, V_SSH, V_OUT, V₀, V₁, V₂, V₃and V₄) reduces step-up

efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this

impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.

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NJU6854

(10-5) Power ON/OFF

To protect the LSI from over current, the following sequences must be maintained to turn on and off the power

supply.

Using Internal LCD Power Supply

Power ON

First “V_DDand V_EEON”, next “Reset by RESb”, then “Internal LCD power supply ON”. Be sure to execute the

“Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be

turned on instantly.

Power OFF

First “Reset by RESb or “HALT” instruction”, next “V_DDand V_EEOFF”. If using different power sources for the

V_DDand the V_EE, the V_EEmust be turned off after the reset or the “HALT”. After that, the V_DDcan be turned off, waiting

until the LCD bias voltages (V₀~V₄) drop below the threshold level of LCD pixels.

Using External LCD Power Supply

Power ON

First “V_DDand V_EEON”, next “Reset by RESb”, then “External LCD power supply ON”. When using only external

V_OUT, first “V_DDON”, next “Reset by RESb”, then “External V_OUTON”, as well.

Power OFF

First “Reset by RESb or “HALT” instruction” to isolate external LCD bias voltages, next “V_DDOFF”. For more

safety, placing a resistor in series on the V₀line (or the V_OUTline in using only the external V_OUT) is recommended. That

resistance is usually between 50Ω and 100Ω.

V_DD, V_EE

Fig 16 Rising Time of the Power Supply

Item

tr

Recommended Rising Time

Applicable Power

V_DD, V_EE

30 ㎲ ~ 100 ㎳

Note : The rising time is the time from 10% V_DDto 90%V_EE

(10-6) Discharge Circuit

The LSI incorporates two independently discharge circuits for the capacitors connected to V_OUTand V₁-V₄. When

setting DSI1 bit of Discharge ON/OFF register (DISC) to “1”, or executing reset instruction, the capacitors on V₁-V₄are

discharged, by the same way, setting DSI2 to “1” or resetting, the capacitor on V_OUTis discharged.

Be sure to turn off the internal or external LCD power supply during discharging, otherwise discharge circuit will

function as a current load and increase operating current.

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NJU6854

(10-7) Reset Function

The reset function initializes the LSI to the following default status by setting the RESb to “L”. Usually connect the

RESb to MPU’s reset pin, so that the LSI and MPU are initialized simultaneously.

Table 12 Default Status

ITEM

Initial value

DDRAM

Undefined

00_H

Y address

X address

00_H

DDRAM access increment mode

Bus length

X/Y address increment ON

8bit

Initial display line

0_H(1^stline)

Display ON/OFF

OFF

Reverse display ON/OFF

Display clock monitor

Duty cycle ratio

OFF(Normal)

OFF

1/132

Vertical Blanking Area

n-line Inversion ON/OFF

Common scan direction

REF

0

OFF

COMA0 → COMA65 → COMB0 → COMB65

REF=0(Normal)

OFF(Normal)

(0, 0, 0, 0, 0, 0)

OFF

Swap

Electronic Volume Register(EVR)

Internal LCD Power Supply

Display mode

Variable grayscale mode(64 grayscales)

1/9 bias

Bias ratio

Colors Select

65,536 colors

Default value

Forward PWM

OFF(0)

Grayscale palette Aj[6:0]

Grayscale palette Bj[6:0]

Grayscale palette Cj[6:0]

Extra palette PCX[6:0]

PWM output mode

Discharge ON/OFF

Ver.2004-06-29

- 46 -

NJU6854

(11) INSTRUCTION TABLES

Table 0 [2:0] = 000_B

RA[3:0]

Name

CR

D7

D6

D5

D4

D3

D2

D1

D0

REMARK

0

1

0000

0001

*

CRF

CRS1

CRS0

OSC control

Display data Configuration

/Window Area ON/OFF

/Increment Control

CFG

AIM1

AIM0

VWR

IDSY

IDSX

WIN

UDS

SWIF

2

3

0010

0011

0100

0101

VPC

FVC

VPC7

*

VPC6

*

VPC5

*

VPC4

*

VPC3

FVC3

XA3

VPC2

FVC2

XA2

VPC1

FVC1

XA1

VPC0

FVC0

XA0

Display Line Number

Blank Line Number

4

ADRH

ADRL

XA7

XA6

XA5

XA4

DDRAM X address

5

YA7

YA6

YA5

YA4

YA3

YA2

YA1

YA0

DDRAM Y address

6

0110 EADRH

0111 EADRL

1000 COLOR

XEA7

YEA7

PWMM1

*

XEA6

YEA6

PWMM0

MDIV2

HCT6

HST6

SSC16

SSC26

PCC16

PCC26

XEA5

YEA5

*

XEA4

YEA4

MODE1

MDIV0

HCT4

HST4

SSC14

SSC24

PCC14

PCC24

XEA3

YEA3

MODE0

*

XEA2

YEA2

*

XEA1

YEA1

*

XEA0

YEA0

MODED

CRB0

HCT0

HST0

SSC10

SSC20

PCC10

PCC20

Window End X address

Window End Y address

Display Mode/Grayscale Mode

OSC Frequency control

Header COM

7

8

9

1001

1010

1011

1100

1101

1110

1111

MDIV

HCT

MDIV1

HCT5

HST5

SSC15

SSC25

PCC15

PCC25

CRB2

HCT2

HST2

SSC12

SSC22

PCC12

PCC22

CRB1

HCT1

HST1

SSC11

SSC21

PCC11

PCC21

10

11

12

13

14

15

*

HCT3

HST3

SSC13

SSC23

PCC13

PCC23

HST

HST7

SSC17

SSC27

PCC17

PCC27

Initial Display Line

SSC1

SSC2

PCC1

PCC2

Scan Start COM 1

Scan Start COM 2

Partial Display Line Number1

Partial Display Line Number 2

Table1 [2:0] = 001_B

RA[3:0] Name

D7

MC7

VGOFF

*

D6

MC6

VBON

EVOL6

*

D5

MC5

TCV1

EVOL5

*

D4

MC4

TCV0

EVOL4

GS

D3

MC3

*

D2

MC2

D1

MC1

D0

MC0

REMARK

N-line Inversion

Power Control 1

Electronic Volume

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

MC

TCBI

EVOL

PBX

B2

B1

B0

2

EVOL3

PBX3

*

EVOL2

PBX2

*

EVOL1

PBX1

*

EVOL0

PBX0

*

Display Timing Signal

3

MON

*

Monitor/Grayscale palette BX

4

*

N/A

5

POW2

GVU

*

CKCONT AMPON

HALT

VU2

DCON

VU1

RES

Power control 2

6

GSEL

BCKS

REF

*

RG2

BCKG

SWAP

*

RG1

*

RG0

*

VU0

Amplifier gain/ Booster Level

Booster clock

7

BCK

BCK3

SHIFT0

PWMB1

LED13

*

BCK2

TBC

BCK1

TEN

BCK0

ON/OFF

PWMA0

LED10

DIS1

8

DISPLAY

PWM

ECONT

DISC

EDATA

RA

*

SHIFT1

PWMC0

REV

Display control

9

PWMC1

ENLED

*

PWMB0

LED12

*

PWMA1

LED11

DIS2

PWM Mode control

3 Partial Display

10

11

12

13

14

15

TST0

*

EN3PTL

*

/ LED control / Rev

*

Discharge control

LED27

RSS

SSC37

PCC37

LED26

RA6

SSC36

PCC36

LED25

RA5

SSC35

PCC35

LED24

RA4

LED23

RA3

LED22

RA2

LED21

RA1

LED20

RA0

LED control signal

Setting Instruction Table

Scan Start COM 3

SSC3

PCC3

SSC34

PCC34

SSC33

PCC33

SSC32

PCC32

SSC31

PCC31

SSC30

PCC30

Partial Display Line Number3

Ver.2004-06-29

- 47 -

NJU6854

Table2 [2:0] = 010_B

RA[3:0]

Name

PA0

D7

*

D6

D5

PA05

PA15

PA25

PA35

PA45

PA55

PA65

PA75

PA85

PA95

PA105

PA115

PA125

PA135

PA145

PA155

D4

PA04

PA14

PA24

PA34

PA44

PA54

PA64

PA74

PA84

PA94

PA104

PA114

PA124

PA134

PA144

PA154

D3

PA03

PA13

PA23

PA33

PA43

PA53

PA63

PA73

PA83

PA93

PA103

PA113

PA123

PA133

PA143

PA153

D2

PA02

PA12

PA22

PA32

PA42

PA52

PA62

PA72

PA82

PA92

PA102

PA112

PA122

PA132

PA142

PA152

D1

PA01

PA11

D0

REMARK

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PA06

PA16

PA26

PA36

PA46

PA56

PA66

PA76

PA86

PA96

PA106

PA116

PA126

PA136

PA146

PA156

PA00

PA10

PA20

PA30

PA40

PA50

PA60

PA70

PA80

PA90

PA100

PA110

PA120

PA130

PA140

PA150

Grayscale palette A0 (0/31)

Grayscale palette A1 (1/31)

Grayscale palette A2 (2/31)

Grayscale palette A3 (3/31)

Grayscale palette A4 (4/31)

Grayscale palette A5 (5/31)

Grayscale palette A6 (6/31)

Grayscale palette A7 (7/31)

Grayscale palette A8 (8/31)

Grayscale palette A9 (9/31)

Grayscale palette A10 (10/31)

Grayscale palette A11 (11/31)

Grayscale palette A12 (12/31)

Grayscale palette A13 (13/31)

Grayscale palette A14 (14/31)

Grayscale palette A15 (15/31)

PA1

*

2

PA2

*

PA21

PA31

PA41

PA51

PA61

PA71

PA81

PA91

PA101

PA111

PA121

PA131

PA141

PA151

3

PA3

*

4

PA4

*

5

PA5

*

6

PA6

*

7

PA7

*

8

PA8

*

9

PA9

*

10

11

12

13

14

15

PA10

PA11

PA12

PA13

PA14

PA15

*

Table3 [2:0] = 011_B

RA[3:0]

Name

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

D7

*

D6

D5

D4

D3

D2

D1

D0

REMARK

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PA166

PA176

PA186

PA196

PA206

PA216

PA226

PA236

PA246

PA256

PA266

PA276

PA286

PA296

PA306

PA316

PA165

PA175

PA185

PA195

PA205

PA215

PA225

PA235

PA245

PA255

PA265

PA275

PA285

PA295

PA305

PA315

PA164

PA174

PA184

PA194

PA204

PA214

PA224

PA234

PA244

PA254

PA264

PA274

PA284

PA294

PA304

PA314

PA163

PA173

PA183

PA193

PA203

PA213

PA223

PA233

PA243

PA253

PA263

PA273

PA283

PA293

PA303

PA313

PA162

PA172

PA182

PA192

PA202

PA212

PA222

PA232

PA242

PA252

PA262

PA272

PA282

PA292

PA302

PA312

PA161

PA171

PA181

PA191

PA201

PA211

PA221

PA231

PA241

PA251

PA261

PA271

PA281

PA291

PA301

PA311

PA160

PA170

PA180

PA190

PA200

PA210

PA220

PA230

PA240

PA250

PA260

PA270

PA280

PA290

PA300

PA310

Grayscale palette A16 (16/31)

Grayscale palette A17 (17/31)

Grayscale palette A18 (18/31)

Grayscale palette A19 (19/31)

Grayscale palette A20 (20/31)

Grayscale palette A21 (21/31)

Grayscale palette A22 (22/31)

Grayscale palette A23 (23/31)

Grayscale palette A24 (24/31)

Grayscale palette A25 (25/31)

Grayscale palette A26 (26/31)

Grayscale palette A27 (27/31)

Grayscale palette A28 (28/31)

Grayscale palette A29 (29/31)

Grayscale palette A30 (30/31)

Grayscale palette A31 (31/31)

*

2

*

3

*

4

*

5

*

6

*

7

*

8

*

9

*

10

11

12

13

14

15

*

Ver.2004-06-29

- 48 -

NJU6854

Table4 [2:0] = 100_B

RA[3:0]

Name

PB0

D7

*

D6

D5

PB05

PB15

PB25

PB35

PB45

PB55

PB65

PB75

PB85

PB95

PB105

PB115

PB125

PB135

PB145

PB155

D4

PB04

PB14

PB24

PB34

PB44

PB54

PB64

PB74

PB84

PB94

PB104

PB114

PB124

PB134

PB144

PB154

D3

D2

D1

D0

REMARK

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PB06

PB16

PB26

PB36

PB46

PB56

PB66

PB76

PB86

PB96

PB106

PB116

PB126

PB136

PB146

PB156

PB03

PB13

PB23

PB33

PB43

PB53

PB63

PB73

PB83

PB93

PB103

PB113

PB123

PB133

PB143

PB153

PB02

PB12

PB22

PB32

PB42

PB52

PB62

PB72

PB82

PB92

PB102

PB112

PB122

PB132

PB142

PB152

PB01

PB11

PB00

PB10

PB20

PB30

PB40

PB50

PB60

PB70

PB80

PB90

PB100

PB110

PB120

PB130

PB140

PB150

Grayscale palette B0 (0/31)

Grayscale palette B1 (1/31)

Grayscale palette B2 (2/31)

Grayscale palette B3 (3/31)

Grayscale palette B4 (4/31)

Grayscale palette B5 (5/31)

Grayscale palette B6 (6/31)

Grayscale palette B7 (7/31)

Grayscale palette B8 (8/31)

Grayscale palette B9 (9/31)

Grayscale palette B10 (10/31)

Grayscale palette B11 (11/31)

Grayscale palette B12 (12/31)

Grayscale palette B13 (13/31)

Grayscale palette B14 (14/31)

Grayscale palette B15 (15/31)

PB1

*

2

PB2

*

PB21

PB31

PB41

PB51

PB61

PB71

PB81

PB91

PB101

PB111

PB121

PB131

PB141

PB151

3

PB3

*

4

PB4

*

5

PB5

*

6

PB6

*

7

PB7

*

8

PB8

*

9

PB9

*

10

11

12

13

14

15

PB10

PB11

PB12

PB13

PB14

PB15

*

Table5 [2:0] = 101_B

RA[3:0]

Name

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PB24

PB25

PB26

PB27

PB28

PB29

PB30

PB31

D7

*

D6

D5

D4

D3

D2

D1

D0

REMARK

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PB166

PB176

PB186

PB196

PB206

PB216

PB226

PB236

PB246

PB256

PB266

PB276

PB286

PB296

PB306

PB316

PB165

PB175

PB185

PB195

PB205

PB215

PB225

PB235

PB245

PB255

PB265

PB275

PB285

PB295

PB305

PB315

PB164

PB174

PB184

PB194

PB204

PB214

PB224

PB234

PB244

PB254

PB264

PB274

PB284

PB294

PB304

PB314

PB163

PB173

PB183

PB193

PB203

PB213

PB223

PB233

PB243

PB253

PB263

PB273

PB283

PB293

PB303

PB313

PB162

PB172

PB182

PB192

PB202

PB212

PB222

PB232

PB242

PB252

PB262

PB272

PB282

PB292

PB302

PB312

PB161

PB171

PB181

PB191

PB201

PB211

PB221

PB231

PB241

PB251

PB261

PB271

PB281

PB291

PB301

PB311

PB160

PB170

PB180

PB190

PB200

PB210

PB220

PB230

PB240

PB250

PB260

PB270

PB280

PB290

PB300

PB310

Grayscale palette B16 (16/31)

Grayscale palette B17 (17/31)

Grayscale palette B18 (18/31)

Grayscale palette B19 (19/31)

Grayscale palette B20 (20/31)

Grayscale palette B21 (21/31)

Grayscale palette B22 (22/31)

Grayscale palette B23 (23/31)

Grayscale palette B24 (24/31)

Grayscale palette B25 (25/31)

Grayscale palette B26 (26/31)

Grayscale palette B27 (27/31)

Grayscale palette B28 (28/31)

Grayscale palette B29 (29/31)

Grayscale palette B30 (30/31)

Grayscale palette B31 (31/31)

*

2

*

3

*

4

*

5

*

6

*

7

*

8

*

9

*

10

11

12

13

14

15

*

Ver.2004-06-29

- 49 -

NJU6854

Table6 [2:0] = 110_B

RA[3:0]

Name

PC0

D7

*

D6

D5

PC05

PC15

PC25

PC35

PC45

PC55

PC65

PC75

PC85

PC95

PC105

PC115

PC125

PC135

PC145

PC155

D4

D3

D2

D1

D0

REMARK

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PC06

PC16

PC26

PC36

PC46

PC56

PC66

PC76

PC86

PC96

PC106

PC116

PC126

PC136

PC146

PC156

PC04

PC14

PC24

PC34

PC44

PC54

PC64

PC74

PC84

PC94

PC104

PC114

PC124

PC134

PC144

PC154

PC03

PC13

PC23

PC33

PC43

PC53

PC63

PC73

PC83

PC93

PC103

PC113

PC123

PC133

PC143

PC153

PC02

PC12

PC22

PC32

PC42

PC52

PC62

PC72

PC82

PC92

PC102

PC112

PC122

PC132

PC142

PC152

PC01

PC11

PC00

PC10

PC20

PC30

PC40

PC50

PC60

PC70

PC80

PC90

PC100

PC110

PC120

PC130

PC140

PC150

Grayscale palette C0 (0/31)

Grayscale palette C1 (1/31)

Grayscale palette C2 (2/31)

Grayscale palette C3 (3/31)

Grayscale palette C4 (4/31)

Grayscale palette C5 (5/31)

Grayscale palette C6 (6/31)

Grayscale palette C7 (7/31)

Grayscale palette C8 (8/31)

Grayscale palette C9 (9/31)

Grayscale palette C10 (10/31)

Grayscale palette C11 (11/31)

Grayscale palette C12 (12/31)

Grayscale palette C13 (13/31)

Grayscale palette C14 (14/31)

Grayscale palette C15 (15/31)

PC1

*

2

PC2

*

PC21

PC31

PC41

PC51

PC61

PC71

PC81

PC91

PC101

PC111

PC121

PC131

PC141

PC151

3

PC3

*

4

PC4

*

5

PC5

*

6

PC6

*

7

PC7

*

8

PC8

*

9

PC9

*

10

11

12

13

14

15

PC10

PC11

PC12

PC13

PC14

PC15

*

Table7 [2:0] = 111_B

RA[3:0]

Name

PC16

PC17

PC18

PC19

PC20

PC21

PC22

PC23

PC24

PC25

PC26

PC27

PC28

PC29

PC30

PC31

D7

*

D6

D5

D4

D3

D2

D1

D0

REMARK

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PC166

PC176

PC186

PC196

PC206

PC216

PC226

PC236

PC246

PC256

PC266

PC276

PC286

PC296

PC306

PC316

PC165

PC175

PC185

PC195

PC205

PC215

PC225

PC235

PC245

PC255

PC265

PC275

PC285

PC295

PC305

PC315

PC164

PC174

PC184

PC194

PC204

PC214

PC224

PC234

PC244

PC254

PC264

PC274

PC284

PC294

PC304

PC314

PC163

PC173

PC183

PC193

PC203

PC213

PC223

PC233

PC243

PC253

PC263

PC273

PC283

PC293

PC303

PC313

PC162

PC172

PC182

PC192

PC202

PC212

PC222

PC232

PC242

PC252

PC262

PC272

PC282

PC292

PC302

PC312

PC161

PC171

PC181

PC191

PC201

PC211

PC221

PC231

PC241

PC251

PC261

PC271

PC281

PC291

PC301

PC311

PC160

PC170

PC180

PC190

PC200

PC210

PC220

PC230

PC240

PC250

PC260

PC270

PC280

PC290

PC300

PC310

Grayscale palette C16 (16/31)

Grayscale palette C17 (17/31)

Grayscale palette C18 (18/31)

Grayscale palette C19 (19/31)

Grayscale palette C20 (20/31)

Grayscale palette C21 (21/31)

Grayscale palette C22 (22/31)

Grayscale palette C23 (23/31)

Grayscale palette C24 (24/31)

Grayscale palette C25 (25/31)

Grayscale palette C26 (26/31)

Grayscale palette C27 (27/31)

Grayscale palette C28 (28/31)

Grayscale palette C29 (29/31)

Grayscale palette C30 (30/31)

Grayscale palette C31 (31/31)

*

2

*

3

*

4

*

5

*

6

*

7

*

8

*

9

*

10

11

12

13

14

15

*

Ver.2004-06-29

- 50 -

NJU6854

(12) INSTRUCTION DESCRIPTIONS

(12-1) 8-bit Access Mode

(12-1-1) Instruction Register

Set MSB bit of the 1^stbyte to “0”. Data to instruction register is transferred in 2 bytes, For the 1^stbyte, D6~D4 is

used to set the instruction table address, and D3~D0 to set instruction register address. The 2^ndbyte is instruction data.

MSB

0

LSB

Instruction Table Address Instruction Register Address 1^staccess

data

2^ndaccess

(Example) X, Y address of DDRAM

Step 1: 1^stbyte(X address)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

1

D1

0

D0

0

CSb

0

RS

1

RDb

1

WRb

0

Register address

0

Table address

Pins setting

Step 2: 2^ndbyte(X address)

D7

D6

D5

D4

D3

D2

D1

D0

CSb

0

RS

1

RDb

1

WRb

0

XA7

XA6

XA5

XA4

XA3

XA2

XA1

XA0

Step 3: 1^stbyte(Y address)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

1

D1

0

D0

1

CSb

0

RS

1

RDb

1

WRb

0

Table address

0

Register address

Pins setting

Step 4: 2^ndbyte(Y address).

D7

D6

D5

D4

D3

D2

D1

D0

CSb

0

RS

1

RDb

1

WRb

0

YA7

YA6

YA5

YA4

YA3

YA2

YA1

YA0

Ver.2004-06-29

- 51 -

NJU6854

(12-1-2) Auto-increment of Instruction Register Address

By setting MSB bit of the 1^stbyte to “1”, instruction data can be written to the registers successively. For the 1^st

byte, D6~D4 is used to set the instruction table address(Table[2:0]) and D3~D0 to set the count number for the registers,

from the 2^ndbyte, data will be automatically written to the successive registers.

MSB

1

LSB

Table address

Count number(n)

data of address 0

count 1

count 2

data of address 1

.

data of address n-1

count n

If the counter number is set as 0, data is written to the registers from the address 0 to 15.

(Example) Oscillator and others.

Step 1: 8bit auto increment / table address set / count number

D7

1

D6

0

D5

0

D4

0

D3

0

D2

1

D1

0

D0

1

CSb

0

RS

1

RDb

1

WRb

0

1

Pins setting

Table address

count number = 5

Step 2: 8bit auto increment / count = 1

D7

*

D6

*

D5

*

D4

*

D3

*

D2

D1

D0

CSb

0

RS

1

RDb

1

WRb

0

CRF

CRS1

CRS0

Step 3: 8 bit auto increment / count = 2

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

AIM1

AIM0

VWR

IDSY

IDSX

WIN

UDS

SWIF

0

1

0

Step 4: 8 bit auto increment / count = 3

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

VPC7

VPC6

VPC5

VPC4

VPC3

VPC2

VPC1

VPC0

0

1

0

Step 5: 8 bit auto increment / count = 4

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

*

FVC3

FVC2

FVC1

FVC0

0

1

0

Step 6: 8 bit auto increment / count = 5

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

XA7

XA6

XA5

XA4

XA3

XA2

XA1

XA0

0

1

0

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NJU6854

(12-2) 16-bit Access Mode

(12-2-1) Instruction Register

Set MSB bit to”0”. Instruction table number, instruction register address and instruction data will be transferred in

one 16-bit data. Instruction table number is determined by D14~D12, instruction register is determined by D11~D8, and

D7~D0 is instruction data.

MSB

0

LSB

Table address

Register address

Instruction data

(Example) X, Y address of DDRAM

Step 1: X address setting.

D15 D14 D13 D12 D11 D10

D9

0

D8

0

D7

D6

D5

D4

D3

D2

D1

D0

0

1

XA7 XA6 XA5 XA4 XA3 XA2 XA1 XA0

Table address

Register address

data

0

Step 1: Y address setting

D15

0

D14

0

D13

0

D12

0

D11

0

D10

1

D9

0

D8

1

D7

D6

D5

D4

D3

D2

D1

D0

YA7

YA6

YA5

YA4

YA3

YA2

YA1

YA0

Register address

data

0

Table address

(12-2-2) Auto Increment of Instruction Register Address

By setting MSB bit of the 1^stbyte to “1”, instruction data can be written to the registers successively. For the 1^st

byte, only upper 8-bit data is valid, D14~D12 is used to set the instruction table number(Table[2:0]) and D11~D8 to set

the count number of the registers. From the 2^ndbyte, data will be automatically written to the successive registers.

MSB

1

LSB

Count number(n)

Table address

data of address 0

data of address 1

data of address 2

data of address 3

..

.

..

.

data of address n-2

data of address n-1

If count number is 0, data is written to the registers from the address 0 to 15.

(Example) Oscillator and Configuration control

Step 1:

D15

1

D14

0

D13

0

D12

0

D11

0

D10

1

D9

0

D8

1

D7

*

D6

*

D5

*

D4

*

D3

*

D2

*

D1

*

D0

*

1

count number = 5

Table address

data (don’t care )

Step 2:

D15

*

D14

*

D13

*

D12

*

D11

*

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CRF

CRS1

CRS0

AIM1

AIM0

VWR

IDSY

IDSX

WIN

UDS

SWIF

Step 3:

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

VPC7

VPC6

VPC5

VPC4

VPC3

VPC2

VPC1

VPC0

*

FVC3

FVC2

FVC1

FVC0

Step 4:

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

XA7

XA6

XA5

XA4

XA3

XA2

XA1

XA0

*

(*: not applicable)

Ver.2004-06-29

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NJU6854

(12-3) Oscillation Control

Register : CR Table0 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

CRF

CRS1

CRS0

(default: {CRF, CRS1, CRS0} = 0_H, address: 0_H)

Setting Frequency

CRF

CRS1

CRS0

Function

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OSCI (730 kHz)

OSC2 (170 kHz)

OSC5 (external R, external source)

Invalid

OSC3 (1,200 kHz)

OSC4 (285 kHz)

Invalid

In OSC5 mode, connect the OSCI pin and the OSCO pin with a resistor, and input external clock signal to OSCI.

(12-4) Display Data Assignment/ Window Area ONOFF/Increment Control

Register: CFG / Table 0 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

AIM1

AIM0

VWR

IDSY

IDSX

WIN

UDS

SWIF

(default: {AIM1, AIM0, VWR, IDSY, ISDX, WIN, UDS, SWIF} = 0_H, address: 1_H)

(i) SWIF

SWIF

Bus length

0

1

8bit I/F (Initial Value)

16bit I/F

(ii) UDS

Assignment of MPU data on the DDRAM

16 Bit I/F Access

UDS = “0”: the lower 8-bit MPU data corresponding to the lower 8-bit display data

the upper 8-bit MPU data corresponding to the upper 8-bit display data

UDS = “1”: the lower 8-bit MPU data corresponding to the upper 8-bit display data

the upper 8-bit MPU data corresponding to the lower 8-bit display data

8 Bit I/F Access

UDS = “0”: 1^stMPU data corresponding to the lower 8-bit display data

2^ndMPU data corresponding to the upper 8-bit display data

UDS = “1”: 1^stMPU data corresponding to the upper 8-bit display data

2^ndMPU data corresponding to the lower 8-bit display data

(iii) WIN

WIN = “1” : Window area ON

WIN = “0” : Window area OFF(default)

(iv) IDSX

X address auto increment/auto decrement

IDSX = “0” : auto increment

IDSX = “1” : auto decrement

(v) IDSY

Y address auto increment/auto decrement

IDSY = “0” : auto increment

IDSY = “1” : auto decrement

Ver.2004-06-29

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NJU6854

(vi) VWR

Setting the direction of data write /read to DDRAM

VWR = “0” : start from X direction

VWR = “1” : start from Y direction

(vii) AIM[1:0]

AIM1

AIM0

0

1

0

1

0

1

Auto increment/decrement during data writing and reading

Auto increment/decrement during data writing

Auto increment/decrement OFF

Prohibited

(12-5) Display Line Number

Register: VPC TABLE0 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

VPC7 VPC6

VPC5 VPC4 VPC3

VPC2 VPC1

VPC0

(default: VPC[7:0] = 84_H, address: 2_H)

VPC[7:0]: display line number (displayed pixel number in Y direction).

Setting within the range of 2~132（02H~84H）

VPC7

VPC6

VPC5

VPC4

VPC3

VPC2

VPC1

VPC0 Vertical Pixel Number

0

1

0

1

0

1

0

1

0

1

Forbidden

2

3

4

5

:

1

0

1

0

1

0

1

130

131

132

Forbidden

1

Forbidden

(12-6) Blank Line Number

Register : FVC TABLE0 [3_H]

D7

D6

D5

D4

*

D3

FVC3

D2

D1

D0

FVC0

CSb

0

RS

1

RDb WRb

1

0

*

FVC2 FVC1

(default: FVC[3:0]=0_H, address: 3_H)

FVC[3:0]: Blank line number(not displayed pixel number in Y direction)

FVC3

0

FVC2

0

FVC1

0

FVC0

0

1

Vertical blanking Lines

0

1

:

1

0

1

14

15

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NJU6854

(12-7) X Address

Register : ADRH TABLE0 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

XA7

XA6

XA5

XA4

XA3

XA2

XA1

XA0

(default: XA[7:0] = 0H, address: 4H)

X address range is from 00H to 83H.

(12-8) Y Address

Register : ADRL TABLE0 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

YA7

YA6

YA5

YA4

YA3

YA2

YA1

YA0

(default: YA[7:0] = 0_H, address: 5_H)

Y address range is from 00H to 83H.

(12-9) Window End X Address

Register : EADRH TABLE0 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

XEA7 XEA6

XEA5 XEA4 XEA3

XEA2 XEA1

XEA0

(default: XEA[7:0] = 0_H, address: 6_H)

Setting X address of window area when window area access is valid(WIN=”1”).

(12-10) Window End Y Address

Register : EADRL TABLE0 [7H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

YEA7 YEA6

YEA5 YEA4 YEA3

YEA2 YEA1

YEA0

(default: YEA[7:0] = 0_H, address: 7_H)

Setting Y address of window area when window area access is valid(WIN=”1”).

(12-11) Display Mode/Grayscale Mode

Register : COLOR TABLE0 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

PWMM1 PWMM0

*

MODE1 MODE0

*

MODED

(default: PWMM[1:0], MODE[1:0], MODED = 0_H, address: 8_H)

(i) MODED

Setting 65k-color or 4k-color display mode

MODED

Display Color Mode

0

1

65,536 Colors Mode (PWM 5bit + 2 FRC)

4,096 Colors(4bit PWM only)

(ii) MODE[1:0]

Bit assignment of display data

MODE[1:0]

Input data

Remark

MODE1 MODE0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

C4

C3

C2

C1

C0 B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 Note ⁽¹⁾

C3

C2

C1

C0

B3 B2 B1 B0

A3 A2 A1 A0

Note ⁽²⁾

C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0 Note ⁽³⁾

Invalid

Note (1) 65,536 colors 5-6-5 data

(2) 4,096 colors 4-4-4 data

(3) 4,096 colors4-4-4 data, upper 4 bits invalid

Ver.2004-06-29

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NJU6854

(iii) PWMM[1:0]

Setting grayscale mode through PWM control.

PWMM1

PWMM0

Grayscale Mode

0

1

0

1

0

1

Select 32 grayscales

Select 16 grayscales

Select 32 grayscales

（

65k mode

）

or 16 grayscales

（

4k mode

）

from 64 levels.

from 32 levels.

（

4k mode

）

from 16 levels.

or 16 grayscales

65k mode

）

（

4k mode

）

from 128 levels.

Using PWM control (PWMM[1:0]) and Frame rate control(FRC), the following display mode can be selected.

PWM control

MODED

Display Mode

FRC control

64 grayscales

base

32 grayscales 16 grayscales

128 grayscales

base

65,536 color

mode

4,096 color

mode

32 grayscales

selectable

32grayscales

selectable

32 grayscales

selectable

0

1

2 scan

Forbidden

16 grayscales

selectable

16 grayscales 16 grayscales

16 grayscales

selectable

unavailable

selectable

The relationship among the oscillating circuit, built-in clock and frame frequency

Original source clock

OSCI,OSC2,OSC3,OSC4,OSC5(external) selection

Internal oscillator resistor selection(0.7~1.3xR)

CRF,CRS[1:0]

register

CRB[2:0] register

GCK(Source clock for grayscale signal) signal generator

GCK

LP

Frequency dividing ratio selection (1/1~1/8) MDIV[2:0] register

BCKG

LP(Latch Pulse) signal generator

Decided by dividing rate(1/127,63,31,15)

PWMM[1:0], MODED

BCKG LP

Selection

one

Duty set

Decided by VPC or (PPC1+PPC2)

or (PPC1+PPC2+PPC3) : 1/2~1/132

VPC,PPC1,PPC2,PPC3

FVC[3:0]

Vertical blanking line set

FLM

Number of inserted LP pulse(0~15)

Source clock for DCDC booster

Booster clock making BCK[3:0]

Booster clock

FVC[3:0]

BLANK

CKCONT

1/127,63,31,15

PWMM[1:0]

1/duty

+

FLM

LP

OSC

MDIV

VPC,

CRB[2:0] MDIV[2:0]

PPC1,PPC2,PPC3

CRF

CRS[1:0]

0

GCK

booster

clock

BCK

0

1

BCKG

BCK[3:0]

1

1/8

BCKG

BCKS

Fig 17 Block Diagram of Oscillator

Frame Duty = 1 / (duty + blank)

Ver.2004-06-29

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NJU6854

PWM duty vs. display mode

PWM control

Display mode

MODED

PWMM=00

variable

1/63

PWMM=01

PWMM=10

fixed

PWMM=11

variable

1/127

variable

1/31

65,536 color mode

4,096 color mode

0

1

Forbidden

1/15

1/63

1/31

1/127

Frame frequency vs. display mode

Display

Usage Oscillator GCK

mode

Grayscale mode

( PWMM[1:0] )

Duty

Blank Equation^*1)

0

5

FLM=1200kHz/(1x127x(132+ 0))=72Hz

FLM=1200kHz/(1x127x(132+ 5))=69Hz

FLM=285kHz/(1x31x(132+ 0))=70Hz

FLM=285kHz/(1x31x(132+10))=65Hz

FLM=170kHz/(1x15x(132+ 0))=86Hz

FLM=170kHz/(1x15x(132+15))=77Hz

FLM=730kHz/(1x63x(132+ 0))=88Hz

FLM=730kHz/(1x63x(132+ 8))=83Hz

1/1

Among

1

2

3

4

1200 kHz

285 kHz

170 kHz

730 kHz

65,536 color Variable

4,096 color Variable

1/132

undivided

128

0

1/1

Among

undivided

32

10

0

1/1

Among

32

4,096 color

Fixed

undivided

15

0

1/1

Among

65,536 color Variable

undivided

64

8

NOTE): FLM: frame frequency = f_OSC/ (MDIV(1,2,3,4,5,6,7,8) x PWMM(15,31,63,127) x (Duty + Blank))

Ver.2004-06-29

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NJU6854

65k Colors Display Mode

Display data and grayscale palette.

Display RAM data

Grayscale by PWM + FRC

A4

B5

C4

0

1

A3

B4

C3

0

1

0

1

A2

B3

C2

0

1

0

1

0

1

0

1

A1

B2

C1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A0

B1

C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-

B0

-

A/C

32 gray

GS=X

B

C/A

32 gray

GS=X

64 gray ⁽¹⁾

GS=1

PB0

GS=0

PB0

PBX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PA0

PA1

PC0

( PB0 + PB1 ) / 2

PB1

( PB1 + PB2 ) / 2

PB2

( PB0 + PB1 ) / 2

PB1

( PB1 + PB2 ) / 2

PB2

PC1

PC2

PA2

( PB2 + PB3 ) / 2

PB3

( PB3 + PB4 ) / 2

PB4

( PB2 + PB3 ) / 2

PB3

( PB3 + PB4 ) / 2

PB4

PA3

PC3

PA4

PC4

( PB4 + PB5 ) / 2

PB5

( PB5 + PB6 ) / 2

PB6

( PB4 + PB5 ) / 2

PB5

( PB5 + PB6 ) / 2

PB6

PA5

PC5

PA6

PC6

( PB6 + PB7 ) / 2

PB7

( PB7 + PB8 ) / 2

PB8

( PB6 + PB7 ) / 2

PB7

( PB7 + PB8 ) / 2

PB8

PA7

PC7

PA8

PC8

( PB8 + PB9 ) / 2

PB9

( PB9 + PB10 ) / 2

PB10

( PB8 + PB9 ) / 2

PB9

( PB9 + PB10 ) / 2

PB10

PA9

PC9

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

PC10

PC11

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19

PC20

PC21

PC22

PC23

PC24

PC25

PC26

PC27

PC28

PC29

PC30

PC31

( PB10 + PB11 ) / 2

PB11

( PB11 + PB12 ) / 2

PB12

( PB10 + PB11 ) / 2

PB11

( PB11 + PB12 ) / 2

PB12

( PB12 + PB13 ) / 2

PB13

( PB13 + PB14 ) / 2

PB14

( PB12 + PB13 ) / 2

PB13

( PB13 + PB14 ) / 2

PB14

( PB14 + PB15 ) / 2

PB15

( PB15 + PB16 ) / 2

PB16

( PB14 + PB15 ) / 2

PB15

( PB15 + PB16 ) / 2

PB16

( PB16 + PB17 ) / 2

PB17

( PB17 + PB18 ) / 2

PB18

( PB16 + PB17 ) / 2

PB17

( PB17 + PB18 ) / 2

PB18

( PB18 + PB19 ) / 2

PB19

( PB19 + PB20 ) / 2

PB20

( PB18 + PB19 ) / 2

PB19

( PB19 + PB20 ) / 2

PB20

( PB20 + PB21 ) / 2

PB21

( PB21 + PB22 ) / 2

PB22

( PB20 + PB21 ) / 2

PB21

( PB21 + PB22 ) / 2

PB22

( PB22 + PB23 ) / 2

PB23

( PB23 + PB24 ) / 2

PB24

( PB22 + PB23 ) / 2

PB23

( PB23 + PB24 ) / 2

PB24

( PB24 + PB25 ) / 2

PB25

( PB25 + PB26 ) / 2

PB26

( PB24 + PB25 ) / 2

PB25

( PB25 + PB26 ) / 2

PB26

( PB26 + PB27 ) / 2

PB27

( PB27 + PB28 ) / 2

PB28

( PB26 + PB27 ) / 2

PB27

( PB27 + PB28 ) / 2

PB28

( PB28 + PB29 ) / 2

PB29

( PB29 + PB30 ) / 2

PB30

( PB28 + PB29 ) / 2

PB29

( PB29 + PB30 ) / 2

PB30

( PB30 + PB31 ) / 2

PB31

( PB30 + PB31 ) / 2

PB31

Note1) 5 bits for PWM control and 1 bit for Frame rate control(total 6 bits display data), SEGBi can realize 64-grayscale

(32-grayscalex2) display.

Note2) Real 64-grayscael can be realized by setting PBX bit(GS=”0”).

Ver.2004-06-29

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NJU6854

4k Colors Display Mode

Display data and grayscale palette.

Display RAM data

Grayscale by PWM

B

A3

B3

C3

0

A2

B2

C2

0

A1

B1

C1

0

A0

B0

C0

0

A / C

16 gray

GS=X

PA1

C / A

16 gray

GS=X

PC1

16 gray

GS=X

PB1

0

1

PA3

PB3

PC3

0

1

0

PA5

PB5

PC5

0

1

PA7

PB7

PC7

0

1

0

PA9

PB9

PC9

0

1

0

1

PA11

PA13

PA15

PA17

PA19

PA21

PA23

PA25

PA27

PA29

PA31

PB11

PC11

PC13

PC15

PC17

PC19

PC21

PC23

PC25

PC27

PC29

PC31

0

1

0

PB13

PB15

PB17

PB19

PB21

PB23

PB25

PB27

PB29

PB31

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Note) Under 4k colors display mode, GS bit is invalid.

(12-12) Oscillating Frequency Adjustment/Frequency Dividing

Register : MDIV TABLE0 [9H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

MDIV2 MDIV1 MDIV0

*

CRB2 CRB1 CRB0

0

1

0

*

(default: MDIV[2:0], CRB[2:0] = 0H, address : 9H)

(i) CRB[2:0]

Frame frequency can be modified by adjusting the resistor of oscillating circuit.

Relationship between RF and Resistance ratio

CRB2

CRB1

CRB0 Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Initial Resistance Ratio

1.1 times of Initial Resistance Ratio

1.2 times of Initial Resistance Ratio

1.3 times of Initial Resistance Ratio

0.9 times of Initial Resistance Ratio

0.8 times of Initial Resistance Ratio

0.7 times of Initial Resistance Ratio

Forbidden

(ii) MDIV[2:0]

Oscillating Frequency or external clock frequency can be divided.

MDIV2

MDIV1

MDIV0 Divide Ratio

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/1 dividing

1/2 dividing

1/3 dividing

1/4 dividing

1/5 dividing

1/6 dividing

1/7 dividing

1/8 dividing

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NJU6854

(12-13) Header COM

Register : HCT TABLE0 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

HCT6 HCT5 HCT4 HCT3 HCT2 HCT1 HCT0

(default: HCT [6:0] = 0_H, address: A_H)

For small panel size(row number is less than 132), this instruction is used to decide Header COM position to

specify available COM drivers. The setting range is from COMA0/COMB0 ~ COMA65/COMB65. Refer to “(13)

Relationship Between Logic COM Number and Physical COM Driver” for details. Note that this instruction is not used

to specify a scan start position, The scan start position is decided by the “Scan Start COM 1~3”.

0 ≤ HCT ≤ (132-VPC)/2

HCT6

HCT5

HCT4

HCT3

HCT2

HCT1

HCT0

Header COM

COMA0/COMB0

COMA1/COMB1

COMA2/COMB2

COMA3/COMB3

COMA4/COMB4

COMA5/COMB5

···

0

···

1

0

···

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

COMA62/COMB62

COMA63/COMB63

COMA64/COMB64

COMA65/COMB65

Forbidden

···

1

Forbidden

(12-14) Initial Display Line

Register : HST TABLE0 [BH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

HST7 HST6 HST5 HST4 HST3 HST2 HST1 HST0

(default : HST[7:0] = 0_H, address: B_H)

This instruction sets the DDRAM Y address, and the addressed RAM data will be displayed by the scan start

COM 1 driver. The available Y address range is from 0~131.

HST7 HST6 HST5 HST4 HST3 HST2 HST1 HST0

Y address

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

:

···

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

128

129

130

131

Forbidden

···

1

Forbidden

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NJU6854

(12-15) Scan Start COM 1

Register : SSC1 TABLE0 [CH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

SSC17 SSC16 SSC15 SSC14 SSC13 SSC12 SSC11 SSC10

(default : SSC1[7:0] = 0_H, address: C_H)

Totally three partial area can be display on the screen once time. This instruction sets the logical number of the scan

start COM driver for the full screen display or for the first partial display. Refer to (13) Relationship between logical

COM number and physical COM driver for details. The available setting range is: 0 ≤ SSC1 ≤ (VPC – 1)

(12-16) Scan Start COM 2

Register : SSC2 TABLE0 [DH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

SSC27 SSC26 SSC25 SSC24 SSC23 SSC22 SSC21 SSC20

(default : SSC2[7:0] = 0_H, address: D_H)

This instruction sets the logical number of the scan start COM driver for the second partial display. Refer to (13)

Relationship between logical COM number and physical COM driver for details. The available setting range is:

SSC1+PCC1 ≤ SSC2 ≤ (VPC – 1)

(12-17) Line Number of Partial Display 1

Register : PCC1 TABLE0 [EH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

PCC17 PCC16 PCC15 PCC14 PCC13 PCC12 PCC11 PCC10

(default : PCC1[7:0] = 0_H, address: E_H)

This instruction sets line number(DDRAM Y address range) for the first partial display. In the partial display mode,

this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display duty.

The available setting range is: 0 ≤ PCC1 ≤ (VPC - SSC1)

(12-18) Line Number of Partial Display 2

Register : PCC2 TABLE0 [FH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

PCC27 PCC26 PCC25 PCC24 PCC23 PCC22 PCC21 PCC20

(default : PCC2[7:0] = 0_H, address: F_H)

This instruction sets line number(DDRAM Y address range) for the second partial display. In the partial display

mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display

duty. The available setting range is: 0 ≤ PCC2 ≤ (VPC – SSC2).

(12-19) N-Line Inversion

Register : MC TABLE1 [0H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

MC7

MC6

MC5

MC4

MC3

MC2

MC1

MC0

(default : MC[7:0] = 0_H, address: 0_H)

This instruction can let LCD driving signal polarity (M signal) to be alternated every N(2=<N<=132) lines. Under

default setting( MC[7:0]=0H), driving signal polarity alternates every frame.

MC7

MC6

MC5

MC4

MC3

MC2

MC1

MC0 Function

0

:

1

:

1

0

:

0

:

0

:

0

:

1

0

:

0

:

1

0

:

0

:

0

:

0

:

0

1

:

1

:

0

1

0

1

:

Frame inversion (Default State)

2 line inversion

3 line inversion

4 line Inversion

:

132 Line Inversion

prohibited

1

:

0

prohibited.

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NJU6854

(i) Frame Inversion (1/132 DUTY)

1

^stline

2^ndline

3^rdline

131^stline132^ndline 1^stline

LP

FLM

M

(ii) N Line Inversion

nth line cycle

1 st line

2nd line

1 st line

3rd line

nth line

n-1th line

LP

FLM

M

(12-20) Power Control 1

Register : TCBI TABLE1 [1H]

D7

D6

D5

D4

D3

*

D2

B2

D1

B1

D0

B0

CSb

0

RS

1

RDb WRb

1

0

VGOFF VBON TCV1 TCV0

(default: VGOFF, VBON, TCV[1:0] = 0H, B[2:0] = 4H, address: 1H)

(i)VGOFF

Voltage Regulator (V_REGoutput) ON/OFF

VG OFF = 0: AMPON=”1”, Voltage Regulator ON

VG OFF = 1:

Voltage Regulator OFF

(ii)VBON

Reference Voltage Generator (VBA output) ON/OFF

VBON = 0: Reference Voltage Circuit OFF

VBON = 1: AMPON=”1” & VGOFF=”0“, Reference Voltage Circuit ON

(iii)TCV[1:0]

Setting temperature compensation coefficient for Reference Voltage Circuit.

TCV[1]

TCV[0]

VBA output

0.0 % /°C

- 0.13 % /°C

- 0.20 % /°C

- 0.24 % /°C

remark

0

1

0

1

0

1

Default setting

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NJU6854

(iv) B[2:0] LCD Bias Ratio

B2

0

B1

0

B0

0

Function

1/5 Bias

0

1

1/6 Bias

0

1

0

1/7 Bias

0

1

1/8 Bias

1

0

1/9 Bias (Initial state)

1/10 Bias

1/11 Bias

1/12 Bias

1

0

1

0

1

(12-21) Electronic Volume Control

Register: EVOL TABLE1 [2H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

EVOL6 EVOL5 EVOL4 EVOL3 EVOL2 EVOL1 EVOL0

(default: EVOL[6:0] = 0_H, address: 2_H)

128 steps available

EVOL6 EVOL5 EVOL4 EVOL3 EVOL2 EVOL1 EVOL0

Output Voltage

Lower

0

1

···

1

···

1

0

1

Higher

V_REGcan be calculated from the equation (1)

V

_REG= V_REFx N ..............................................................................................................(1)

(N determined by VU[2:0](boost level), RG[2:0] and GSEL bits of GVU register)

LCD driving voltage V₀can be calculated from the equation (2)

V0 = 0.5 x V_REG+ M x (V_REG– 0.5 V_REG) / 127 ………………......…… …………….(2)

(electronic volume M determined by EVOL[6:0] bits of EVOL register)

(12-22) Display Timing Signal Monitor/PBX Palette

Register : PBX TABLE1 [3H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

MON

*

GS

PBX3

PBX2 PBX1

PBX0

(default: MON, GS = 0_H, PBX[3:0] = 3_H, address: 3_H)

(i) MON

Setting FLM, LP and M signals output ON/OFF

MON

0

1

Function

FLM, LP, M signal output OFF

（

default

）

FLM, LP, M signal output ON

(ii) GS, PBX[3:0]

When GS=”0”, palette PBX setting is available. When GS=”1”, PB0 is selected.

GS=1

GS=0

PBX[3:0] register invalid

PBX3 PBX2

(Note 1)

0

PBX1

PBX0

Note 1) Under 65k colors mode , palette PBX is selected to set B data. PBX is used to display the grayscale between PB0

and PB1.

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NJU6854

(12-23) Power Control 2

Register : POW2 TABLE1 [5H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

CKCONT AMPON HALT DCON

RES

(default: CKCONT, AMPON, HALT, DCON, RES = 0_H, address: 5_H)

(i) RES

RES = “0”: Default

RES = “1”: Initialization

Note 1) After initialization(RES=”1”), RES bit turn to “0”.

Note 2) After initialization, at least two LP signal cycles is needed to wait to execute the next instruction.

(ii) DCON

Setting voltage booster ON/OFF.

DCON= “0”: voltage booster OFF

DCON= “1”: voltage booster ON

(iii) HALT

Setting power save mode ON/OFF

HALT = “0”: power save mode OFF(default)

HALT = “1”: power save mode ON

LSI Internal status under power save mode:

a. Internal oscillator and LCD power supply is in the halted state.

b. COM/SEG outputs V_SSHlevel voltage.

c. External clock is unacceptable.

d. DDRAM data is remained

e. Instruction Register data is remained

(iv) AMPON

Using together with VGOFF and VBON bits of Power control 1register (TCBI) to set voltage converter ON/OFF.

AMPON = “0” voltage converter OFF

AMPON = “1”: voltage converter ON

(v) CKCONT

Setting GCK signal and LP signal ON/OFF

CKCONT = “0”: GCK and LP OFF

CKCONT = “1”: GCK and LP ON

Note) NJU6854 use internal oscillator or external clock signal to generate GCK and LP signal. Not only used as display

clock, GCK and LP are also used as operating clock for voltage booster. Be sure to set CKCONT=”1” when voltage

booster is used(DCON= “1”).

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NJU6854

(12-24) Booster Level/Amplifier Gain

Register : GVU TABLE1 [6H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

GSEL RG2

RG1

RG0

*

VU2

VU1

VU0

0

1

0

(default: GSEL, RG[2:0] = 0H, VU[2:0] = 0H, address: 6H)

(i) GSEL

Setting amplifier gain of VREG

GSEL = 0: Amplifier gain is determined by VU[2:0] bits as the same as the boost level.

GSEL = 1: Amplifier gain is determined by RG[2:0] bits

(ii)RG[2:0]

When GSEL=”1”, the relationship between RG[2:0] and amplifier gain is showed as below.

GSEL = ‘0’

GSEL = ‘1’

RG1

Amplifier gain (N)

Remark

VU2

0

VU1

0

VU0

0

RG2

RG0

-

2

default VU[2:0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

default RG[2:0]

0

1

4

1

0

5

1

0

1

6

6.45

7

7.3

8.0

-

1

0

1

-

(iii) VU[2:0]

Setting boost level. And when GSEL=”0”, also setting amplifier gain of V_REG.

VU2

0

VU1

0

VU0

0

Function

No Boost Up

0

1

2 Times Boost Up

3 Times Boost Up

4 Times Boost Up

5 Times Boost Up

6 Times Boost Up

Forbidden

0

1

0

1

0

1

0

1

0

1

Forbidden

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NJU6854

(12-25) Voltage Booster Clock

Register : BCK TABLE1 [7H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

BCKS BCKG

*

BCK3

BCK2 BCK1

BCK0

(default: BCKS, BCKG, BCK[3:0] = 0_H, address: 7_H)

Note) NJU6854 use internal oscillator or external clock to generate GCK and LP signal. Not only used as display clock,

GCK and LP are also used as operating clock for voltage booster. Be sure to set CKCONT=”1” when voltage booster is

used(DCON= “1”).

(i) BCK[3:0]

Setting dividing ratio for the oscillating signal or external clock to generate GCK and LP.

BCK3

BCK2

BCK1

BCK0 Function

0

···

1

0

1

0

1

0

1

0

1

0

1/1 Dividing (There is a restriction)

1/2 Dividing

1/3 Dividing

1/4 Dividing

1/5 Dividing

···

0

1

0

1

0

1

0

1

1/12 Dividing

1/13 Dividing

1/14 Dividing

1/15 Dividing

1/16 Dividing

Note) When BCK[3:0]=[0000, MDIV[2:0]=[000] and BCKS=”1” settings are prohibited.

(ii) BCKG

When BCKG=”1”, MDIV output signal is equally divided into 8 time slots.

(iii) BCKS

Selecting divided clock signal.

BCKS = “0” : LP signal

BCKS = “1” : BCKG signal

Note) There is a trade-off relationship between voltage booster driving capability and current consumption, so the optimal

booster clock shall be decided by your LCD module.

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NJU6854

(12-26) Display Control

Register : Display TABLE1 [8H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

REF

SWAP

*

SHIFT1 SHIFT0 TBC

TEN ON/OFF

(default: REF, SWAP, SHIFT[1:0], TBC, TEN, ON/OFF = 0_H, address: 8_H)

(i) ON/OFF

Display Control ON/OFF

ON/OFF = “0”: Display OFF

ON/OFF = “1”: Display ON

(ii) TEN

TEN = “0”: Normal

TEN = “1”: Independent from DDRAM data, pixels are forced to be ON or OFF.

(iii) TBC(TEN = “1”)

TBC = “0” : All pixels ON

TBC = “1” : All pixels OFF

(iv) SHIFT[1:0]

Setting the shift direction of the COM drivers’ output.

(v) SWAP

Switching corresponding relationship between DDRAM data and palette A, B, C. This bit shall be set before

DDRAM data writing.

SWAP = “0”: Normal

SWAP = “1”: SWAP

(vi) REF

Reversing the shift direction of SEG drivers’ output by redirecting X address. This bit shall be set before DDRAM

data writing.

REF = “0”: Normal

REF = “1”: Opposite Direction

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NJU6854

(12-27) PWM Control

Register : PWM TABLE1 [9H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PWMC1 PWMC0 PWMB1 PWMB0 PWMA1 PWMA0

(default: PWMC[1:0], PWMB[1:0],PWMA[1:0] = 0_H, address: 9_H)

(i) PWMC[1:0], PWMB[1:0], PWMA[1:0]

Setting PWM signals for SEGA, SEGB, and SEGC respectively.

SEGAi (i=0~131)

PWMA1

PWMA0

Output Timing

0

1

0

1

0

1

Forward PWM

Backward PWM

Forward and Backward alternately

Shift Phase

SEGBi (i=0~131)

PWMB1

PWMB0

Output Timing

Forward PWM

0

1

0

1

0

1

Backward PWM

Forward and Backward alternately

Shift Phase

SEGCi (i=0~131)

PWMC1

PWMC0

Output Timing

Forward PWM

0

1

0

1

0

1

Backward PWM

Forward and Backward alternately

Shift Phase

LP

forward

backward

forward and

backward

alternatively

shift phase

M

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NJU6854

(12-28) Three Partial Display Areas/ LED Driver Control/REV Bit

Register : ECONT TABLE1 [AH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

TST0 EN3PTL ENLED REV LED13 LED12 LED11 LED10

(default: TST0, EN3PTL, ENLED, REV, LED1[3:0] = 0_H, address: A_H)

(i) TST0

For maker testing, usually set to ”0”.

(ii) EN3PTL

When EN3PTL=”1”, three specified partial areas can be displayed through setting SSC1[7:0]~SSC3[7:0] and

PCC1[7:0]~PCC3[7:0]. If setting EN3PTL=”0”, one or two partial area can be displayed.

(iii) ENLED

When ENLED=”1”, data saved at LED1[3:0] can be used to control white LED through control port(LDAT, LSCK,

LREQ, LRESB)

ENLED = 0 : LDAT, LSCK, LREQ, LRESB ports invalid (high impedance)

ENLED = 1 : LDAT, LSCK, LREQ, LRESB ports valid.

(iv) LED1 [3:0]

When ENLED=”1”, white LED control ports (LDAT, LSCK, LREQ, LRESB) are valid, LED control signal output

from LDAT, LSCK, LREQ and LRESB to LED10, LED11, LED12 and LED13 respectively.

Concerning white LED driver, please refer to NJRC white LED controller series (NJU6051/52/53). Besides, the

above mentioned bits and ports can be used as general-purpose ports too.

Note) For NJRC white LED driver, data pin state will be changed according to request pin. When request pin is “L”, data

pin of white LED driver is in input state, and when request pin is “H”, data pin become output state. when LREQ pin of

NJU6854 is “L”, LDAT pin output signals, and when LREQ is “H”, LDAT is in input state. So, if LDAT, LSCK, LREQ and

LRESB are used as common ports, please pay attention to this point. LSCK, LREQ and LRESB pins can be used as 3-bit

general-purpose ports too.

Example of connection with NJU6053

LRESB

RSTb

LREQ

LSCK

LDAT

REQ

SCK

NJU6053

NJU6854

DATA

Timing Sequence of data sending

LRESb

LREQ

LSCK

LDAT

B7

B6

B5

B1

B0

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NJU6854

Timing Sequence of data receiving

LRESb

LREQ

LSCK

LDAT

B7

B6

B5

B1

B0

Follow Chart of NJU6053 Operation

Initialization of NJU6053

(LRESB=L->H)

“0”-> LED13

or “1” ->LED13

Data Receiving Request Active

(LREQ=H)

Data Sending Request Active (LREQ=L)

“0”-> LED12

“1” -> LED12

Data Setting(LDAT=DATA(7))

Data(7th bit) -> LED10

Clock Setting (LSCK=L->H)

“0” -> LED11

or “1” -> LED11

Data

Cycle 8

times

Clock Setting(LSCK=L->H)

“0” ->LED11

Data

Receiving

sending

Or “1” -> LED11

Clock Setting (LSCK=L->H)

“0” -> LED11

Or “1” -> LED11

DATA 6

~ 1 sent

under the same way

EDATA Read

Data Setting (LDAT=DATA(0))

data(0 bit) -> LED10

In instruction data read,

EDATA is read out

Clock Setting (LSCK=L->H)

“0” -> LED11

Or “1” -> LED11

(v) REV

Without changing data in DDRAM, pixel display state can be inverted

REV = “0”: data=”1” pixel ON (Normal)

REV = “1”: data=”0” pixel ON (Reversed)

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NJU6854

(12-29) Discharge ON/OFF

Register : DIS TABLE1 [BH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

DIS2

DIS1

(default: DIS[2:1] = 0_H, address: B_H)

(i) DIS1

If DIS1=”1”, the capacitors connected to V₀~V₄pins discharge.

DIS1 = “0”: Discharge OFF

DIS1 = “1”: Discharge ON

(ii) DIS2

If DIS2=”1”, the capacitor connected to V_OUTpin discharge

DIS2 = “0”: discharge OFF

DIS2 = “1”: discharge ON

Vout

V0

V1

V2

100k(typ)

V3

V4

5M(typ)

DIS2

DIS1

VEE

V

SSH

(12-30) LED Driver Data

Register : EDATA TABLE1 [CH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

LED27 LED26 LED25 LED24 LED23 LED22 LED21 LED20

(default: LED2[7:0] = 0_H, address: C_H)

(i)LED2[7:0]

Data from NJRC white LED driver(NJU6051/52/53) is saved in this register.

(12-31) Instruction Table/Address

Register : RA TABLE1 [DH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

RSS

RA6

RA5

RA4

RA3

RA2

RA1

RA0

(default: RA[6:0] = 0_H, address: D_H)

RA[6:4] : Instruction table selection

RA6

0

RA5

0

RA4

0

Table indicator

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

Ver.2004-06-29

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NJU6854

RA[3:0] :Register address selection during direct access, or increment number selection in auto increment mode.

Auto increment

setting increment number

Direct access

(address selection)

RA3

RA2

RA1

RA0

（

）

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0_H

1_H

2_H

3_H

4_H

5_H

6_H

7_H

···

B_H

C_H

D_H

E_H

F_H

1

2

3

4

5

6

7

8

···

12

13

14

15

0

1

0

1

0

1

0

1

0

1

RSS: RSS = “1”: increment number in auto increment mode.

RSS = “0”: register address selection for direct access

(12-32) Scan Start COM 3

Register : SSC3 TABLE1 [EH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

SSC37 SSC36 SSC35 SSC34 SSC33 SSC32 SSC31 SSC30

(default: SSC3[7:0] = 0_H, address: E_H)

This instruction sets the logical number of the scan start COM driver for the third partial display, and the setting

method just as of the Scan Start COM 1 or 2. This instruction can not be used with normal display and single partial

display. When EN3PTL = “1”, the setting is valid.

Range: SSC2 + PCC2 ≤ SSC3 ≤ (VPC – 1)

(12-33) Line Number of Partial Display 3

Register : PCC3 TABLE1 [FH]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

PCC37 PCC36 PCC35 PCC34 PCC33 PCC32 PCC31 PCC30

(default: PCC3[7:0] = 0_H, address: F_H)

This instruction set line number(DDRAM Y address range) for the third partial display area. In the partial display

mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display

duty. When EN3PTL = “1”, the setting is valid

Range: 0 ≤ PCC3 ≤ (VPC – SSC3)

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NJU6854

(12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31)

Register : PA0 TABLE2 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA06

PA05

PA04

PA03

PA02

PA01

PA00

(Initialization: PA0[6:0] = 0_H, Register Address: 0_H)

Register : PA1 TABLE2 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA16

PA15

PA14

PA13

PA12

PA11

PA10

(Initialization: PA1[6:0] = 6_H, Register Address: 1_H)

Register : PA2 TABLE2 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA26

PA25

PA24

PA23

PA22

PA21

PA20

(Initialization: PA2[6:0] = A_H, Register Address: 2_H)

Register : PA3 TABLE2 [3_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA36

PA35

PA34

PA33

PA32

PA31

PA30

(Initialization: PA3[6:0] = E_H, Register Address: 3_H)

Register : PA4 TABLE2 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA46

PA45

PA44

PA43

PA42

PA41

PA40

(Initialization: PA4[6:0] = 12_H, Register Address: 4_H)

Register : PA5 TABLE2 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA56

PA55

PA54

PA53

PA52

PA51

PA50

(Initialization: PA5[6:0] = 16_H, Register Address: 5_H)

Register : PA6 TABLE2 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA66

PA65

PA64

PA63

PA62

PA61

PA60

(Initialization: PA6[6:0] = 1A_H, Register Address: 6_H)

Register : PA7 TABLE2 [7_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA76

PA75

PA74

PA73

PA72

PA71

PA70

(Initialization: PA7[6:0] = 1E_H, Register Address: 7_H)

Register : PA8 TABLE2 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA86

PA85

PA84

PA83

PA82

PA81

PA80

(Initialization: PA8[6:0] = 22_H, Register Address: 8_H)

Register : PA9 TABLE2 [9_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

0

1

0

*

PA96

PA95

PA94

PA93

PA92

PA91

PA90

(Initialization: PA9[6:0] = 26_H, Register Address: 9_H)

Register : PA10 TABLE2 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA106 PA105 PA104 PA103 PA102 PA101 PA100

(Initialization: PA10[6:0] = 2A_H, Register Address: A_H)

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NJU6854

Register : PA11 TABLE2 [B_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA116 PA115 PA114 PA113 PA112 PA111 PA110

(Initialization: PA11[6:0] = 2E_H, Register Address: B_H)

Register : PA12 TABLE2 [C_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA126 PA125 PA124 PA123 PA122 PA121 PA120

(Initialization: PA12[6:0] = 32_H, Register Address: C_H)

Register : PA13 TABLE2 [D_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA136 PA135 PA134 PA133 PA132 PA131 PA130

(Initialization: PA13[6:0] = 36_H, Register Address: D_H)

Register : PA14 TABLE2 [E_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA146 PA145 PA144 PA143 PA142 PA141 PA140

(Initialization: PA14[6:0] = 3A_H, Register Address: E_H)

Register : PA15 TABLE2 [F_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA156 PA155 PA154 PA153 PA152 PA151 PA150

(Initialization: PA15[6:0] = 3E_H, Register Address: F_H)

Register : PA16 TABLE3 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA166 PA165 PA164 PA163 PA162 PA161 PA160

(Initialization: PA16[6:0] = 42_H, Register Address: 0_H)

Register : PA17 TABLE3 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA176 PA175 PA174 PA173 PA172 PA171 PA170

(Initialization: PA17[6:0] = 46_H, Register Address: 1_H)

Register : PA18 TABLE3 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA186 PA185 PA184 PA183 PA182 PA181 PA180

(Initialization: PA18[6:0] = 4A_H, Register Address: 2_H)

Register : PA19 TABLE3 [3_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA196 PA195 PA194 PA193 PA192 PA191 PA190

(Initialization: PA19[6:0] = 4E_H, Register Address: 3_H)

Register : PA20 TABLE3 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA206 PA205 PA204 PA203 PA202 PA201 PA200

(Initialization: PA20[6:0] = 52_H, Register Address: 4_H)

Register : PA21 TABLE3 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA216 PA215 PA214 PA213 PA212 PA211 PA210

(Initialization: PA21[6:0] = 56_H, Register Address: 5_H)

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NJU6854

Register : PA22 TABLE3 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA226 PA225 PA224 PA223 PA222 PA221 PA220

(Initialization: PA22[6:0] = 5A_H, Register Address: 6_H)

Register : PA23 TABLE3 [7_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA236 PA235 PA234 PA233 PA232 PA231 PA230

(Initialization: PA23[6:0] = 5E_H, Register Address: 7_H)

Register : PA24 TABLE3 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA246 PA245 PA244 PA243 PA242 PA241 PA240

(Initialization: PA24[6:0] = 62_H, Register Address: 8_H)

Register : PA25 TABLE3 [9_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA256 PA255 PA254 PA253 PA252 PA251 PA250

(Initialization: PA25[6:0] = 66_H, Register Address: 9_H)

Register : PA26 TABLE3 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA266 PA265 PA264 PA263 PA262 PA261 PA260

(Initialization: PA26[6:0] = 6A_H, Register Address: A_H)

Register : PA27 TABLE3 [B_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA276 PA275 PA274 PA273 PA272 PA271 PA270

(Initialization: PA27[6:0] = 6E_H, Register Address: B_H)

Register : PA28 TABLE3 [C_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA286 PA285 PA284 PA283 PA282 PA281 PA280

(Initialization: PA28[6:0] = 72_H, Register Address: C_H)

Register : PA29 TABLE3 [D_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA296 PA295 PA294 PA293 PA292 PA291 PA290

(Initialization: PA29[6:0] = 76_H, Register Address: D_H)

Register : PA30 TABLE3 [E_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA306 PA305 PA304 PA303 PA302 PA301 PA300

(Initialization: PA30[6:0] = 7A_H, Register Address: E_H)

Register : PA31 TABLE3 [F_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PA316 PA315 PA314 PA313 PA312 PA311 PA310

(Initialization: PA31[6:0] = 7F_H, Register Address: F_H)

Register : PB0 TABLE4 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB06

PB05 PB04

PB03

PB02 PB01

PB00

(Initialization: PB0[6:0] = 0_H, Register Address: 0_H)

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NJU6854

Register : PB1 TABLE4 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB16

PB15 PB14

PB13

PB12 PB11

PB10

(Initialization: PB1[6:0] = 6_H, Register Address: 1_H)

Register : PB2 TABLE4 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB26

PB25 PB24

PB23

PB22 PB21

PB20

(Initialization: PB2[6:0] = A_H, Register Address: 2_H)

Register : PB3 TABLE4 [3_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB36

PB35 PB34

PB33

PB32 PB31

PB30

(Initialization: PB3[6:0] = E_H, Register Address: 3_H)

Register : PB4 TABLE4 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB46

PB45 PB44

PB43

PB42 PB41

PB40

(Initialization: PB4[6:0] = 12_H, Register Address: 4_H)

Register : PB5 TABLE4 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB56

PB55 PB54

PB53

PB52 PB51

PB50

(Initialization: PB5[6:0] = 16_H, Register Address: 5_H)

Register : PB6 TABLE4 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB66

PB65 PB64

PB63

PB62 PB61

PB60

(Initialization: PB6[6:0] = 1A_H, Register Address: 6_H)

Register : PB7 TABLE4 [7_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB76

PB75 PB74

PB73

PB72 PB71

PB70

(Initialization: PB7[6:0] = 1E_H, Register Address: 7_H)

Register : PB8 TABLE4 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB86

PB85 PB84

PB83

PB82 PB81

PB80

(Initialization: PB8[6:0] = 22_H, Register Address: 8_H)

Register : PB9 TABLE4 [9_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

0

1

0

*

PB96

PB95 PB94

PB93

PB92 PB91

PB90

(Initialization: PB9[6:0] = 26_H, Register Address: 9_H)

Register : PB10 TABLE4 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB106 PB105 PB104 PB103 PB102 PB101 PB100

(Initialization: PB10[6:0] = 2A_H, Register Address: A_H)

Register : PB11 TABLE4 [B_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB116 PB115 PB114 PB113 PB112 PB111 PB110

(Initialization: PB11[6:0] = 2E_H, Register Address: B_H)

Register : PB12 TABLE4 [C_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB126 PB125 PB124 PB123 PB122 PB121 PB120

(Initialization: PB12[6:0] = 32_H, Register Address: C_H)

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NJU6854

Register : PB13 TABLE4 [D_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB136 PB135 PB134 PB133 PB132 PB131 PB130

(Initialization: PB13[6:0] = 36_H, Register Address: D_H)

Register : PB14 TABLE4 [E_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB146 PB145 PB144 PB143 PB142 PB141 PB140

(Initialization: PB14[6:0] = 3A_H, Register Address: E_H)

Register : PB15 TABLE4 [F_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB156 PB155 PB154 PB153 PB152 PB151 PB150

(Initialization: PB15[6:0] = 3E_H, Register Address: F_H)

Register : PB16 TABLE5 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB166 PB165 PB164 PB163 PB162 PB161 PB160

(Initialization: PB16[6:0] = 42_H, Register Address: 0_H)

Register : PB17 TABLE5 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB176 PB175 PB174 PB173 PB172 PB171 PB170

(Initialization: PB17[6:0] = 46_H, Register Address: 1_H)

Register : PB18 TABLE5 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB186 PB185 PB184 PB183 PB182 PB181 PB180

(Initialization: PB18[6:0] = 4A_H, Register Address: 2_H)

Register : PB19 TABLE5 [3_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB196 PB195 PB194 PB193 PB192 PB191 PB190

(Initialization: PB19[6:0] = 4E_H, Register Address: 3_H)

Register : PB20 TABLE5 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB206 PB205 PB204 PB203 PB202 PB201 PB200

(Initialization: PB20[6:0] = 52_H, Register Address: 4_H)

Register : PB21 TABLE5 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB216 PB215 PB214 PB213 PB212 PB211 PB210

(Initialization: PB21[6:0] = 56_H, Register Address: 5_H)

Register : PB22 TABLE5 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB226 PB225 PB224 PB223 PB222 PB221 PB220

(Initialization: PB22[6:0] = 5A_H, Register Address: 6_H)

Register : PB23 TABLE5 [7_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB236 PB235 PB234 PB233 PB232 PB231 PB230

(Initialization: PB23[6:0] = 5E_H, Register Address: 7_H)

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- 78 -

NJU6854

Register : PB24 TABLE5 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB246 PB245 PB244 PB243 PB242 PB241 PB240

(Initialization: PB24[6:0] = 62_H, Register Address: 8_H)

Register : PB25 TABLE5 [9_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB256 PB255 PB254 PB253 PB252 PB251 PB250

(Initialization: PB25[6:0] = 66_H, Register Address: 9_H)

Register : PB26 TABLE5 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB266 PB265 PB264 PB263 PB262 PB261 PB260

(Initialization: PB26[6:0] = 6A_H, Register Address: A_H)

Register : PB27 TABLE5 [B_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB276 PB275 PB274 PB273 PB272 PB271 PB270

(Initialization: PB27[6:0] = 6E_H, Register Address: B_H)

Register : PB28 TABLE5 [C_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB286 PB285 PB284 PB283 PB282 PB281 PB280

(Initialization: PB28[6:0] = 72_H, Register Address: C_H)

Register : PB29 TABLE5 [D_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB296 PB295 PB294 PB293 PB292 PB291 PB290

(Initialization: PB29[6:0] = 76_H, Register Address: D_H)

Register : PB30 TABLE5 [E_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB306 PB305 PB304 PB303 PB302 PB301 PB300

(Initialization: PB30[6:0] = 7A_H, Register Address: E_H)

Register : PB31 TABLE5 [F_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PB316 PB315 PB314 PB313 PB312 PB311 PB310

(Initialization: PB31[6:0] = 7F_H, Register Address: F_H)

Register : PC0 TABLE6 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC06

PC05 PC04 PC03

PC02 PC01

PC00

(Initialization: PC0[6:0] = 0_H, Register Address: 0_H)

Register : PC1 TABLE6 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC16

PC15 PC14 PC13

PC12 PC11

PC10

(Initialization: PC1[6:0] = 6_H, Register Address: 1_H)

Register : PC2 TABLE6 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC26

PC25 PC24 PC23

PC22 PC21

PC20

(Initialization: PC2[6:0] = A_H, Register Address: 2_H)

Ver.2004-06-29

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NJU6854

Register : PC3 TABLE6 [3_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC36

PC35 PC34 PC33

PC32 PC31

PC30

(Initialization: PC3[6:0] = E_H, Register Address: 3_H)

Register : PC4 TABLE6 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC46

PC45 PC44 PC43

PC42 PC41

PC40

(Initialization: PC4[6:0] = 12_H, Register Address: 4_H)

Register : PC5 TABLE6 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC56

PC55 PC54 PC53

PC52 PC51

PC50

(Initialization: PC5[6:0] = 16_H, Register Address: 5_H)

Register : PC6 TABLE6 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC66

PC65 PC64 PC63

PC62 PC61

PC60

(Initialization: PC6[6:0] = 1A_H, Register Address: 6_H)

Register : PC7 TABLE6 [7_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC76

PC75 PC74 PC73

PC72 PC71

PC70

(Initialization: PC7[6:0] = 1E_H, Register Address: 7_H)

Register : PC8 TABLE6 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC86

PC85 PC84 PC83

PC82 PC81

PC80

(Initialization: PC8[6:0] = 22_H, Register Address: 8_H)

Register : PC9 TABLE6 [9_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb

WRb

0

1

0

*

PC96

PC95 PC94 PC93

PC92 PC91

PC90

(Initialization: PC9[6:0] = 26_H, Register Address: 9_H)

Register : PC10 TABLE6 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC106 PC105 PC104 PC103 PC102 PC101 PC100

(Initialization: PC10[6:0] = 2A_H, Register Address: A_H)

Register : PC11 TABLE6 [B_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC116 PC115 PC114 PC113 PC112 PC111 PC110

(Initialization: PC11[6:0] = 2E_H, Register Address: B_H)

Register : PC12 TABLE6 [C_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC126 PC125 PC124 PC123 PC122 PC121 PC120

(Initialization: PC12[6:0] = 32_H, Register Address: C_H)

Register : PC13 TABLE6 [D_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC136 PC135 PC134 PC133 PC132 PC131 PC130

(Initialization: PC13[6:0] = 36_H, Register Address: D_H)

Register : PC14 TABLE6 [E_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC146 PC145 PC144 PC143 PC142 PC141 PC140

(Initialization: PC14[6:0] = 3A_H, Register Address: E_H)

Ver.2004-06-29

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NJU6854

Register : PC15 TABLE6 [F_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC156 PC155 PC154 PC153 PC152 PC151 PC150

(Initialization: PC15[6:0] = 3E_H, Register Address: F_H)

Register : PC16 TABLE7 [0_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC166 PC165 PC164 PC163 PC162 PC161 PC160

(Initialization: PC16[6:0] = 42_H, Register Address: 0_H)

Register : PC17 TABLE7 [1_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC176 PC175 PC174 PC173 PC172 PC171 PC170

(Initialization: PC17[6:0] = 46_H, Register Address: 1_H)

Register : PC18 TABLE7 [2_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC186 PC185 PC184 PC183 PC182 PC181 PC180

(Initialization: PC18[6:0] = 4A_H, Register Address: 2_H)

Register : PC19 TABLE7 [3_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC196 PC195 PC194 PC193 PC192 PC191 PC190

(Initialization: PC19[6:0] = 4E_H, Register Address: 3_H)

Register : PC20 TABLE7 [4_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC206 PC205 PC204 PC203 PC202 PC201 PC200

(Initialization: PC20[6:0] = 52_H, Register Address: 4_H)

Register : PC21 TABLE7 [5_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC216 PC215 PC214 PC213 PC212 PC211 PC210

(Initialization: PC21[6:0] = 56_H, Register Address: 5_H)

Register : PC22 TABLE7 [6_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC226 PC225 PC224 PC223 PC222 PC221 PC220

(Initialization: PC22[6:0] = 5A_H, Register Address: 6_H)

Register : PC23 TABLE7 [7_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC236 PC235 PC234 PC233 PC232 PC231 PC230

(Initialization: PC23[6:0] = 5E_H, Register Address: 7_H)

Register : PC24 TABLE7 [8_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC246 PC245 PC244 PC243 PC242 PC241 PC240

(Initialization: PC24[6:0] = 62_H, Register Address: 8_H)

Register : PC25 TABLE7 [9_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC256 PC255 PC254 PC253 PC252 PC251 PC250

(Initialization: PC25[6:0] = 66_H, Register Address: 9_H)

Ver.2004-06-29

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NJU6854

Register : PC26 TABLE7 [A_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC266 PC265 PC264 PC263 PC262 PC261 PC260

(Initialization: PC26[6:0] = 6A_H, Register Address: A_H)

Register : PC27 TABLE7 [B_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC276 PC275 PC274 PC273 PC272 PC271 PC270

(Initialization: PC27[6:0] = 6E_H, Register Address: B_H)

Register : PC28 TABLE7 [C_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC286 PC285 PC284 PC283 PC282 PC281 PC280

(Initialization: PC28[6:0] = 72_H, Register Address: C_H)

Register : PC29 TABLE7 [D_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC296 PC295 PC294 PC293 PC292 PC291 PC290

(Initialization: PC29[6:0] = 76_H, Register Address: D_H)

Register : PC30 TABLE7 [E_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC306 PC305 PC304 PC303 PC302 PC301 PC300

(Initialization: PC30[6:0] = 7A_H, Register Address: E_H)

Register : PC31 TABLE8 [F_H]

D7

D6

D5

D4

D3

D2

D1

D0

CSb

RS

RDb WRb

0

1

0

*

PC316 PC315 PC314 PC313 PC312 PC311 PC310

(Initialization: PC31[6:0] = 7F_H, Register Address: F_H)

Ver.2004-06-29

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NJU6854

65k-color Mode(32 Grayscale from 128 Levels, PWM1=1, PWM0=1)

[Three groups of palettes Aj, Bj and Cj (j=0~31) are available]

(marking points are default positions)

Palette

Grayscale level

0/127

Remarks⁽²⁾

Palette

Grayscale level

64/127

65/127

66/127

67/127

68/127

69/127

70/127

71/127

72/127

73/127

74/127

75/127

76/127

77/127

78/127

79/127

80/127

81/127

82/127

83/127

84/127

85/127

86/127

87/127

88/127

89/127

90/127

91/127

92/127

93/127

94/127

95/127

96/127

97/127

98/127

99/127

100/127

101/127

102/127

103/127

104/127

105/127

106/127

107/127

108/127

109/127

110/127

111/127

112/127

113/127

114/127

115/127

116/127

117/127

118/127

119/127

120/127

121/127

122/127

123/127

124/127

125/127

126/127

127/127

Remarks⁽²⁾

0 0 0 0 0 0 0

0 0 0 0 0 0 1

0 0 0 0 0 1 0

0 0 0 0 0 1 1

0 0 0 0 1 0 0

0 0 0 0 1 0 1

0 0 0 0 1 1 0

0 0 0 0 1 1 1

0 0 0 1 0 0 0

0 0 0 1 0 0 1

0 0 0 1 0 1 0

0 0 0 1 0 1 1

0 0 0 1 1 0 0

0 0 0 1 1 0 1

0 0 0 1 1 1 0

0 0 0 1 1 1 1

0 0 1 0 0 0 0

0 0 1 0 0 0 1

0 0 1 0 0 1 0

0 0 1 0 0 1 1

0 0 1 0 1 0 0

0 0 1 0 1 0 1

0 0 1 0 1 1 0

0 0 1 0 1 1 1

0 0 1 1 0 0 0

0 0 1 1 0 0 1

0 0 1 1 0 1 0

0 0 1 1 0 1 1

0 0 1 1 1 0 0

0 0 1 1 1 0 1

0 0 1 1 1 1 0

0 0 1 1 1 1 1

0 1 0 0 0 0 0

0 1 0 0 0 0 1

0 1 0 0 0 1 0

0 1 0 0 0 1 1

0 1 0 0 1 0 0

0 1 0 0 1 0 1

0 1 0 0 1 1 0

0 1 0 0 1 1 1

0 1 0 1 0 0 0

0 1 0 1 0 0 1

0 1 0 1 0 1 0

0 1 0 1 0 1 1

0 1 0 1 1 0 0

0 1 0 1 1 0 1

0 1 0 1 1 1 0

0 1 0 1 1 1 1

0 1 1 0 0 0 0

0 1 1 0 0 0 1

0 1 1 0 0 1 0

0 1 1 0 0 1 1

0 1 1 0 1 0 0

0 1 1 0 1 0 1

0 1 1 0 1 1 0

0 1 1 0 1 1 1

0 1 1 1 0 0 0

0 1 1 1 0 0 1

0 1 1 1 0 1 0

0 1 1 1 0 1 1

0 1 1 1 1 0 0

0 1 1 1 1 0 1

0 1 1 1 1 1 0

0 1 1 1 1 1 1

Palette 0 initial value[6:0]

1 0 0 0 0 0 0

1 0 0 0 0 0 1

1 0 0 0 0 1 0

1 0 0 0 0 1 1

1 0 0 0 1 0 0

1 0 0 0 1 0 1

1 0 0 0 1 1 0

1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 0 1 0 0 1

1 0 0 1 0 1 0

1 0 0 1 0 1 1

1 0 0 1 1 0 0

1 0 0 1 1 0 1

1 0 0 1 1 1 0

1 0 0 1 1 1 1

1 0 1 0 0 0 0

1 0 1 0 0 0 1

1 0 1 0 0 1 0

1 0 1 0 0 1 1

1 0 1 0 1 0 0

1 0 1 0 1 0 1

1 0 1 0 1 1 0

1 0 1 0 1 1 1

1 0 1 1 0 0 0

1 0 1 1 0 0 1

1 0 1 1 0 1 0

1 0 1 1 0 1 1

1 0 1 1 1 0 0

1 0 1 1 1 0 1

1 0 1 1 1 1 0

1 0 1 1 1 1 1

1 1 0 0 0 0 0

1 1 0 0 0 0 1

1 1 0 0 0 1 0

1 1 0 0 0 1 1

1 1 0 0 1 0 0

1 1 0 0 1 0 1

1 1 0 0 1 1 0

1 1 0 0 1 1 1

1 1 0 1 0 0 0

1 1 0 1 0 0 1

1 1 0 1 0 1 0

1 1 0 1 0 1 1

1 1 0 1 1 0 0

1 1 0 1 1 0 1

1 1 0 1 1 1 0

1 1 0 1 1 1 1

1 1 1 0 0 0 0

1 1 1 0 0 0 1

1 1 1 0 0 1 0

1 1 1 0 0 1 1

1 1 1 0 1 0 0

1 1 1 0 1 0 1

1 1 1 0 1 1 0

1 1 1 0 1 1 1

1 1 1 1 0 0 0

1 1 1 1 0 0 1

1 1 1 1 0 1 0

1 1 1 1 0 1 1

1 1 1 1 1 0 0

1 1 1 1 1 0 1

1 1 1 1 1 1 0

1 1 1 1 1 1 1

1/127

2/127

Palette 16 initial value[6:0]

3/127

Palette X initial value [6:0]⁽¹⁾

Palette 1 initial value[6:0]

4/127

5/127

6/127

Palette 17 initial value[6:0]

Palette 18 initial value[6:0]

Palette 19 initial value[6:0]

Palette 20 initial value[6:0]

Palette 21 initial value[6:0]

Palette 22 initial value[6:0]

Palette 23 initial value[6:0]

Palette 24 initial value[6:0]

Palette 25 initial value[6:0]

Palette 26 initial value[6:0]

Palette 27 initial value[6:0]

Palette 28 initial value[6:0]

Palette 29 initial value[6:0]

Palette 30 initial value[6:0]

7/127

8/127

9/127

10/127

11/127

12/127

13/127

14/127

15/127

16/127

17/127

18/127

19/127

20/127

21/127

22/127

23/127

24/127

25/127

26/127

27/127

28/127

29/127

30/127

31/127

32/127

33/127

34/127

35/127

36/127

37/127

38/127

39/127

40/127

41/127

42/127

43/127

44/127

45/127

46/127

47/127

48/127

49/127

50/127

51/127

52/127

53/127

54/127

55/127

56/127

57/127

58/127

59/127

60/127

61/127

62/127

63/127

Palette 2 initial value[6:0]

Palette 3 initial value[6:0]

Palette 4 initial value[6:0]

Palette 5 initial value[6:0]

Palette 6 initial value[6:0]

Palette 7 initial value[6:0]

Palette 8 initial value[6:0]

Palette 9 initial value[6:0]

Palette 10 initial value[6:0]

Palette 11 initial value[6:0]

Palette 12 initial value[6:0]

Palette 13 initial value[6:0]

Palette 14 initial value[6:0]

Palette 15 initial value[6:0]

Palette 31 initial value[6:0]

Remark 1) PBX[6:0] grayscale palette is enable under GS = ‘0’(defaults) setting.

Remark 2) Please refer to the description of setting range, effective bit and rule for each grayscale palettes

Ver.2004-06-29

- 83 -

NJU6854

65k-color Mode(32 Grayscale from 64 Levels, PWM1=0, PWM0=0)

[Three groups of palettes Aj, Bj and Cj (j=0~31) are available]

(marking points are default positions)

Remarks

Palette

Grayscale level

0/63

Remarks

Palette

Grayscale level

32/63

33/63

34/63

35/63

36/63

37/63

38/63

39/63

40/63

41/63

42/63

43/63

44/63

45/63

46/63

47/63

48/63

49/63

50/63

51/63

52/63

53/63

54/63

55/63

56/63

57/63

58/63

59/63

60/63

61/63

62/63

63/63

0 0 0 0 0 0 X

0 0 0 0 0 1 X

0 0 0 0 1 0 X

0 0 0 0 1 1 X

0 0 0 1 0 0 X

0 0 0 1 0 1 X

0 0 0 1 1 0 X

0 0 0 1 1 1 X

0 0 1 0 0 0 X

0 0 1 0 0 1 X

0 0 1 0 1 0 X

0 0 1 0 1 1 X

0 0 1 1 0 0 X

0 0 1 1 0 1 X

0 0 1 1 1 0 X

0 0 1 1 1 1 X

0 1 0 0 0 0 X

0 1 0 0 0 1 X

0 1 0 0 1 0 X

0 1 0 0 1 1 X

0 1 0 1 0 0 X

0 1 0 1 0 1 X

0 1 0 1 1 0 X

0 1 0 1 1 1 X

0 1 1 0 0 0 X

0 1 1 0 0 1 X

0 1 1 0 1 0 X

0 1 1 0 1 1 X

0 1 1 1 0 0 X

0 1 1 1 0 1 X

0 1 1 1 1 0 X

0 1 1 1 1 1 X

Palette 0 initial value[6:1]

Palette X initial value[6:1]

1 0 0 0 0 0 X

1 0 0 0 0 1 X

1 0 0 0 1 0 X

1 0 0 0 1 1 X

1 0 0 1 0 0 X

1 0 0 1 0 1 X

1 0 0 1 1 0 X

1 0 0 1 1 1 X

1 0 1 0 0 0 X

1 0 1 0 0 1 X

1 0 1 0 1 0 X

1 0 1 0 1 1 X

1 0 1 1 0 0 X

1 0 1 1 0 1 X

1 0 1 1 1 0 X

1 0 1 1 1 1 X

1 1 0 0 0 0 X

1 1 0 0 0 1 X

1 1 0 0 1 0 X

1 1 0 0 1 1 X

1 1 0 1 0 0 X

1 1 0 1 0 1 X

1 1 0 1 1 0 X

1 1 0 1 1 1 X

1 1 1 0 0 0 X

1 1 1 0 0 1 X

1 1 1 0 1 0 X

1 1 1 0 1 1 X

1 1 1 1 0 0 X

1 1 1 1 0 1 X

1 1 1 1 1 0 X

1 1 1 1 1 1 X

1/63

2/63

3/63

4/63

5/63

6/63

7/63

8/63

Palette 16 initial value[6:1]

Palette 17 initial value[6:1]

Palette 18 initial value[6:1]

Palette 19 initial value[6:1]

Palette 20 initial value[6:1]

Palette 21 initial value[6:1]

Palette 22 initial value[6:1]

Palette 23 initial value[6:1]

Palette 24 initial value[6:1]

Palette 25 initial value[6:1]

Palette 26 initial value[6:1]

Palette 27 initial value[6:1]

Palette 28 initial value][6:1]

Palette 29 initial value[6:1]

Palette 30 initial value[6:1]

Palette 31 initial value[6:1]

Palette 1 initial value[6:1]

Palette 2 initial value[6:1]

Palette 3 initial value[6:1]

Palette 4 initial value[6:1]

Palette 5 initial value[6:1]

Palette 6 initial value[6:1]

Palette 7 initial value[6:1]

Palette 8 initial value[6:1]

Palette 9 initial value[6:1]

Palette 10 initial value[6:1]

Palette 11 initial value[6:1]

Palette 12 initial value[6:1]

Palette 13 initial value[6:1]

Palette 14 initial value[6:1]

Palette 15 initial value[6:1]

9/63

10/63

11/63

12/63

13/63

14/63

15/63

16/63

17/63

18/63

19/63

20/63

21/63

22/63

23/63

24/63

25/63

26/63

27/63

28/63

29/63

30/63

31/63

65k-color Mode(32 Grayscale from 32 Levels, PWM1=0, PWM0=1)

[Three groups of palettes Aj, Bj and Cj (j=0~31) are available]

(marking points are default positions)

Palette

Grayscale level

0/31

Remarks

Palette

Grayscale level

Remarks

0 0 0 0 0 X X

0 0 0 0 1 X X

0 0 0 1 0 X X

0 0 0 1 1 X X

0 0 1 0 0 X X

0 0 1 0 1 X X

0 0 1 1 0 X X

0 0 1 1 1 X X

0 1 0 0 0 X X

0 1 0 0 1 X X

0 1 0 1 0 X X

0 1 0 1 1 X X

0 1 1 0 0 X X

0 1 1 0 1 X X

0 1 1 1 0 X X

0 1 1 1 1 X X

Palette 0/X initial value[6:2]

Palette 1 initial value[6:2]

Palette 2 initial value[6:2]

Palette 3 initial value[6:2]

Palette 4 initial value[6:2]

Palette 5 initial value[6:2]

Palette 6 initial value[6:2]

Palette 7 initial value[6:2]

Palette 8 initial value[6:2]

Palette 9 initial value[6:2]

Palette 10 initial value[6:2]

Palette 11 initial value[6:2]

Palette 12 initial value[6:2]

Palette 13 initial value[6:2]

Palette 14 initial value[6:2]

Palette 15 initial value[6:2]

1 0 0 0 0 X X

1 0 0 0 1 X X

1 0 0 1 0 X X

1 0 0 1 1 X X

1 0 1 0 0 X X

1 0 1 0 1 X X

1 0 1 1 0 X X

1 0 1 1 1 X X

1 1 0 0 0 X X

1 1 0 0 1 X X

1 1 0 1 0 X X

1 1 0 1 1 X X

1 1 1 0 0 X X

1 1 1 0 1 X X

1 1 1 1 0 X X

1 1 1 1 1 X X

16/31

Palette 16 initial value[6:2]

Palette 17 initial value[6:2]

Palette 18 initial value[6:2]

Palette 19 initial value[6:2]

Palette 20 initial value[6:2]

Palette 21 initial value[6:2]

Palette 22 initial value[6:2]

Palette 23 initial value[6:2]

Palette 24 initial value[6:2]

Palette 25 initial value[6:2]

Palette 26 initial value[6:2]

Palette 27 initial value[6:2]

Palette 28 initial value][6:2]

Palette 29 initial value[6:2]

Palette 30 initial value[6:2]

Palette 31 initial value[6:2]

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Ver.2004-06-29

- 84 -

NJU6854

4k-color Mode(16 Grayscale from 128 Levels, PWM1=1, PWM0=1)

Only odd number palettes ( ex palette1 palette3 .. palette31)are effective under 4k color mode.

[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available] (marking points are default positions)

Palette

Grayscale level

0/127

Remarks

Palette

Grayscale level

64/127

65/127

66/127

67/127

68/127

69/127

70/127

71/127

72/127

73/127

74/127

75/127

76/127

77/127

78/127

79/127

80/127

81/127

82/127

83/127

84/127

85/127

86/127

87/127

88/127

89/127

90/127

91/127

92/127

93/127

94/127

95/127

96/127

97/127

98/127

99/127

100/127

101/127

102/127

103/127

104/127

105/127

106/127

107/127

108/127

109/127

110/127

111/127

112/127

113/127

114/127

115/127

116/127

117/127

118/127

119/127

120/127

121/127

122/127

123/127

124/127

125/127

126/127

127/127

Remarks

0 0 0 0 0 0 0

0 0 0 0 0 0 1

0 0 0 0 0 1 0

0 0 0 0 0 1 1

0 0 0 0 1 0 0

0 0 0 0 1 0 1

0 0 0 0 1 1 0

0 0 0 0 1 1 1

0 0 0 1 0 0 0

0 0 0 1 0 0 1

0 0 0 1 0 1 0

0 0 0 1 0 1 1

0 0 0 1 1 0 0

0 0 0 1 1 0 1

0 0 0 1 1 1 0

0 0 0 1 1 1 1

0 0 1 0 0 0 0

0 0 1 0 0 0 1

0 0 1 0 0 1 0

0 0 1 0 0 1 1

0 0 1 0 1 0 0

0 0 1 0 1 0 1

0 0 1 0 1 1 0

0 0 1 0 1 1 1

0 0 1 1 0 0 0

0 0 1 1 0 0 1

0 0 1 1 0 1 0

0 0 1 1 0 1 1

0 0 1 1 1 0 0

0 0 1 1 1 0 1

0 0 1 1 1 1 0

0 0 1 1 1 1 1

0 1 0 0 0 0 0

0 1 0 0 0 0 1

0 1 0 0 0 1 0

0 1 0 0 0 1 1

0 1 0 0 1 0 0

0 1 0 0 1 0 1

0 1 0 0 1 1 0

0 1 0 0 1 1 1

0 1 0 1 0 0 0

0 1 0 1 0 0 1

0 1 0 1 0 1 0

0 1 0 1 0 1 1

0 1 0 1 1 0 0

0 1 0 1 1 0 1

0 1 0 1 1 1 0

0 1 0 1 1 1 1

0 1 1 0 0 0 0

0 1 1 0 0 0 1

0 1 1 0 0 1 0

0 1 1 0 0 1 1

0 1 1 0 1 0 0

0 1 1 0 1 0 1

0 1 1 0 1 1 0

0 1 1 0 1 1 1

0 1 1 1 0 0 0

0 1 1 1 0 0 1

0 1 1 1 0 1 0

0 1 1 1 0 1 1

0 1 1 1 1 0 0

0 1 1 1 1 0 1

0 1 1 1 1 1 0

0 1 1 1 1 1 1

1 0 0 0 0 0 0

1 0 0 0 0 0 1

1 0 0 0 0 1 0

1 0 0 0 0 1 1

1 0 0 0 1 0 0

1 0 0 0 1 0 1

1 0 0 0 1 1 0

1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 0 1 0 0 1

1 0 0 1 0 1 0

1 0 0 1 0 1 1

1 0 0 1 1 0 0

1 0 0 1 1 0 1

1 0 0 1 1 1 0

1 0 0 1 1 1 1

1 0 1 0 0 0 0

1 0 1 0 0 0 1

1 0 1 0 0 1 0

1 0 1 0 0 1 1

1 0 1 0 1 0 0

1 0 1 0 1 0 1

1 0 1 0 1 1 0

1 0 1 0 1 1 1

1 0 1 1 0 0 0

1 0 1 1 0 0 1

1 0 1 1 0 1 0

1 0 1 1 0 1 1

1 0 1 1 1 0 0

1 0 1 1 1 0 1

1 0 1 1 1 1 0

1 0 1 1 1 1 1

1 1 0 0 0 0 0

1 1 0 0 0 0 1

1 1 0 0 0 1 0

1 1 0 0 0 1 1

1 1 0 0 1 0 0

1 1 0 0 1 0 1

1 1 0 0 1 1 0

1 1 0 0 1 1 1

1 1 0 1 0 0 0

1 1 0 1 0 0 1

1 1 0 1 0 1 0

1 1 0 1 0 1 1

1 1 0 1 1 0 0

1 1 0 1 1 0 1

1 1 0 1 1 1 0

1 1 0 1 1 1 1

1 1 1 0 0 0 0

1 1 1 0 0 0 1

1 1 1 0 0 1 0

1 1 1 0 0 1 1

1 1 1 0 1 0 0

1 1 1 0 1 0 1

1 1 1 0 1 1 0

1 1 1 0 1 1 1

1 1 1 1 0 0 0

1 1 1 1 0 0 1

1 1 1 1 0 1 0

1 1 1 1 0 1 1

1 1 1 1 1 0 0

1 1 1 1 1 0 1

1 1 1 1 1 1 0

1 1 1 1 1 1 1

1/127

2/127

3/127

4/127

5/127

6/127

Palette 1 initial value[6:0]

Palette 17 initial value[6:0]

7/127

8/127

9/127

10/127

11/127

12/127

13/127

14/127

15/127

16/127

17/127

18/127

19/127

20/127

21/127

22/127

23/127

24/127

25/127

26/127

27/127

28/127

29/127

30/127

31/127

32/127

33/127

34/127

35/127

36/127

37/127

38/127

39/127

40/127

41/127

42/127

43/127

44/127

45/127

46/127

47/127

48/127

49/127

50/127

51/127

52/127

53/127

54/127

55/127

56/127

57/127

58/127

59/127

60/127

61/127

62/127

63/127

Palette 3 initial value[6:0]

Palette 5 initial value[6:0]

Palette 7 initial value[6:0]

Palette 9 initial value[6:0]

Palette 11 initial value[6:0]

Palette 13 initial value[6:0]

Palette 15 initial value[6:0]

Palette 19 initial value[6:0]

Palette 21 initial value[6:0]

Palette 23 initial value[6:0]

Palette 25 initial value[6:0]

Palette 27 initial value[6:0]

Palette 29 initial value[6:0]

Palette 31 initial value[6:0]

Ver.2004-06-29

- 85 -

NJU6854

4k-color Mode(16 Grayscale from 64 Levels, PWM1=0, PWM0=0)

[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available]

(marking points are default positions)

Remarks

Palette

Grayscale level

0/63

Remarks

Palette

Grayscale level

32/63

33/63

34/63

35/63

36/63

37/63

38/63

39/63

40/63

41/63

42/63

43/63

44/63

45/63

46/63

47/63

48/63

49/63

50/63

51/63

52/63

53/63

54/63

55/63

56/63

57/63

58/63

59/63

60/63

61/63

62/63

63/63

0 0 0 0 0 0 X

0 0 0 0 0 1 X

0 0 0 0 1 0 X

0 0 0 0 1 1 X

0 0 0 1 0 0 X

0 0 0 1 0 1 X

0 0 0 1 1 0 X

0 0 0 1 1 1 X

0 0 1 0 0 0 X

0 0 1 0 0 1 X

0 0 1 0 1 0 X

0 0 1 0 1 1 X

0 0 1 1 0 0 X

0 0 1 1 0 1 X

0 0 1 1 1 0 X

0 0 1 1 1 1 X

0 1 0 0 0 0 X

0 1 0 0 0 1 X

0 1 0 0 1 0 X

0 1 0 0 1 1 X

0 1 0 1 0 0 X

0 1 0 1 0 1 X

0 1 0 1 1 0 X

0 1 0 1 1 1 X

0 1 1 0 0 0 X

0 1 1 0 0 1 X

0 1 1 0 1 0 X

0 1 1 0 1 1 X

0 1 1 1 0 0 X

0 1 1 1 0 1 X

0 1 1 1 1 0 X

0 1 1 1 1 1 X

1 0 0 0 0 0 X

1 0 0 0 0 1 X

1 0 0 0 1 0 X

1 0 0 0 1 1 X

1 0 0 1 0 0 X

1 0 0 1 0 1 X

1 0 0 1 1 0 X

1 0 0 1 1 1 X

1 0 1 0 0 0 X

1 0 1 0 0 1 X

1 0 1 0 1 0 X

1 0 1 0 1 1 X

1 0 1 1 0 0 X

1 0 1 1 0 1 X

1 0 1 1 1 0 X

1 0 1 1 1 1 X

1 1 0 0 0 0 X

1 1 0 0 0 1 X

1 1 0 0 1 0 X

1 1 0 0 1 1 X

1 1 0 1 0 0 X

1 1 0 1 0 1 X

1 1 0 1 1 0 X

1 1 0 1 1 1 X

1 1 1 0 0 0 X

1 1 1 0 0 1 X

1 1 1 0 1 0 X

1 1 1 0 1 1 X

1 1 1 1 0 0 X

1 1 1 1 0 1 X

1 1 1 1 1 0 X

1 1 1 1 1 1 X

1/63

2/63

3/63

4/63

5/63

6/63

7/63

8/63

Palette 1 initial value[6:1]

Palette 3 initial value[6:1]

Palette 5 initial value[6:1]

Palette 7 initial value[6:1]

Palette 9 initial value[6:1]

Palette 11 initial value[6:1]

Palette 13 initial value[6:1]

Palette 15 initial value[6:1]

Palette 17 initial value[6:1]

Palette 19 initial value[6:1]

Palette 21 initial value[6:1]

Palette 23 initial value[6:1]

Palette 25 initial value[6:1]

Palette 27 initial value[6:1]

Palette 29 initial value[6:1]

Palette 31 initial value[6:1]

9/63

10/63

11/63

12/63

13/63

14/63

15/63

16/63

17/63

18/63

19/63

20/63

21/63

22/63

23/63

24/63

25/63

26/63

27/63

28/63

29/63

30/63

31/63

4k-color Mode(16 Grayscale from 32 Levels, PWM1=0, PWM0=1)

[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available] (marking points are default positions)

Palette

Grayscale level

0/31

Remarks

Palette

Grayscale level Remarks

16/31

0 0 0 0 0 X X

0 0 0 0 1 X X

0 0 0 1 0 X X

0 0 0 1 1 X X

0 0 1 0 0 X X

0 0 1 0 1 X X

0 0 1 1 0 X X

0 0 1 1 1 X X

0 1 0 0 0 X X

0 1 0 0 1 X X

0 1 0 1 0 X X

0 1 0 1 1 X X

0 1 1 0 0 X X

0 1 1 0 1 X X

0 1 1 1 0 X X

0 1 1 1 1 X X

1 0 0 0 0 X X

1 0 0 0 1 X X

1 0 0 1 0 X X

1 0 0 1 1 X X

1 0 1 0 0 X X

1 0 1 0 1 X X

1 0 1 1 0 X X

1 0 1 1 1 X X

1 1 0 0 0 X X

1 1 0 0 1 X X

1 1 0 1 0 X X

1 1 0 1 1 X X

1 1 1 0 0 X X

1 1 1 0 1 X X

1 1 1 1 0 X X

1 1 1 1 1 X X

1/31

Palette 1 initial value[6:2]

Palette 3 initial value[6:2]

Palette 5 initial value[6:2]

Palette 7 initial value[6:2]

Palette 9 initial value[6:2]

Palette 11 initial value[6:2]

Palette 13 initial value[6:2]

Palette 15 initial value[6:2]

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

Palette 17 initial value[6:2]

2/31

3/31

Palette 19 initial value[6:2]

Palette 21 initial value[6:2]

Palette 23 initial value[6:2]

Palette 25 initial value[6:2]

Palette 27 initial value[6:2]

Palette 29 initial value[6:2]

Palette 31 initial value[6:2]

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

4k-color Mode(16 Grayscale from 16 Levels, PWM1=1, PWM0=0)

[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available] (marking points are default positions)

Palette

Grayscale level

0/15

Remarks

Palette

Grayscale level

8/15

Remarks

0 0 0 0 X X X

0 0 0 1 X X X

0 0 1 0 X X X

0 0 1 1 X X X

0 1 0 0 X X X

0 1 0 1 X X X

0 1 1 0 X X X

0 1 1 1 X X X

Palette 1 initial value[6:3]

Palette 3 initial value[6:3]

Palette 5 initial value[6:3]

Palette 7 initial value[6:3]

Palette 9 initial value[6:3]

Palette 11 initial value[6:3]

Palette 13 initial value[6:3]

Palette 15 initial value[6:3]

1 0 0 0 X X X

1 0 0 1 X X X

1 0 1 0 X X X

1 0 1 1 X X X

1 1 0 0 X X X

1 1 0 1 X X X

1 1 1 0 X X X

1 1 1 1 X X X

Palette 17 initial value[6:3]

Palette 19 initial value[6:3]

Palette 21 initial value[6:3]

Palette 23 initial value[6:3]

Palette 25 initial value[6:3]

Palette 27 initial value[6:3]

Palette 29 initial value[6:3]

Palette 31 initial value[6:3]

1/15

9/15

2/15

10/15

3/15

11/15

4/15

12/15

5/15

13/15

6/15

14/15

7/15

15/15

Ver.2004-06-29

- 86 -

NJU6854

The setting range of the palette level which can be set up is limited in each palette (RGB common).

level

Hex Dec

Palette register

P4 P2

Palette selection range

14 15 16

P6

0

1

P5

0

1

0

1

P3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

2

3

4

5

6

7

8

9

10

11

12

13

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

A

10

11

B

C

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

Caution: Do not set same level for each grayscale palette ( palette

_m

= palette

_n

, m = 0~31, n = 0~31)

Forbidden random level palette ( palette

_n

> palette

_n+1

)

Ver.2004-06-29

- 87 -

NJU6854

The setting range of the palette level can be expressed as the following table.

Palette register

Palette No.

MSB

6

LSB

0

5

0

4

3

2

1

0

Anything

X

1

0

Anything

2

3

4

Except(1,1)

5

6

7

8

Anything

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Except(0,0)

Anything

1

Anything

1

Anything

Caution:

(1) Do not set the same grayscale level in each grayscale palette(forbidden case: palette_m= palette_m+n, m=0~31 n=0~31)

(2) Do not set the zigzag typed grayscale palette. (forbidden case: palette_n> palette_n+1, n=0~31 )

Ver.2004-06-29

- 88 -

NJU6854

(13) PARTIAL DISPLAY FUNCTION

Partial display function is used to save power. In the partial display mode, only specified common drivers output

scanning signals, therefore part of the panel area is selected for display. Because the duty ratio and LCD driving

voltage are lowed in partial display mode. Current consumption can be minimized.

NJU6854 can realize 3 partial display areas on the screen once. The setting of Partial display function is conducted

through Scan Start COM 1~3(SSC1~3) registers, Partial Display Line Number 1~3(PCC1~3) registers, Power Control

1~2 (TCBI,POW2) registers, Amplifier Gain/Booster Level(GVU) register, and 3 Partial Display/LED Control/Rev

(ECONT) register. Refer to (15)TYPICAL INSTRUCTION SEQUENCES for the functions setting

The image of partial display.

(i) Full Screen Display

SSC1

VPC(Display line number)

(Scan Start COM1)

(ii) Partial Display (1 area)

VPC(Display line number)

SSC1

(Scan Start COM1)

PCC1(partial display line number 1)

(iii) Partial Display (2 areas)

VPC(Display line number)

SSC1

(Scan Start COM1)

PCC1(partial display line number 1)

SSC2

(Scan Start COM 2)

PCC2(partial display line number 2)

(iv) Partial Display (3 areas)

VPC(Display line number)

SSC1

(Scan Start COM1)

PCC1(partial display line number 1)

SSC2

PCC2(partial display line number 2)

PCC3(partial display line number 3)

(Scan Start COM 2)

SSC3

(Scan Start COM 3)

Note) For the full screen display, set the Scan Start COM 1(SCC1) and the Display Line Number(VPC).

For the partial display, set the Scan Start COM 1~3(SCC1~3) and the Partial Display Line Number 1~3(PCC1~3). In this

case, the Partial Display Line Number 1~3(PCC1~3) have priority over the Display Line Number(VPC), and thus the

display duty is: Duty=PCC1+PCC2+PCC.

Ver.2004-06-29

- 89 -

NJU6854

(14) RELATIONSHIP BETWEEN LOGICAL COM NUMBER AND PHYSICAL COMMON DRIVER

(EN3PTL=’0’)

VPC (Display line number)

106

HCT (Header COM)

13

SHIFT[1] (COM shift A/B set)

SHIFT[0] (COM shift direction)

SSC1 (Scan Start COM 1)

‘0’ (A start-> A end -> B start -> B end)

‘0’

‘1’

logical

COM

number

0

*

10

0

*

36

80

20

15

*

logical

COM

number

0

*

96

0

*

11

50

15

20

*

SSC2 (Scan Start COM 2)

PCC1 (Line No. of partial display 1)

PCC2 (Line No. of partial display 2)

SSC3 (Scan Start COM 3)

PCC3 (Line No. of partial display 3)

*

A

B

A

B

-

A

B

A

B

A

B

A

B

-

A

B

A

B

A

B

COMA0

COMB0

-

COMA1

COMB1

-

COMA2

COMB2

-

COMA3

COMB3

-

COMA4

COMB4

-

COMA5

COMB5

-

COMA6

COMB6

-

COMA7

COMB7

-

COMA8

COMB8

-

COMA9

COMB9

-

COMA10

COMA11

COMA12

COMA13

COMA14

COMA15

COMA16

COMA17

COMA18

COMA19

COMA20

COMA21

COMA22

COMA23

COMA24

COMA25

COMA26

COMA27

COMA28

COMA29

COMA30

COMA31

COMA32

COMA33

COMA34

COMA35

COMA36

COMA37

COMA38

COMA39

COMA40

COMA41

COMA42

COMA43

COMA44

COMA45

COMA46

COMA47

COMA48

COMA49

COMA50

COMA51

COMA52

COMA53

COMA54

COMA55

COMA56

COMA57

COMA58

COMA59

COMA60

COMA61

COMA62

COMA63

COMA64

COMA65

COMB10

COMB11

COMB12

COMB13

COMB14

COMB15

COMB16

COMB17

COMB18

COMB19

COMB20

COMB21

COMB22

COMB23

COMB24

COMB25

COMB26

COMB27

COMB28

COMB29

COMB30

COMB31

COMB32

COMB33

COMB34

COMB35

COMB36

COMB37

COMB38

COMB39

COMB40

COMB41

COMB42

COMB43

COMB44

COMB45

COMB46

COMB47

COMB48

COMB49

COMB50

COMB51

COMB52

COMB53

COMB54

COMB55

COMB56

COMB57

COMB58

COMB59

COMB60

COMB61

COMB62

COMB63

COMB64

COMB65

-

0

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

96

97

98

99

100

101

102

103

104

105

0

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

17

18

19

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

17

16

15

1

2

7

3

6

4

5

4

6

3

7

2

8

1

9

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

14

13

12

11

10

9

8

7

6

0

1

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

5

4

2

3

2

4

1

5

0

6

7

8

9

7

10

11

12

13

14

15

16

6

5

4

3

2

1

0

one area

Normal

two area

one area

Reversed

two area

R E M A R K

(A -> B)

(A <- B)

Ver.2004-06-29

- 90 -

NJU6854

(EN3PTL= ‘1’)

VPC (Display line number)

HCT (Header COM)

106

13

SHIFT[1] (COM shift A/B set)

SHIFT[0] (COM shift direction)

SSC1 (Scan Start COM 1)

‘1’ (B start-> B end -> A start -> A end)

‘0’

‘1’

logical

COM

0

*

10

0

*

36

80

20

15

*

logical

COM

0

*

96

0

*

11

50

15

20

*

SSC2 (Scan Start COM 2)

PCC1 (Line No. of partial display 1)

PCC2 (Line No. of partial display 2)

SSC3 (Scan Start COM 3)

number

PCC3 (Line No. of partial display 3)

*

A

B

A

B

A

B

A

B

A

B

A

B

A

B

A

B

A

B

COMA0

COMA1

COMB0

COMB1

-

COMA2

COMB2

-

COMA3

COMB3

-

COMA4

COMB4

-

COMA5

COMB5

-

COMA6

COMB6

-

COMA7

COMB7

-

COMA8

COMB8

-

COMA9

COMB9

-

COMA10

COMA11

COMA12

COMA13

COMA14

COMA15

COMA16

COMA17

COMA18

COMA19

COMA20

COMA21

COMA22

COMA23

COMA24

COMA25

COMA26

COMA27

COMA28

COMA29

COMA30

COMA31

COMA32

COMA33

COMA34

COMA35

COMA36

COMA37

COMA38

COMA39

COMA40

COMA41

COMA42

COMA43

COMA44

COMA45

COMA46

COMA47

COMA48

COMA49

COMA50

COMA51

COMA52

COMA53

COMA54

COMA55

COMA56

COMA57

COMA58

COMA59

COMA60

COMA61

COMA62

COMA63

COMA64

COMA65

COMB10

COMB11

COMB12

COMB13

COMB14

COMB15

COMB16

COMB17

COMB18

COMB19

COMB20

COMB21

COMB22

COMB23

COMB24

COMB25

COMB26

COMB27

COMB28

COMB29

COMB30

COMB31

COMB32

COMB33

COMB34

COMB35

COMB36

COMB37

COMB38

COMB39

COMB40

COMB41

COMB42

COMB43

COMB44

COMB45

COMB46

COMB47

COMB48

COMB49

COMB50

COMB51

COMB52

COMB53

COMB54

COMB55

COMB56

COMB57

COMB58

COMB59

COMB60

COMB61

COMB62

COMB63

COMB64

COMB65

-

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

17

18

19

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

17

16

15

1

2

7

3

6

4

5

4

6

3

7

2

8

1

9

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

14

13

12

11

10

9

8

7

6

0

1

5

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

4

2

3

2

4

1

5

0

6

7

8

9

7

10

11

12

13

14

15

16

6

5

4

3

2

1

0

one area

Normal

two area

one area

Reversed

two area

R E M A R K

(B -> A)

(B <- A)

Ver.2004-06-29

- 91 -

NJU6854

(EN3PTL= ‘1’)

VPC (Display line number)

HCT (Header COM)

106

13

SHIFT[1] (COM shift A/B set)

SHIFT[0] (COM shift direction)

SSC1 (Scan Start COM 1)

‘0’ (A start-> A end -> B start -> B end)

‘0’

‘1’

logical

COM

0

10

0

36

80

20

15

101

5

logical

COM

0

96

0

SSC2 (Scan Start COM 2)

11

5

PCC1 (Line No. of partial display 1)

PCC2 (Line No. of partial display 2)

SSC3 (Scan Start COM 3)

number

0

number

0

15

50

20

0

PCC3 (Line No. of partial display 3)

0

A

B

A

B

A

B

A

B

A

B

A

B

A

B

A

B

A

B

COMA0

COMA1

COMB0

COMB1

-

COMA2

COMB2

-

COMA3

COMB3

-

COMA4

COMB4

-

COMA5

COMB5

-

COMA6

COMB6

-

COMA7

COMB7

-

COMA8

COMB8

-

COMA9

COMB9

-

COMA10

COMA11

COMA12

COMA13

COMA14

COMA15

COMA16

COMA17

COMA18

COMA19

COMA20

COMA21

COMA22

COMA23

COMA24

COMA25

COMA26

COMA27

COMA28

COMA29

COMA30

COMA31

COMA32

COMA33

COMA34

COMA35

COMA36

COMA37

COMA38

COMA39

COMA40

COMA41

COMA42

COMA43

COMA44

COMA45

COMA46

COMA47

COMA48

COMA49

COMA50

COMA51

COMA52

COMA53

COMA54

COMA55

COMA56

COMA57

COMA58

COMA59

COMA60

COMA61

COMA62

COMA63

COMA64

COMA65

COMB10

COMB11

COMB12

COMB13

COMB14

COMB15

COMB16

COMB17

COMB18

COMB19

COMB20

COMB21

COMB22

COMB23

COMB24

COMB25

COMB26

COMB27

COMB28

COMB29

COMB30

COMB31

COMB32

COMB33

COMB34

COMB35

COMB36

COMB37

COMB38

COMB39

COMB40

COMB41

COMB42

COMB43

COMB44

COMB45

COMB46

COMB47

COMB48

COMB49

COMB50

COMB51

COMB52

COMB53

COMB54

COMB55

COMB56

COMB57

COMB58

COMB59

COMB60

COMB61

COMB62

COMB63

COMB64

COMB65

-

0

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

96

97

98

99

100

101

102

103

104

105

0

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

17

18

19

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

22

21

20

1

2

7

3

6

4

5

4

6

3

7

2

8

1

9

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

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51

52

105

104

103

102

101

100

99

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96

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63

1

2

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42

20

21

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23

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25

26

27

28

29

30

31

32

33

34

19

18

17

16

15

14

13

12

11

10

9

0

1

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

2

8

3

7

4

6

5

6

7

8

9

7

10

11

12

13

14

15

16

6

5

35

36

37

38

39

4

3

2

1

0

3

2

1

0

one area

Normal

two area

one area

Reversed

two area

R E M A R K

(A -> B)

(A <- B)

Ver.2004-06-29

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NJU6854

(EN3PTL= ‘1’)

VPC (Display line number)

HCT (Header COM)

106

13

SHIFT[1] (COM shift A/B set)

SHIFT[0] (COM shift direction)

SSC1 (Scan Start COM 1)

‘1’ (B start-> B end -> A start -> A end)

‘0’

‘1’

logical

COM

0

10

0

36

80

20

15

101

5

logical

COM

0

96

0

SSC2 (Scan Start COM 2)

11

5

PCC1 (Line No. of partial display 1)

PCC2 (Line No. of partial display 2)

SSC3 (Scan Start COM 3)

number

0

number

0

15

20

10

0

PCC3 (Line No. of partial display 3)

0

A

B

A

B

A

B

A

B

A

B

A

B

A

B

A

B

A

B

COMA0

COMA1

COMB0

COMB1

-

COMA2

COMB2

-

COMA3

COMB3

-

COMA4

COMB4

-

COMA5

COMB5

-

COMA6

COMB6

-

COMA7

COMB7

-

COMA8

COMB8

-

COMA9

COMB9

-

COMA10

COMA11

COMA12

COMA13

COMA14

COMA15

COMA16

COMA17

COMA18

COMA19

COMA20

COMA21

COMA22

COMA23

COMA24

COMA25

COMA26

COMA27

COMA28

COMA29

COMA30

COMA31

COMA32

COMA33

COMA34

COMA35

COMA36

COMA37

COMA38

COMA39

COMA40

COMA41

COMA42

COMA43

COMA44

COMA45

COMA46

COMA47

COMA48

COMA49

COMA50

COMA51

COMA52

COMA53

COMA54

COMA55

COMA56

COMA57

COMA58

COMA59

COMA60

COMA61

COMA62

COMA63

COMA64

COMA65

COMB10

COMB11

COMB12

COMB13

COMB14

COMB15

COMB16

COMB17

COMB18

COMB19

COMB20

COMB21

COMB22

COMB23

COMB24

COMB25

COMB26

COMB27

COMB28

COMB29

COMB30

COMB31

COMB32

COMB33

COMB34

COMB35

COMB36

COMB37

COMB38

COMB39

COMB40

COMB41

COMB42

COMB43

COMB44

COMB45

COMB46

COMB47

COMB48

COMB49

COMB50

COMB51

COMB52

COMB53

COMB54

COMB55

COMB56

COMB57

COMB58

COMB59

COMB60

COMB61

COMB62

COMB63

COMB64

COMB65

-

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

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85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

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66

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81

82

83

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85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

0

17

18

19

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

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80

79

78

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74

73

72

71

70

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68

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66

65

64

63

62

61

60

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57

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55

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53

52

51

50

49

48

47

46

45

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43

42

41

40

39

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36

35

34

33

32

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30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

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75

74

73

72

71

70

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68

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66

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64

63

62

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60

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57

56

55

54

53

62

61

60

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58

57

56

55

54

53

52

51

50

49

48

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46

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43

42

41

40

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30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

22

21

20

1

2

7

3

6

4

5

4

6

3

7

2

8

1

9

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

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40

41

42

43

44

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46

47

48

49

50

51

52

10

11

12

13

14

15

16

17

18

19

20

21

22

23

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25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

19

18

17

16

15

14

13

12

11

10

9

0

1

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

2

8

3

7

4

6

5

6

7

8

9

7

10

11

12

13

14

15

16

6

5

35

36

37

38

39

4

3

2

1

0

3

2

1

0

one area

Normal

two area

one area

Reversed

two area

R E M A R K

(B -> A)

(B <- A)

Ver.2004-06-29

- 93 -

NJU6854

Example of panel connection 1 (HCT=00H)

Physical COM Layout

RAM Mapping

Scanning Direction

SHIFT[1:0]

=(0,1)

X Address

00H

83H

00H

83H

SHIFT[1:0]

=(0,0)

Scanning Direction

COMB[65~0]

COMA[0~65]

Example of panel connection 2 (HCT=0AH)

Physical COM Layout

RAM Mapping

Scanning Direction

SHIFT[1:0]

=(0,1)

X Address

00H

83H

00H

6FH

70H

SHIFT[1:0]

Scanning Direction

=(0,0)

83H

COMB[65~10]

COMA[10~65]

Ver.2004-06-29

- 94 -

NJU6854

(15) TYPICAL INSTRUCTION SEQUENCES

(1) Initialization (internal power supply)

V_DD, V_EE– V_SSRESb=”L”

Power Supply Stabilization

RESb=”H”

Note 1 ) If V_EEis different from V_DD, input V_DDfirst

Note 2) Waiting until V_DDand V_EEstabilization

Note 3) Waiting at least 10 us

WAIT

Bus length selection

8 or 16-bit bus length selection

Display Control

Duty ratio

Blank line number

N-line inversion

Display mode

Note 4) Waiting until V_OUTstabilization

Power Supply

Boost level, amplifier gain for V_REG

Electronic volume

Bias ratio

V

_REG, V_BA

Power Control

(CKCONT=”1", DCON=”1")

Note 5) Waiting until V₀and V₁~V₄stabilization

WAIT

Power Supply

Power control

(AMPON=”1")

WAIT

End of Initialization

Ver.2004-06-29

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NJU6854

(2) Initialization (external power supply)

Note 1) Waiting until V_DDstabilization

Note 2) Waiting at least 10 us

V_DDON, RESb=”L”

Power supply stabilization

RESb=”H”

Note 3) Waiting until V_OUT, V₀~V₄stabilization

V_OUT, V₀~V₄ON

WAIT

Display Control

Duty ratio

Blank line number

N-line inversion

Display mode

End of Initialization

(3) Data Write

Initialization

Display Control

Initial Display Line

Display data configuration / window area

X address Y address

Display data write

Display data ON (ON/OFF=”1")

End of display data setting

Optional condition

(4) Power OFF

Function

Execute HALT or reset instruction

(All drivers outputs V_SS)

Execute discharge instruction

(V₀and V₁~V₄capacitors discharge)

Wait

V_EE, V_DD~V_SSOFF

Ver.2004-06-29

- 96 -

NJU6854

(5) Partial Display

Optional Condition

Display OFF

(ON/OFF="0")

Internal power supply OFF

(DCON="0", AMPON="0")

Note 1) Waiting until voltage booster OFF

WAIT

Power Supply

Note 2) Waiting until V_OUTstabilization

Boost Lever, amplifier gain of V_REG

Electronic volume

Bias ratio

V

_REG, V_BA

Power control

(DCON="1", AMPON="1")

WAIT

Note 3) Waiting until V_OUTV₀and V₁~V₄stabilization

Display Control

Duty ratio

Initial display line

Partial display

Display ON(ON/OFF="1")

Partial display ON

Ver.2004-06-29

- 97 -

NJU6854

ꢀ ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage (1)

Supply Voltage (2)

Supply Voltage (3)

Supply Voltage (4)

Supply Voltage (5)

Supply Voltage (6)

Input Voltage

SYMBOL

CONDITION

TERMINAL

RATING

-0.3 to +4.0

UNIT

V

V_DD

V_EE

-0.3 to +4.0

V

V_OUT

-0.3 to +20.0

-0.3 to V0 + 0.3

-0.3 to V_DD+ 0.3

-45 to +125

V

_SS=0V

V_REG

V

Ta = +25

°

C

V0

V

V₁, V₂, V₃, V₄

*1

V

V_I

V

Storage Temperature

T_stg

°

C

Note 1) D₀~ D₁₅, CSb, RS, RDb, WRb, OSCI, RESb pins

Note 2) To stabilize the LSI operation, place decoupling capacitors between V_DDand V_SS, V_EEand V_SSH

.

ꢀ RECOMMENDED OPERATING CONDITIONS

PARAMETER

Supply Voltage

SYMBOL

V_DD1

V_DD2

V_EE

TERMINAL

V_DD

MIN

1.7

2.4

5

TYP

MAX

3.3

UNIT NOTE

V

*1

*2

*3

*4

3.3

V_EE

V₀

3.3

V₀

18.0

V_OUT

V_REG

V_REF

V_OUT

V_REG

V_REF

Operating Voltage

V_OUT

×

3.3

0.9

1.59(TBD)

-30

*5

Operating

T_opr

85

°

C

Temperature

Note1) Applies to the condition when the reference voltage generator is not used.

Note2) Applies to the condition when the reference voltage generator is used.

Note3) Applies to the condition when the voltage booster is used.

Note4) The following relationship among the supply voltages must be maintained.

V

_SSH<V₄<V₃<V₂<V₁<V₀<V_OUT

Note5) The relationship: V_REF<V_EEmust be maintained.

Ver.2004-06-29

- 98 -

NJU6854

ꢀ DC CHARACTERISTICS

V_SS= 0V, V_DD= +1.7 to +3.3V, Ta = -30 to +85 C

°

SYM

PARAMETER

BOL

NOT

E

CONDITION

MIN

TYP

MAX

UNIT

High level input voltage

Low level input voltage

V_IH

V_IL

0.8 V_DD

0

V_DD

V

*1

*2

*3

*4

*5

0.2V_DD

High level output voltage V_OH1I_OH= -0.4mA

Low level output voltage V_OL1I_OL= 0.4mA

High level output voltage V_OH2I_OH= -0.1mA

Low level output voltage V_OL2I_OL= 0.1mA

V_DD- 0.4

0.4

V_DD- 0.4

0.4

10

2

-10

Input leakage current

Output leakage current

IL_IV_I= V_SSor V_DD

IL_OV_I= V_SSor V_DD

µ

A

V₀= 10V

V₀= 6V

1

2

Driver ON-resistance

R_ON1

*6

*7

|

∆

V_ON| = 0.5V

kΩ

4

15

I_STB

f_OSCI

f_OSC2

V

_DD= 3V

CSb=V_DD, Ta=25

°

C

µA

Stand-by current

TBD

730

170

TBD

V_DD= 3V

Internal oscillation

Frequency

kHz

*8

f_OSC3Ta = 25

f_OSC4

°

C

1200

285

External oscillation

Frequency

Voltage converter

output voltage

f_r1

730

kHz

V

*9

Rf=15k

Ω

, V_DD= 3V,Ta = 25 C

°

N-time booster (N=2 to 6)

(N x V_EE

x 0.95

)

V_OUT

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

*10

RL = 500k

Ω

(V_OUT- V_SS)

V_DD= 3V, 6-time booster

Whole ON pattern

Supply current (1)

Supply current (2)

Supply current (3)

Supply current (4)

Supply current (5)

TBD(760) TBD(1140)

TBD(930) TBD(1400)

TBD(520) TBD(780)

TBD(650) TBD(980)

TBD(360) TBD(540)

TBD(450) TBD(680)

V_DD= 3V, 6-time booster

Checker pattern

V_DD= 3V, 5-time booster

Whole ON pattern

*11

µA

V_DD= 3V, 5-time booster

Checker pattern

V_DD= 3V, 4-time booster

Whole ON pattern

V_DD= 3V, 4-time booster

Checker pattern

Supply current (6)

I_DD6

V_BA

V_BAOperating voltage

1.86

1.9

1.94

V

*12

*13

V_EE= 2.4 to 3.3V@ T=25

°

C

V_EE= 2.4 to 3.3V

(V_REFx N)

x 0.97

(V_REFx N)

x 1.03

V_REGOperating voltage

Output Voltage

V_REG

V

_REF= 1.9

(V_REFx N)

V

N-time booster (N=2 to 6)

V₂

V₃

V_D12

V_D34

V_D24

-100

-30

0

+100

+30

mV *14

-30

+30

-30

+30

Ver.2004-06-29

- 99 -

NJU6854

● Applicable Pins and Conditions

*1 D₀-D₁₅, CSb, RS, RDb, WRb, PS, SEL68, RESb

*2 D₀-D₁₅

*3 LP, FLM, M

*4 CSb, RS, SEL68, RDb, WRb, PS, RESb, OSCI

*5 D₀-D₁₅, M, FLM, LP in the high impedance

*6 SEGA₀-SEGA₁₃₁, SEGB₀-SEGB₁₃₁, SEGC₀-SEGC₁₃₁, COMA₀-COMA₆₅, COMB₀-COMB₆₅

Defines the resistance between the COM/SEG terminals and the power supply terminals (V₀, V₁, V₂, V₃

and V₄) at the condition of 0.5V deference and 1/9 LCD bias ratio.

*7 V_DD

The oscillator is halted, CSb=”1” (disabled), No-load on the COM/SEG drivers

*8 f_OSCI

- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 0, 0).

f_OSC2

- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 0, 1).

f_OSC3

- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (1, 0, 0).

f_OSC4

- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (1, 0, 1).

*9 f_r1

- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 1, 0).

*10 V_OUT

- N x boosting (N=2~6), applicable under internal oscillator circuit and internal power circuit are ON state.

- V_EE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/5 to 1/12 LCD bias, duty is 1/132 , No loads on COM/SEG

drivers.

- RL=500KΩ between the V_OUTand the V_SS, CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”1”, AMPON=”1”

*11 V_DD

- Applies to the condition using the internal oscillator and internal power circuits, no access between the LSI

and MPU.

EVR value is ‘1,1,1,1,1,1,1’.

Driving patterns are ‘all pixels turned-on’ or ‘checkerboard’ display in grayscale mode.

No load are connected on the COM/SEG drivers.

- V_DD=V_EE, V_REF=0.9V_EE, CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”, 1/132 Duty cycle,

Ta=25 C

°

*12 V_BA

V

_EE=2.4V to 3.3V , Ta=25

°

C

*13 V_REG

- V_EE=2.4V to 3.3V, V_REF=1.9(external)V, V_OUT=18V, bias ratio is from 1/5 to 1/12, 1/132 duty cycle,

EVR=(1,1,1,1,1,1,1), Checkerboard display, No-load on the COM/SEG drivers, the voltage booster

N=2 to 6. CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”0”, AMPON=”1”, NLIN=”0”

*14 V0, V₁, V₂, V₃, V₄

- V_EE=3.0V, V_REF=0.9V_EE, V_OUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-load on

the COM/SEG drivers, voltage booster N=5. CA₁=CA₂=1.0uF, CA₃=0.1uF, DCON=”0”, AMPON=”1”

V0

1

V1

V2

VD12 =

VD34 =

VD24 =

1

3

2

-

2

4

2

(VD24 is applied to the condition

that VD12 and VD34 are out of

specifications.)

V3

3

4

V4

VSS

Ver.2004-06-29

- 100 -

NJU6854

ꢀ AC CHARACTERISTICS

(1) Write operation (80-type MPU)

t_AS8

t_AH8

CSb

RS

WRb

t_WRLW8

t_WRHW8

t_DS8

t_DH8

D₀to D₁₅

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85 C)

°

PARAMETER

Address hold time

Address setup time

SYMBOL

t_AH8

t_AS8

CONDITION

MIN.

0

MAX.

UNIT

ns

TERMINAL

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

240

110

ns

WRb

Data setup time

Data hold time

t_DS8

t_DH8

60

15

ns

D₀to D₁₅

(V_DD=1.7 to 2.5V, Ta=-30 to +85 C)

°

PARAMETER

Address hold time

Address setup time

SYMBOL

CONDITION

MIN.

0

MAX.

UNIT

ns

TERMINAL

t_AH8

t_AS8

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

300

95

ns

WRb

Data setup time

Data hold time

t_DS8

t_DH8

80

20

ns

D₀to D₁₅

Note) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-06-29

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NJU6854

(2) Read operation (80-type MPU)

t_AH8

t_AS8

CSb

RS

t_WRLR8

RDb

t_WRHR8

t_RDH8

D₀to D₁₅

t_RDD8

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85 C)

°

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

260

120

ns

RDb

Read Data delay time

Read Data hold time

T_RDD8

T_RDH8

90

ns

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.5V, Ta=-30 to +85 C)

°

PARAMETER

Address hold time

Address setup time

SYMBOL

CONDITION

MIN.

0

MAX.

UNIT

ns

TERMINAL

t_AH8

t_AS8

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

360

170

ns

RDb

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

150

ns

CL=15pF

D₀to D₁₅

0

Note) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-06-29

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NJU6854

(3) Write operation (68-type MPU)

t_AS6

t_AH6

CSb

RS

R/W

(WRb)

t_ELW6

t_EHW6

E

(RDb)

t_DS6

t_DH6

D₀to D₁₅

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85

°

C)

PARAMETER

Address hold time

Address setup time

SYMBOL

t_AH6

t_AS6

CONDITION

MIN.

0

MAX.

UNIT

ns

TERMINAL

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

240

110

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

70

15

ns

D₀to D₁₅

(V_DD=1.7 to 2.5V, Ta=-30 to +85

°

C)

PARAMETER

Address hold time

Address setup time

SYMBOL

CONDITION

MIN.

0

MAX.

UNIT

ns

TERMINAL

t_AH6

t_AS6

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

300

95

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

80

20

ns

D₀to D₁₅

Note) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-06-29

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NJU6854

(4) Read operation (68-type MPU)

t_AS6

t_AH6

CSb

RS

R/W

(WRb)

t_ELR6

t_EHR6

E

(RDb)

t_RDH6

D₀to D₁₅

t_RDD6

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85

°

C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

ns

TERMINAL

0

Address hold time

t_AH6

CSb

RS

Address setup time

t_AS6

ns

0

260

120

System cycle time

t_CYC6

t_ELR6

t_EHR6

ns

Enable ”L” level pulse width

Enable ”H” level pulse width

E

100

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.5V, Ta=-30 to +85

°

C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

ns

TERMINAL

0

Address hold time

t_AH6

CSb

RS

Address setup time

t_AS6

ns

0

360

170

System cycle time

t_CYC6

t_ELR6

t_EHR6

ns

Enable ”L” level pulse width

Enable ”H” level pulse width

E

150

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

CL=15pF

D0 to D15

0

Note) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-06-29

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NJU6854

(5) Serial interface

t_CSH

t_CSS

CSb

RS

t_ASS

t_AHS

t_SLW

t_SHW

SCL

t_CYCS

t_DSS

t_DHS

SDA

(V_DD=2.5 to 3.3V, Ta=-30 to +85

°

C)

UNIT

PARAMETER

Serial clock cycle

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

TBD(75)

TBD(33)

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CSb – SCL time

CSb hold time

t_CSS

TBD(33)

ns

CSb

t_CSH

TBD(33)

ns

(V_DD=1.7 to 2.5V, Ta=-30 to +85

°

C)

UNIT

PARAMETER

Serial clock cycle

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

TBD(120)

TBD(55)

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CSb – SCL time

CSb hold time

Note) Each timing is specified based on 20% and 80% of V_DD

t_CSS

TBD(55)

ns

CSb

t_CSH

TBD(55)

ns

.

Ver.2004-06-29

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NJU6854

(6) Display control timing

OSCI

LP

t_DLP

t_DFLM

FLM

t_M

M

Output timing

(V_DD=2.5 to 3.3V, Ta=-30 to +85

°

C)

PARAMETER

FLM delay time

FR delay time

SYMBOL

t_DFLM

t_FR

CONDITION

MIN.

MAX.

500

UNIT

ns

TERMINAL

0

FLM

FR

CL=15pF

500

ns

CL delay time

t_DCL

200

ns

CL

Output timing

(V_DD=1.7 to 2.5V, Ta=-30 to +85

°

PARAMETER

FLM delay time

FR delay time

SYMBOL

t_DFLM

t_FR

CONDITION

CL=15pF

MIN.

MAX.

1000

200

UNIT

ns

TERMINAL

0

FLM

FR

ns

CL delay time

t_DCL

ns

CL

Note) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-06-29

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NJU6854

(7) Reset input timing

t_RW

RESb

t_R

Internal circuit

status

During reset

End of reset

(V_DD=2.4 to 3.3V, Ta=-30 to +85

°

C)

UNIT

PARAMETER

Reset time

SYMBOL

CONDITION

MIN.

10.0

MAX.

Terminal

t_R

1.0

µ

s

RESb “L” level pulse width

t_RW

RESb

µ

(V_DD=1.7 to 2.4V, Ta=-30 to +85

°

UNIT

PARAMETER

Reset time

SYMBOL

MIN.

MAX.

Terminal

t_R

1.5

µ

s

RESb “L” level pulse width

t_RW

10.0

.

RESb

µ

Note) Each timing is specified based on 20% and 80% of V_DD

Ver.2004-06-29

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NJU6854

ꢀ INPUT/OUTPUT BLOCK DIAGRAM

PARAMETER

SYMBOL

C, V_SS=0V, V_DD=3.0V

MIN

TYP

10

MAX

UNIT

ns

Basic delay time of gate

Ta=+25

°

I/O circuit types

(a) Input Circuit

VDD

Input

Input signal

Applicable Pins : CSb, RS RDb, WRb, SEL68,

P/S, RESb, TEST, OSCI

(b) Output Circuit

VDD

output

signal

Applicable Pins : FLM, LP, M, OSCO

Ver.2004-06-29

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NJU6854

(c) Input/Output Circuit

VDD

input/

output

Input signal

input control signal

VDD

output

control signal

output

signal

Applicable Pins : D0 ~ D15,

(d) LCD Drive Circuit for Graphic Display

VLCD

V1/V2

output

control

signal 1

output

control

signal 2

output

control

signal 3

output

control

signal 4

V3/V4

Applicable Pins : SEGA₀to SEGA₁

31

SEGB₀to SEGB₁

SEGC₀to SEGC₁³¹

31

COMA₀to COMA

65

COMB₀to COMB

65

Ver.2004-06-29

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NJU6854

ꢀ MPU Connections

80-type MPU interface

1.7 V ~ 3.3 V

CC

V

DD

V

0

A

RS

1

7

A ~A

7

decoder

CSb

IORQ

0

7

0

7

D ~D

8

80 series

RDb

WRb

RDb

WRb

RESb

SS

V

GND

reset input

68-type MPU interface

1.7 V ~ 3.3 V

CC

V

DD

V

0

A

RS

1

15

A ~A

15

decoder

CSb

VMA

0

7

0

7

D ~D

8

68 series

E

RDb(E)

WRBb

WRb(R/W)

RESb

RESBb

SS

V

GND

reset input

Serial interface

1.7 V ~ 3.3 V

CC

V

DD

V

0

A

RS

1

7

A ~A

7

decoder

CSBb

(CPU)

1

PORT

SDA

SCL

2

PORT

RESbB

RESBb

SS

V

GND

reset input

Ver.2004-06-29

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NJU6854

Memo

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

Ver.2004-06-29

- 111 -


型号：	NJU6854CJ
厂家：	NEW JAPAN RADIO
描述：	暂无描述驱动 CD
文件：	总111页 (文件大小：1859K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6854CJ [NJRC]

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