NJU7360RB1 [NJRC]

Brushless DC Motor Controller, 0.6A, CMOS, PDSO8, MO-187DA, TVSP, MSOP-8;
NJU7360RB1
型号: NJU7360RB1
厂家: NEW JAPAN RADIO    NEW JAPAN RADIO
描述:

Brushless DC Motor Controller, 0.6A, CMOS, PDSO8, MO-187DA, TVSP, MSOP-8

电动机控制 光电二极管 电视
文件: 总7页 (文件大小:101K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
NJU7360  
Single-phase DC Brushless Motor Driver IC  
GENERAL DESCRIPTION  
PACKAGE OUTLINE  
The NJU7360 is a single-phase DC brushless motor driver  
IC designed for small and high power fan-motor applications.  
It provides a low operating current of 2mA (typ.) and low  
saturation output voltage at high output current operation,  
which offers a high efficiency motor driving. It also has a high  
output current capability of 1000mA (peak) and 400mA  
(continuous). The NJU7360 has a hall bias circuit and hall  
signal amplifier for output wave optimization, which offers a low  
noise motor driving. It also has useful functions such as a FG  
(frequency generator) output for speed detection and thermal  
shutdown. The NJU7360 is available in a small and thin  
package of MSOP8 (TVSP8), which provides downsizing and  
thinning in motor applications.  
NJU7360RB1  
( MSOP8 (TVSP8 ))  
FEATURES  
Operating Voltage  
VDD =2.2 to 5.5V  
Low Operating Current IDD = 2mA(typ.)  
Low Saturation Output Voltage  
VOM=±0.30V @Io=±250mA  
Thermal Shutdown Circuit  
Frequency Generator Output  
Hall Bias Terminal  
C-MOS Technology  
Package outline  
BLOCK DIAGRAM  
1
MSOP8 (TVSP8)*  
*MEET JEDEC MO-187-DA / THIN TYPE  
PIN FUNCTION  
8
PIN no. PIN NAME  
-
+
1
2
3
4
5
6
7
8
OUT B  
IN+  
HB  
IN-  
FG  
VDD  
OUT A  
GND  
2
7
TSD  
Hall  
Bias  
+
-
3
4
6
5
+
-
Ver.2012-07-18  
- 1 -  
NJU7360  
ABSOLUTE MAXIMUM RATINGS  
(Ta=25°C)  
NOTE  
PARAMETER  
RATINGS  
SYMBOL (unit)  
Supply Voltage  
Input Voltage  
+7.0  
-0.3 to VDD  
600  
VDD (V)  
VID (V)  
1)  
Output Current (Peak)  
FG Output Current  
IO PEAK (mA)  
IFG (mA)  
5
Operating Temperature Range  
Storage Temperature Range  
Power Dissipation  
-40 to +85  
-50 to +150  
400  
Topr (°C)  
Tstg (°C)  
PD (mW)  
Tjmax (°C)  
Device itself  
Junction Temperature  
150  
1): The Input Voltage (VID) never exceeds the Supply Voltage (VDD).  
RECOMMENDED OPERATING CONDITIONS  
(Ta=25°C, VDD=5V)  
PARAMETER  
Supply Voltage  
SYMBOL  
VDD  
CONDITION  
-
MIN.  
2.2  
TYP.  
5.0  
MAX.  
UNIT  
5.5  
V
Input Common Mode Voltage  
Range  
VICM  
-
0.4  
-
4.0  
V
ERECTRICAL CHARACTERISTICS  
PARAMETER SYMBOL  
General  
(Ta=25°C, VDD= 5V)  
CONDITION  
MIN.  
TYP.  
MAX.  
UNIT  
Operating Current  
Thermal Shutdown  
Temperature  
I DD  
TTSD  
THYS  
-
-
-
-
-
-
2.0  
180  
50  
5.0  
mA  
°C  
°C  
-
-
Thermal Shutdown Hysteresis  
Hall Amplifier  
Close Loop Gain  
Input Offset Voltage  
Output  
AV  
VIO  
-
-
43  
-12  
46  
-
49  
12  
dB  
mV  
Maximum Output  
Voltage Range  
FGL Output Voltage  
FGH Leak Current  
Hall Bias  
VOH  
VOL  
VFG  
Io=250mA  
Io= -250mA  
RFG=10kΩ  
-
4.55  
4.70  
0.30  
-
-
-
V
-
-
-
0.45  
0.3  
5.0  
V
µA  
IFG-LEAK  
V
Hall Bias Voltage  
VHB  
-
1.1  
1.3  
1.5  
Ver.2012-07-18  
- 2 -  
NJU7360  
INPUT-OUTPUT TRUTH TABLE  
IN+  
H
IN-  
OUTA  
H
OUTB  
L
FG  
L
L (Output TR : ON)  
L
H
L
H
Z (Output TR : OFF)  
APPLICATION CIRCUIT EXAMPLE  
V+  
D1  
C1  
GND  
1
2
3
4
8
7
6
5
Coil  
-
+
TSD  
Hall  
Bias  
+
-
Hall  
element  
FG out  
+
-
R1  
Ver.2012-07-18  
- 3 -  
NJU7360  
POWER DISSIPATION  
400  
350  
300  
250  
200  
150  
100  
50  
0
125  
150  
25  
50  
75  
85  
100  
AMBIENT TEMPERATURE [DegC]  
TYPICAL CHARACTERISTICS  
FG voltage vs FG input current  
VDD=5V, IN+=2.5V, IN-=GND  
IDD vs VDD  
IN+=V , IN-=GND  
dd  
3
2.5  
2
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
1.5  
1
0.5  
0
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
VDD[V]  
FG inout current [mA]  
Ver.2012-07-18  
- 4 -  
NJU7360  
TYPICAL CHARACTERISTICS  
VOH vs VDD  
IN+=VDD, IN-=GND, Io=+250mA  
VOL vs VDD  
IN+=GND, IN-=VDD, Io=-250mA  
500  
400  
300  
200  
100  
0
500  
400  
300  
200  
100  
0
0
2
4
6
8
0
2
4
6
8
VDD [V]  
VDD [V]  
VOL vs IO  
VOH vs IO  
VDD=5V, IN+=GND, IN-=VDD  
VDD=5V, IN+=VDD, IN-=GND  
2
1.5  
1
5
4.5  
4
0.5  
0
3.5  
3
0
100  
200  
300  
400  
500  
600  
700  
0
100  
200  
300  
400  
500  
600  
700  
IO [mA]  
IO [mA]  
VHB vs VDD  
IN+=VDD/2, IN-=GND, Io=5mA  
1.5  
1.45  
1.4  
1.35  
1.3  
1.25  
1.2  
1.15  
1.1  
0
1
2
3
4
5
6
7
VDD [V]  
Ver.2012-07-18  
- 5 -  
NJU7360  
APPLICATION NOTE  
The NJU7360 is a single-phase DC brushless motor driver IC in a small MSOP8 (TVSP8) package.  
With minimal external components, that can drive up to 250mA of motor current for small fan application.  
[Application Circuit Example]  
1) Hall Bias unused application circuit  
V+  
D1  
C1  
GND  
RL  
HB  
VDD  
Hall  
element  
OUTA  
IN+  
Motor  
IN-  
R1  
OUTB  
FG  
NJU7360  
FG  
[Design Notes]  
Above application example is designed for 5V operation with motor current of 250mA. It uses the following  
components:  
Hall elements: HW101A (AKE)  
1. Selection of C1 and D1:  
C1 is used for a noise reduction purpose. A typical value is 0.1uF.  
Optimize the value in actual operating conditions if necessary. D1 is a diode for protection against reverse voltage  
supply. Silicon rectifier diode (WO3C, 10D1 and equivalent) is appropriate.  
2. Position Detection Circuit Hall Device  
2-1. When using HB (R1 design)  
By connecting a Hall device to the Hall bias terminal (HB), a constant Hall output amplitude that has good  
temperature characteristics is obtained, resulting in stable linear drive. If it is necessary to adjust the Hall output  
amplitude, perform adjustment with R1.  
2-2. When using VDD (R2 and R3 design)  
When it is necessary to increase the Hall bias current to increase the Hall output amplitude, obtain Hall bias from VDD.  
The input bias voltage for the amplifier must be used within the Hall input common mode voltage (0.4 - VDD-1 V)  
including the amplitude of the signal. It is recommended that the Hall bias voltage be one half of the power supply  
voltage, that is, VDD/2.  
Ver.2012-07-18  
- 6 -  
NJU7360  
VDD  
R2  
Hall  
element  
IN+  
IN-  
R3  
3. Design of FG output resistance (RL)  
FG Out (FG: Pin5) is an open drain output and RL is a pull up register. A typical value of RL is 10k.  
The timing chart of FG Out is as follows.  
Note that the pull up resistance shall be connected to below supply voltage.  
Hall input  
IN+  
FG  
T
e
rminal  
[CAUTION]  
The specifications on this databook are only  
given for information , without any guarantee  
as regards either mistakes or omissions. The  
application circuits in this databook are  
described only to show representative usages  
of the product and not intended for the  
guarantee or permission of any right including  
the industrial rights.  
Ver.2012-07-18  
- 7 -  

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