NJU7505BD [NJRC]
Active Filter;
| 型号： | NJU7505BD |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Active Filter |
| 文件： | 总9页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU7505
BAND PASS FILTER FOR AUDIO SPECTRUM ANALYZER DISPLAY
! GENERAL DESCRIPTION
! PACKAGE OUTLINE
The NJU7505 is a band pass filter for audio spectrum
analyzer display.
It consists of high and low band pass filters, CR oscillation
circuit, control circuit and DC transfer circuit.
Each band pass filter using the switched capacitor filter
technology operates at the shared time by 5 bands which
filter constant is switched by the internal clock.
Therefore, the audio signal shared of 5 bands is output from
a serial output terminal.
NJU7505XD
NJU7505XM
The 10 bands version using the double by the cascade
connection is prepared.
! FEATURES
! PIN CONFIGURATION
" BPF for the audio spectrum analyzer display of the 5 bands
" 10 bands extension is available by the cascade connection
(Version of A: For 5-band application by the single)
(Version of B: For 10-band application by the double)
" BPF using the switched capacitor filter technology
" CR oscillation circuit on chip
(External clock input is available)
" Power-on initialization circuit on chip
(External reset input is available)
OSC1
OSC2
1
VDD
5
6
AIN
2
3
4
AOUT
VSS
7
8
RST/CLKO
RD
" C-MOS Technology
" Package Outline
DIP8, DMP8
! BLOCK DIAGRAM
Audi o Signal
Control Signa
Crock Signal
RST/CLKO
RD
OSC1
Power-on
Initialize
Control Circuit
OSC
OSC2
Φ H
Φ L
iH
iL
RL
RH
f
OSC
f
OSC/16
f
OSC/4
BPF
High Band
High Band
Peak Detector
Level Shif ter
&
AIN
AOUT
Input BUF
LPF
Out Put BUF
BPF
Low Band
Low Band
Peak Detector
VDD
VDD
AGND
VSS
VSS
Ver.2004-06-04
- 1 -
NJU7505
! TERMINAL DESCRIPTION
NO.
SYMBOL
FUNCTION
1
2
OSC1
OSC2
External Resistor connecting terminal.
External Resistor connecting terminal or External clock input terminal.
Both as Reset input terminal
3
RST/CLKO
and the clock of (2/3)*fosc output terminal.
4
RD
Trigger signal for reading-out the AOUT of each band output terminal.
5
8
6
7
VSS
VDD
AOUT
AIN
GND
0V
Positive power supply +5.0 V
Peak voltage of each band output terminal.
Audio signal input terminal.
! VERSION LINEUP AND PEAK FREQUENCY
The NJU7505 prepares two version of A and B which are different of the peak frequency of each bands.
The version of A is recommended for the 5 bands application using the single and the version of B is
recommended for the 10 bands using the double by the cascade connection, however, the version of A can be
used for the 10 bands using the double and the version of B can be used for the 5 bands using the single.
Peak Frequency ( Hz )
Band
Using the single
Using the double
Version of A
Version of B
Version of A
Version of B
f1a
f1b
f2a
f2b
f3a
f3b
f4a
f4b
f5a
f5b
12k
18k
-
5.3k
-
1.5k
-
375
-
12k
8k
3.5k
2.3k
1k
18k
12k
5.3k
3.5k
1.5k
1k
375
250
95
-
3.5k
-
1k
-
250
-
63
-
670
250
165
63
95
-
42*
63
Note 1) The bands of f1a, f2a, ... f5a correspond to the master side and the bands of f1b, f2b, ... f5b correspond
to the slave side at the cascade connection of the double.
Note 2) It may not be output along the expectation at the peak frequency of * marking, since the sampling time is
not enough.
The example of using the single
The example of using the double
f1a to f5a
2/3 * f OSC
f 1b t o f5b
OSC1
f1a to f5a
OSC1
OSC1
AOUT
AOUT
AOUT
NJU7505
Master
NJU7505
Slave
NJU7505
OSC2
RST/CLKO
fOS C
fOS C
OSC2
- 2 -
Ver.2004-06-04
NJU7505
! FUNCTIONAL DESCRIPTION
# Interface to external controller
The example of the interface between the NJU7505 and the external controller is shown below;
(1)Example of the interface to the external controller ( Using the single )
After the RST signal from the external controller is input and then the internal circuit is initialized, each band data
is output as shown below timing chart;
Since the RD signal is output before each band is switched, the external controller is to count the number of the
RD signal and is to recognize the status of the band and is to read the output data from the AOUT terminal through
the external A/D converter.
The output type of the external controller connected to the RST/CLKO terminal as the RST input should be the
N-channel and open-drain type or the diode should be connected between the RST/CLKO terminal and the
output terminal of the external controller, so that the voltage of the RST/CLKO terminal is not gotten over the VSS
level.
A
IN
OSC1
NJU7505 OSC2
fOSC
A
OUT
A / D
CONVERTER
V
SS
RD
RST/CLKO
µ COM
3*214 / fOSC
f5
f1
f2
f3
f1
f2
f4
f3
f1
f1
f2
f3
A OUT
f2
f1
f2
f3
f5
f1
f2
f4
f3
f1
RD
RST
248 / fosc
AOUT
Since the RD signal is output before 248/fOSC of each
band switched, the output data should be read out
within the limited time as shown right;
8 / fosc
RD
Available Period
of Read-out
f n
f 1
AOUT
If the RST signal which pulse width is more than
4/fOSC is input, the internal circuit is initialized and the
data of f1 band is output from the AOUT terminal after
52/fOSC of the rise edge of the RST signal.
4/ fosc[MIN] 52/ fosc
RST
Ver.2004-06-04
- 3 -
NJU7505
(2) Example of the interface to the external controller (Using the double)
The 10 bands application is available using the cascade connection of the double NJU7505 as shown blow.
After the RST signals from the external controller are input to each of the master and the slave of the NJU7505
and then each internal circuit is initialized, each band data is output as shown below timing chart;
Since the RD signals are output from the master and the slave before each band is switched, the external
controller is to count the number of the RD signals and is to recognize the status of the band and is to read the
output data from each AOUT terminals through the external A/D converter.
The master clock for the slave is provided with the output signal from the RST/CLKO terminal of the master. The
master clock for the slave is stopped when the RST signal is input from the external controller to the master, so
that the RST/CLKO terminal of the master is used both as the RST input of the master and the master clock for
the slave.
The output type of the external controller connected to each RST/CLKO terminal as the RST input should be the
N-channel and open-drain type or the diode's should be connected between each RST/CLKO terminal and the
output terminals of the external controller, so that the voltage of each RST/CLKO terminal is not gotten over the
VSS level.
AIN
AIN
OSC1
OSC2
NJU7505
Slave
NJU7505 OSC2
Master
AOUT
A/D
CONVERTER
AOUT
VSS
RST/CLKO
RD
RD
RST/CLKO
µ COM
3*214 / fOSC
Master
f1
f2
f5
f5
f1
f1
f2
f4
f4
f3
f3
f1
f2
f3
f3
f2
A OUT
f3
f1
f1
f2
f1
f2
f3
f2
f1
RD
RST
Slave
3*214 / fOSC * 3/2
f2
A OUT
f1
f3
f5
f1
f2
f4
f3
f3
f1
f2
f1
f2
f3
f5
f1
f2
f4
f1
RD
RST
- 4 -
Ver.2004-06-04
NJU7505
248 / fosc
(248/ fosc*3/2)
Since each RD signal of the master and the slave is
output before 248/fOSC (248/fOSC*3/2) of each band
switched, the output data should be read out within the
limited time as shown right;
AOUT
8 / fosc
(8/ fosc*3/2)
RD
* The "( )" is corresponded to the slave.
Available Period
of Read-out
f n
f 1
AOUT
(Master)
If the RST signal which pulse width is more than
4/fOSC is input to the master, the internal circuit is
initialized and the data of f1 band is output from the
AOUT terminal of the master after 52/fOSC of the rise
edge of the RST signal.
4/fosc[MIN]
52/ fsoc
RST
(Master)
The RST signal for the slave should be set to "L" level
while the RST signal for the master is "L" level and
should keep "L" level more than 6/fOSC. So the slave
operates as same as the master after 78/fOSC of the
rise edge of the RST signal for the slave.
RST
(Slave)
6/fosc[MIN]
f n’
78/ fsoc
AOUT
(Slave)
f 1’
Ver.2004-06-04
- 5 -
NJU7505
! ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
NOTE
PARAMETER
Supply Voltage
SYMBOL
RATINGS
UNIT
V
VDD
VIN
-0.3 to +7
-0.3 to VDD+0.3
-0.3 to 0
7
5, 8
Input Voltage
V
VIO
Output Voltage
Power Dissipation
Operating
Temperature
Storage Temperature
VOUT
PD
-0.3 to VDD+0.3
500(DIP), 300(DMP)
V
mW
Topr
Tstg
-30 to 85
°C
°C
-55 to 125
Note 3) If the IC are used on condition above the absolute maximum ratings, the IC may be destroyed. Using the
IC within electric characteristic conditions will cause malfunction and poor reliability.
Note 4) All voltage values are specified as VSS = 0V.
Note 5) When the voltage of the RST/CLKO terminal is gotten over the VSS level, the diode should be connected
between the RST/CLKO terminal and the external.
Note 6) Decoupling capacitor should be connected between the VDD terminal and the VSS due to the stabilization
of the operation.
Note 7) Applied to the AIN or the OSC2 terminals.
Note 8) Applied to the RST/CLKO terminal.
! ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(VDD=5V, VSS= 0V, Ta=25°C)
TYP MAX UNIT NOTE
PARAMETER
SYMBOL
CONDITITONS
MIN
Operating Voltage
Operating Current
VDD
IDD
IIL1
IIH1
IIL2
VILC
VIHC
VOL1
VOH1
VOL2
VOH2
VOS
4.5
-
-0.1
5.0
6.0
6.0
12
V
mA
VDD TERMINAL
AIN TERMINAL
VIL1=0V
-0.05 -0.033
Input Leak Current 1
mA
mA
V
VIH1=5V 0.033 0.05
0.1
-0.05
1.5
5.0
0.5
5.0
0.5
4.75
300
-
Input Leak Current 2
External Clock
Input Voltage
RST/CLKO TERMINAL VIH2=0V
-0.2
0
3.5
0
4.5
0
4.25
-
-0.1
-
-
-
OSC2 TERMINAL
IOL1=100µA
RD TERMINAL
Output Voltage 1
V
V
IOH1=-100µA
-
RST/CLKO
TERMINAL
AOUT TERMINAL
AOUT TERMINAL Sine Wave Input
fIN=f1 to f5 VIN=200mVp-p
IOL1=100µA
IOH1=-5µA
AIN:OPEN
-
4.5
-
26.0
-
Output Voltage 2
Output Offset Voltage
BPF Output Voltage
mV
dB
V
-
9,10,11
9,10
VOUT
3.5
-
Note 9) This specification is tested on condition of fCLK=400KHz (The external clock is input to the OSC2 terminal
through the capacitor for AC coupling.
Note 10) Each input frequency of f1 to f5 is referred to the table of the " VERSION LINEUP AND PEAK
FREQUENCY ".
Note 11) This specification is calculated from " VOUT / VIN ".
- 6 -
Ver.2004-06-04
NJU7505
! AC CHARACTERISTICS
PARAMETER
( VDD=4.5 to 6.0V, VSS=0V, Ta=25°C)
SYMBOL
fOSC
CONDITIONS
MIN
TYP MAX UNIT NOTE
Oscillation Clock Freq
RST/CLKO Terminal
RST/CLKO Terminal
VDD=5V
VILC=0V
360
400
440
KHz
12
External Clock Frequency
fCLK
400
800
KHz
13
VIHC=VDD
8/fOSC
8/fCLK
12/fOS
Master
RD Pulse Width
tPWRD
RD Terminal
µs
14
Slave
C
12/fCLK
4/fOSC
4/fCLK
6/fOSC
6/fCLK
Master
Slave
RST Pulse Width
tPWRS
RST/CLKO Terminal
RST/CLKO Terminal
µs
15
15
RST Rise/Fall Time
tr, tf
100
nA
Note 12) The example for the CR Oscillation
OSC1
RT: 13KΩ(±2%)
CT: 220pF(±5%)
RT
CT
OSC2
*The oscillation clock frequency is calculated from the
output frequency of the RST/CLKO terminal by 3/2.
VSS
Note 13) The example for the external clock input
Open
OSC1
The input signal for the OSC2 terminal should be the
condition of the pulse of DUTY50%±10%.
* The oscillation clock frequency is calculated
from the output frequency of the RST/CLKO terminal
by 3/2.
Oscillator
OSC2
Note 14) The output wave form of the RD terminal.
0.8VDD 0.8VDD
tPWRD
Note 15) The input wave form of the RST terminal.
tr
tf
TPWRS
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Ver.2004-06-04
- 7 -
NJU7505
! APPLICATION CIRCUIT (1)
AUDIO IN
AUDIO IN
Rch
Lch
AUDIO OUT
AUDIO OUT
RESONANCE
CIRCUIT
RESONANCE
CIRCUIT
NJU7305
*1
ATT.
AIN
*2
OSC1
OSC2
13K
NJU7505
220pF
VSS
RD
RST/CLKO
AOUT
*3
A/D
µCOM
DISPLAY DRIVER
DISPLAY
*1 ) The capacitor for AC coupling connected to the AIN terminal should be needed.
*2 ) Connecting the attenuator, the dynamic range of the display can be changed.
*3 ) When the voltage of the output terminal of the µCOM gets over the VSS level, the diode should be connected between
the RST/CLKO terminal and the output of the µCOM.
- 8 -
Ver.2004-06-04
NJU7505
! APPLICATION CIRCUIT (2)
AUDIO IN
AUDIO IN
Lch
Rch
AUDIO OUT
AUDIO OUT
RESONANCE
CIRCUIT
RESONANCE
CIRCUIT
NJU7305
*1
ATT.
*2
ATT.
*2
AIN
AIN
OSC1
13K
OSC2
OSC2
NJU7505
NJU7505
220pF
VSS
RD
RD
RST/CLKO
RST/CLKO
AOUT
AOUT
*3
*3
A/D
A/D
µCOM
DISPLAYDRIVER
DISPLAY
*1 ) The capacitor for AC coupling connected to the AIN terminal should be needed.
*2 ) Connecting the attenuator, the dynamic range of the display can be changed.
*3 ) When the voltage of the output terminal of the µCOM gets over the VSS level,
the diode should be connected between the RST/CLKO terminal and the output
of the µCOM.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2004-06-04
- 9 -
相关型号：
©2020 ICPDF网 联系我们和版权申明