NJW1110V [NJRC]
9-IN 3-OUT STEREO AUDIO SELECTOR; 9 -IN 3 -OUT立体声音频选择器
| 型号： | NJW1110V |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | 9-IN 3-OUT STEREO AUDIO SELECTOR |
| 文件： | 总7页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW1110
9-IN 3-OUT STEREO AUDIO SELECTOR
! GENERAL DESCRIPTION
! PACKAGE OUTLINE
NJW1110 is a 9-input 3-output stereo audio selector.
It includes three independent 9input-1output stereo
audio selectors and adjustable gain buffers.
NJW1110 performs superior audio characteristics
such as low distortion, low output noise and low
crosstalk. All of internal status and variables are
controlled by I2C BUS interface. And the slave
address selector is available for using two chips on
same serial Bus line. It is suitable for latest TV system
and others.
NJW1110V
! APPLICATIONS
•FPD TV
•Car Audio System
•Monitor
! FEATURES
• Operating Voltage
7.5 to 15V
8mA typ.
• Operating Current
• 9-Input, 3-Output Stereo Audio Selector
• Low Distortion
• Low Output Noise
0.0007% typ.
116dB typ.
• Low Crosstalk
110dB typ.
• Channel Separation
• Variable Gain Buffer
100dB typ.
0, 3 to 8dB/0.5dB step
• I2C Bus Interface (Comply with fast mode and 3V I/F)
• Selectable 2-Slave Address
• Bi-CMOS Technology
• Package Outline
SSOP32
! BLOCK DIAGRAM
V+
InB1
InB2
InB3
InB4
InB5
InB6
InB7
InB8
InB9
OutB1
OutB2
OutB3
ADR
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
µ
F
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10
F
10
F
+
µ
µ
µ
µ
+
+
+
+
+
+
+
+
+
+
+
+
+
100
F
µ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
MUTE
Gain
Gain
Gain
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
Vref
50KΩX18
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
I2C
Control
Logic
MUTE
GND
10
GND
14
1
2
3
4
5
6
7
8
9
11
12
13
15
16
+
+
+
+
+
+
+
+
+
+
+
+
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10 F
µ
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10 F
µ
µ
µ
SDA
SCL
InA1
InA2
InA3
InA4
InA5
InA7
InA8
InA9
OutA1
OutA2
OutA3
InA6
– 1 –
NJW1110
! ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER
SYMBOL
RATING
16
UNIT
V
Power Supply Voltage
V+
VIM
0 to V+( )
V
Maximum input voltage
Power Dissipation
800
PD
mW
°C
NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
-40 to +85
-40 to +125
°C
(
)For the maximum input voltage less than V+.
! RECOMMENDED OPERATING CONDITIONS (Ta=25°C)
PARAMETER
Operating Voltage
SYMBOL
V+
TEST CONDITION
-
MIN.
7.5
TYP.
9.0
MAX.
15.0
UNIT
V
! ELECTRICAL CHARACTERISTICS
♦ Power Supply (Ta=25°C, V+=9V)
PARAMETER
Supply Current
Reference Voltage
SYMBOL
TEST CONDITION
MIN.
4.0
TYP.
8.0
MAX.
12.0
5.0
UNIT
MA
V
ICC
No Signal
No Signal
VREF
4.0
4.5
♦ AC CHARACTERISTICS (Ta=25°C, V+=9V, VIN=0dBV (0dBV=1Vrms), f=1kHz, RL=47k
Ω)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
6.0
(2.0)
8.0
(2.5)
dBV
(Vrms)
Maximum Output Voltage
Voltage Gain 1
VOM
GV1
THD=1%
-
1.0
7.0
0.02
-
-
-1.0
0
dB
%
Voltage Gain 2
GV2
VIN=200mVrms, Gain=6dB
BW=400Hz-30kHz
5.0
6.0
Total Harmonic Distortion 1
Total Harmonic Distortion 2
Total Harmonic Distortion 3
Output Noise
THD1
THD2
THD3
VNO
-
-
-
-
-
-
-
-
0.001
0.003
f=10kHz, BW=400Hz-30kHz
V+=12V, BW=400Hz-30kHz
Rg=0Ω, A-Weighted
Rg=0Ω, A-Weighted
Rg=0Ω, f=20kHz
0.0007
-
-116
(1.6)
-106
(5.0)
dBV
(µVrms)
Cross Talk 1
CT1
CT2
CS1
CS2
-110
-90
-
-
-
-
dB
Cross Talk 2
Channel Separation 1
Channel Separation 2
Rg=0Ω, A-Weighted
Rg=0Ω, f=20kHz
-110
-90
dB
BW: Band Width
♦ Logic Control Characteristics (Ta=25°C, V+=9V)
PARAMETER
High Level Input Voltage
Low Level Input Voltage
SYMBOL
TEST CONDITION
ADR Terminal
ADR Terminal
MIN.
2.5
0
TYP.
MAX.
V+
UNIT
V
VADRH
-
-
VADRL
1.5
– 2 –
NJW1110
! I2C BUS BLOCK CHARACTERISTICS (SDA,SCL)
Standard mode : I2C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
Fast mode : I2C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 50pF (Connected to GND)
Standard mode
MIN. TYP. MAX. MIN.
Fast mode
TYP. MAX.
PARAMETER
SYMBOL
UNIT
Low Level Input Voltage
VIL
VIH
0.0
2.7
-
-
-
-
-
1.5
5.0
-
0.0
2.7
0.25
0
-
-
-
-
1.5
5.0
-
V
V
V
V
High Level Input Voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage (3mA at SDA pin)
Vhys
VOL
0
0.4
0.4
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed
by the input filter
20
tof
tSP
Ii
-
-
-
-
-
250
-
-
-
-
250
50
ns
ns
µA
+0.1Cb
0
Input current each I/O pin with an input voltage
between 0.1VDD and 0.9VDDmax
-10
10
-10
10
Capacitance for each I/O pin
SCL clock frequency
Ci
fSCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
pF
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
V
100
400
Hold time (repeated) START condition.
Low period of the SCL clock
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
4.0
4.7
4.0
4.7
0
-
0.6
1.3
0.6
0.6
0
-
-
-
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
-
-
-
-
-
-
Data set-up time
250
-
-
100
-
-
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the Low level
Noise margin at the High level
1000
300
tf
-
300
-
300
tSU:STO
tBUF
4.0
4.7
-
-
0.6
1.3
-
-
-
-
Cb
400
400
VnL
0.5
-
0.5
-
VnH
1
-
1
-
V
Cb; total capacitance of one bus line in pF.
NOTE). Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge.
SCL
tBUF
tR
tF
tHD:STA
tSU:STA
tSU:STO
tHD:STA tLOW
tHD:DAT
tHIGH
tSU:DAT
Sr
P
S
P
– 3 –
NJW1110
! PIN CONFIGURATION
32
1
2
InA1
InA2
InA3
InA4
InA5
InA6
InA7
InA8
InA9
GND
OutA1
InB1
InB2 31
30
3
InB3
4
InB4 29
InB5 28
InB6 27
5
6
26
25
InB7
InB8
7
8
InB9 24
Vref 23
9
10
11
OutB1
22
21
20
12 OutA2
OutB2
OutB3
OutA3
GND
SDA
SCL
13
14
15
GND 19
18
ADR
V+ 17
16
No. Symbol
Function
No. Symbol
Function
1
InA1
InA2
InA3
InA4
InA5
InA6
InA7
InA8
InA9
GND
OutA1
OutA2
OutA3
GND
SDA
SCL
Ach Input 1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V+
ADR
GND
OutB3
OutB2
OutB1
Vref
Power Supply Terminal
2
Ach Input 2
Ach Input 3
Ach Input 4
Ach Input 5
Ach Input 6
Ach Input 7
Ach Input 8
Ach Input 9
Slave address setting terminal
GND Terminal
Bch Output 3
Bch Output 2
Bch Output 1
Reference Voltage
Bch Input 9
3
4
5
6
7
8
InB9
InB8
InB7
InB6
InB5
InB4
InB3
InB2
InB1
9
Bch Input 8
10
11
12
13
14
15
16
GND Terminal
Ach Output 1
Ach Output 2
Ach Output 3
GND Terminal
Bch Input 7
Bch Input 6
Bch Input 5
Bch Input 4
Bch Input 3
SDA Data Input (I2C BUS)
SCL Clock Input (I2C BUS)
Bch Input 2
Bch Input 1
– 4 –
NJW1110
! DEFINITION OF I2C REGISTER
♦ I2C BUS FORMAT
MSB
LSB MSB
LSB MSB
LSB
S
1bit
Slave Address
A
1bit
Select Address
A
1bit
Data
8bit
A
P
8bit
8bit
1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
♦ SLAVE ADDRESS
MSB
LSB
94H(ADR=Low)
96H(ADR=High)
1
1
0
0
0
0
1
1
0
0
1
1
0
1
R/W
R/W
R/W=0: Receive Only
R/W=0: Write mode for register setting
R/W=1: Not available
♦ CONTROL REGISTER TABLE
The select address and sets each function.
The auto increment function cycles the select address as follows.
00H→01H→02H→00H
BIT
Select
Address
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
Variable Gain Buffer for OUT1
Variable Gain Buffer for OUT2
Variable Gain Buffer for OUT3
Input selector for OUT1
Input selector for OUT2
Input selector for OUT3
♦ CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
BIT
Select
Address
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
00H
01H
02H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
– 5 –
NJW1110
! INPUT SELECTOR
" INPUT SELECTOR SETTING (OUT1:00H, OUT2:01H, OUT3:02H)
Signal Select
D3
D2
D1
D0
Mute
0
0
0
0
InA1/InB1
InA2/InB2
InA3/InB3
InA4/InB4
InA5/InB5
InA6/InB6
InA7/InB7
InA8/InB8
InA9/InB9
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
! VARIABLE GAIN BUFFER
" VARIABLE GAIN BUFFER SETTING (OUT1:00H, OUT2:01H, OUT3:02H)
Gain (dB)
D7
0
0
0
0
0
0
0
0
1
1
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
D5
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
– 6 –
NJW1110
! APPLICATION CIRCUIT
V+
InB1
InB2
InB3
InB4
InB5
InB6
InB7
InB8
InB9
OutB1
OutB2
OutB3
ADR
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10 F
µ
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10
F
10
F
+
µ
µ
µ
µ
+
+
+
+
+
+
+
+
+
+
+
+
+
100
F
µ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
MUTE
Gain
Gain
Gain
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
Vref
50KΩX18
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
2
I C
Control
Logic
MUTE
GND
10
GND
14
1
2
3
4
5
6
7
8
9
11
12
13
15
16
+
+
+
+
+
+
+
+
+
+
+
+
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10 F
µ
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10 F
µ
µ
µ
SDA
SCL
InA1
InA2
InA3
InA4
InA5
InA7
InA8
InA9
OutA1
OutA2
OutA3
InA6
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
– 7 –
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