NJW4814MLE [NJRC]
HALF BRIDGE BASED PRPHL DRVR,;
| 型号： | NJW4814MLE |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | HALF BRIDGE BASED PRPHL DRVR, 驱动 接口集成电路 |
| 文件： | 总16页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW4814
Dual H-Bridge Driver with Boost Converter
GENERALDESCRIPTION
■ PACKAGE OUTLINE
The NJW4814 is a dual H-bridge driver with boost converter IC.
It can boost the output voltage from Li-ion battery and/or a 5V power
supply and drives a piezo device by two H- bridge drivers.
48ms of internal fixed soft start function of the boost circuit sets a limit
to startup current.
NJW4814MLE
The dual H-bridge drivers have independent signal inputs and a fault
output function, therefore the NJW4814 improves controllability from a
microcomputer.
The input frequency of H-bridge driver is up to 300kHz.
FEATURES
Boost Converter Block
Output Switch Voltage
Switching Current
40V max.
1.5Amin.
PWM Control
Operating Voltage Range
Oscillation Frequency Range
Soft Start Function
2.7 to 5.5V
380k to 1MHz
48ms typ.
Over Current Protection
Over Voltage Protection
H-Bridge Driver Block
Internal 2 Channel H-Bridge
Each Channel Operates Individually
Over Current Protection
Operating Voltage Range
Switching Frequency
300mAtyp.
7.0 to 35V
300kHz max.
Output Shut Down Control
Fault Indicator Output
Under Voltage Lockout
Built-in Thermal Shutdown
Standby Function
Package Outline
NJW4814MLE : EQFN24-LE
Ver.2015-04-07
- 1 -
NJW4814
PIN CONFIGURATION
PIN FUNCTION
1. IN-
13. OUTA1
14. PGND
15. OUTB1
16. VDD_HB
17. VOVP
18. OUTB2
19. SW
20. PGND
21. RADJ
22. FB
18 17 16 15 14 13
2. VDD_SW
3. STBYb
4. SHDNAb
5. SHDNBb
6. INA1
7. INA2
8. INB1
9. INB2
10. FLT
12
11
10
9
SW
PGND
RADJ
19
20
21
OUTA2
PGND
FLT
FB 22
RT 23
INB2
8
INB1
11. PGND
12. OUTA2
23. RT
24. GND
7
GND 24
INA2
1
2
3
4
5
6
Exposed PAD on
backside connect to GND
< Top View>
NJW4814MLE
Ver.2015-04-07
- 2 -
NJW4814
BLOCK DIAGRAM
UVLO
VDD_SW
Standby
ON/OFF
STBYb
FB
SW
PWM
ERR.AMP
Oscillator
IN-
Buffer
RADJ
Vref 1.0V
Soft Start
Thermal
Shutdown
OVP
OCP
VOVP
RT
VDD_HB
FLT
High Side
Gate Driver
High Side
Gate Driver
UVLO
OUTA1
OUTA2
INA1
Low Side
Gate Driver
Low Side
Gate Driver
Control
Logic
SHDNAb
Control
Logic
INA2
OCP
High Side
High Side
Gate Driver
Gate Driver
OUTB1
OUTB2
INB1
Control
Logic
Low Side
Low Side
SHDNBb
Gate Driver
Gate Driver
Control
Logic
INB2
GND
PGND
Ver.2015-04-07
- 3 -
NJW4814
ABSOLUTE MAXIMUM RATINGS
PARAMETER
(Ta=25°C)
UNIT
SYMBOL
MAXIMUM RATINGS
Boost Converter Block
Supply Voltage
SW pin Voltage
RADJ pin Voltage
IN- pin Voltage
STBYb pin Voltage
VOVP pin Voltage (*2)
VDD_SW
VSW
VRADJ
VIN-
VSTBYb
VOVP
-0.3 to +6
-0.3 to +40
-0.3 to +6 (*1)
-0.3 to +6 (*1)
-0.3 to +6 (*1)
-0.3 to +40
V
V
V
V
V
V
H-Bridge Driver Block
Supply Voltage
SHDNAb, SHDNBb pin
Voltage
VDD_HB
VSHDNAb
VSHDNBb
-0.3 to +40
V
V
-0.3 to +6 (*1)
INA1, INA2, INB1, INB2 pin
Voltage
VINA1 , VINA2
VINB1 , VINB2
-0.3 to +6 (*1)
V
General
FLTpin Voltage
VFLT
PD
-0.3 to +6
V
910 (*3)
2,100 (*4)
-40 to +150
-40 to +85
-40 to +150
Power Dissipation
mW
Junction Temperature Range
Operating Temperature Range
Storage Temperature Range
Tj
Topr
Tstg
C
C
C
(*1): When Supply voltage is less than +6V, the absolute maximum voltage is equal to the Supply voltage.
(*2): VOVP pin should be connected to VDD_HB pin.
(*3): Mounted on glass epoxy board. (101.5×114.5×1.6mm: based on EIA/JEDEC standard, 2Layers FR-4, with Exposed Pad)
(*4): Mounted on glass epoxy board. (101.5×114.5×1.6mm: based on EIA/JEDEC standard, 4Layers FR-4, with Exposed Pad)
(For 4Layers:Applying 99.5×99.5mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD51-5)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Boost Converter Block
Supply Voltage
STBYb pin Voltage
Timing Resistor
VDD_SW
VSTBYb
RT
2.7
0
68
380
－
–
100
700
5.5
VDD_SW
200
V
V
k
Oscillating Frequency
fOSC
1,000
kHz
H-Bridge Driver Block
Supply Voltage
Output Switch DC Current
SHDNAb, SHDNBb pin
Voltage
IN1A, IN1B, IN2A, IN2B pin
Voltage
FLTpin Voltage
VDD_HB
IOM
7
0
–
20
35
–
V
mA
VSHDNAb
VSHDNBb
VINA1 , VINA2
VINB1 , VINB2
VFLT
0
–
VDD_SW
V
0
0
–
–
VDD_SW
5.5
V
V
Ver.2015-04-07
- 4 -
NJW4814
ELECTRICALCHARACTERISTICS
Boost Converter Block
(Unless otherwise noted, VDD_SW=VSTBYb=3.7V, RT=100k , Ta=25 C)
PARAMETER
SYMBOL
TESTCONDITION
MIN.
TYP.
MAX.
UNIT
Under Voltage Lockout Block
UVLO Release Voltage
UVLO Operate Voltage
UVLO Hysteresis Voltage
VRUVLO_SW
VDUVLO_SW
VUVLO_SW
2.1
2.0
–
2.4
2.2
0.2
2.7
2.5
–
V
V
V
VRUVLO_SW - VDUVLO_SW
Soft Start Block
Soft StartTime
TSS
VB=0.95V
34
48
60
ms
Oscillator Block
Oscillation Frequency
fOSC
fDV
630
–
700
1
770
–
kHz
%
RT=100k
Oscillation Frequency
deviation (Supply voltage)
Oscillation Frequency
deviation (Temperature)
VDD_SW=3.0V to 5.5V
fDT
–
3
–
%
Ta= -40 C to +85 C
ErrorAmplifier Block
Reference Voltage
Input Bias Current
IN- pin Clamp Voltage
Short IN- and FB,
Measuring IN- Pin
VB=1.0V
VSTBYb=0V, VDD_SW=5.5V,
ICLIN-=10 A
VB
IB
-1.0%
-0.1
1.00
–
+1.0%
+0.1
5.6
V
A
V
VCLIN-
4.8
5.2
RADJ pin
FET ON Resistance
RADJ pin
FETLeak Current
RON_RADJ IRADJ=10mA
–
–
6
–
12
1
ILEAK_RADJ VSTBYb=0V, VRADJ=3.3V
A
PWM Comparate Block
Maximum Duty Cycle
MAXDUTY VIN-=0.9V
90
93
98
%
Output Block
Switching FET
ON Resistance
RON_SW
ISW=100mA
–
0.6
1.2
Switching Current Limit
Switching FET Leak Current
ILMT_SW
ILEAK_SW
1.5
–
2
–
–
1
A
A
VSTBYb=0V, VSW=40V
Overvoltage Protection Block
OVP Operate Voltage
OVP Release Voltage
VDOVP
VROVP
ΔVOVP
36
31
–
38
33
5
40
35
–
V
V
V
OVP Hysteresis Voltage
VDOVP -VROVP
VOVP= VDD_HB=35V,
OVP Release
VOVP= VDD_HB=40V,
OVP Operate
VSTBYb=0V,
VOVP= VDD_HB=40V
OVP pin Input Current 1
OVP pin Input Current 2
OVP pin Leak Current
IOVP1
IOVP2
–
1,200
–
60
2,400
–
120
4,000
1
A
A
A
IOVP_LEAK
Ver.2015-04-07
- 5 -
NJW4814
ELECTRICALCHARACTERISTICS
H-Bridge Driver Block
(Unless otherwise noted, VDD_SW=VSTBYb=VSHDNAb=VSHDNBb=3.7V, VDD_HB=25V, RT=100k , Ta=25 C)
INA1, INA2, INB1, INB2 pin, OUTA1, OUTA2, OUTB1, OUTB2 pin and SHDNAb, SHDNBb pin are common
PARAMETER
SYMBOL
TESTCONDITION
VRUVLO_HB - VDUVLO_HB
VIN = 3.3 V
MIN.
TYP.
MAX.
UNIT
Under Voltage Lockout Block
UVLO Release Voltage
UVLO Operate Voltage
UVLO Hysteresis Voltage
VRUVLO_HB
VDUVLO_HB
VUVLO_HB
5.6
5.0
–
6.2
5.6
0.6
6.8
6.2
–
V
V
V
Input Block
IN pin High Voltage
IN pin Low Voltage
IN pin Input Current
VIHIN
VILIN
IIIN
1.0
0
–
–
–
VDD_SW
0.4
V
V
A
–
1
SHDNb pin High Voltage
(Operating Mode)
SHDNb pin Low Voltage
(Shutdown Mode)
SHDNb pin
VIHSHDNb
VILSHDNb
RPDSHDNb VSHDNb=3.3V
1.0
0
–
–
VDD_SW
0.4
V
V
k
210
300
390
Pull-down Resistance
Output Block
High Side SW ON Resistance
Low Side SW ON Resistance
RDSH
RDSL
IOSOURCE=20mA
IOSINK=20mA
4.0
4.0
6.0
6.0
8.0
8.0
High Side
Over Current Detection
Low Side
Over Current Detection
Output RiseTime
IDCTH
IDCTL
High-Side
Low-Side
200
200
300
300
400
400
mA
mA
tr
tf
VIN=0 to 3.3V
VIN=0 to 3.3V
VIN=0 to 3.3V
VIN=0 to 3.3V
VIN=0 to 3.3V
VIN=0 to 3.3V
–
–
–
–
–
–
–
400
340
200
180
310
270
–
–
–
ns
ns
Output FallTime
Rise Dead Time
Fall Dead Time
Rise DelayTime
Fall DelayTime
Input Frequency
Dtr
–
ns
Dtf
–
ns
td_ON
td_OFF
fIN
–
ns
–
ns
300
kHz
High Side SW
OFF Leak Current
Low Side SW
OFF Leak Current
OUT pin – VDD pin
Potential Difference
GND pin – OUTpin
Potential Difference
VSTBYb=VSHDNb=0V,
VOUT=0V
VSTBYb=VSHDNb=0V,
VOUT=25V
VSTBYb=VSHDNb=0V,
IORH=20mA
VSTBYb=VSHDNb=0V,
IORL=20mA
IOLEAKOUTH
IOLEAKOUTL
VPDOV
–
–
–
–
–
1
A
A
–
1
0.7
0.7
1.0
1.0
V
VPDGO
V
Ver.2015-04-07
- 6 -
NJW4814
ELECTRICALCHARACTERISTICS
General Characteristics
(Unless otherwise noted, VDD_SW=VSTBYb=VSHDNAb=VSHDNBb=3.7V, VDD_HB=25V, RT=100k , Ta=25 C)
INA1, INA2, INB1, INB2 pin, OUTA1, OUTA2, OUTB1, OUTB2 pin and SHDNAb, SHDNBb pin are common
PARAMETER
SYMBOL
TESTCONDITION
MIN.
TYP.
MAX.
UNIT
STBYb pin High Voltage
(Operating Mode)
STBYb pin Low Voltage
(Standby Mode)
STBYb pin
Pull Down Resistance
VIHSTBYb
1.0
–
VDD_SW
V
VILSTBYb
0
–
0.4
V
k
RPDSTBYb VSTBYb=3.3V
210
300
390
FLTpin
Low Level Output Voltage
FLTpin OFF Leak Current
Quiescent Current
(Switching Regulator Block)
Quiescent Current
(H-Bridge Driver Block)
Quiescent Current
(Standby)
VLFLT
IOLEAKFLT VFLT=5.5V
–
–
–
0.20
–
0.40
1
V
A
IFLT=500 A
IQSW
IQHB
No Load
1.9
2.8
mA
fINA= fINB=10kHz
–
–
1.0
1.6
2.0
3.6
mA
A
antiphase 50% Duty Cycle
VSTBYb=VSHDNb=0V
VDD_HB=0V,
IQSTBY
Ver.2015-04-07
- 7 -
NJW4814
TYPICAL CHARACTERISTICS (Boost Converter Block)
Oscillation Frequency vs. Timing Resistor
Oscillation Frequency vs. Temperature
(VDD_SW=3.7V, Ta=25ºC)
(VDD_SW=3.7V, RT=100kW)
1000
800
780
760
740
720
700
680
660
640
620
600
900
800
700
600
500
400
300
60
80
100 120 140 160 180 200
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Timing Resistor RT (kW)
Output ON Resistance vs. Temperature
(VDD_SW=3.7V, ISW=100mA)
Reference Voltage vs. Temperature
(VDD_SW=3.7V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Ambient Temperature Ta (ºC)
Switching Current Limit vs. Temperature
(VDD_SW=3.7V)
3
2.5
2
1.5
1
0.5
0
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Ver.2015-04-07
- 8 -
NJW4814
TYPICAL CHARACTERISTICS (H-Bridge Driver Block)
High Side SW ON Resistance vs. Temperature
Low Side SW ON Resistance vs. Temperature
(VDD_HB=25V, IOSINK=20mA)
(VDD_HB=25V, IOSOURCE=20mA)
12
12
10
8
10
8
6
6
4
4
2
2
0
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Ambient Temperature Ta (ºC)
High Side Over Current Detection vs. Temperature
(VDD_HB=25V)
400
Low Side Over Current Detection vs. Temperature
(VDD_HB=25V)
400
350
300
250
200
150
100
50
350
300
250
200
150
100
50
0
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Ambient Temperature Ta (ºC)
Output Rise Time vs. Temperature
(VDD_HB=25V, VIN=0 to 3.3V)
Output Fall Time vs. Temperature
(VDD_HB=25V, VIN=0 to 3.3V)
600
500
400
300
200
100
0
600
500
400
300
200
100
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Ambient Temperature Ta (ºC)
Ver.2015-04-07
- 9 -
NJW4814
TYPICAL CHARACTERISTICS (General Characteristics)
Quiescent Current vs. Supply Voltage
Quiescent Current vs. Temperature
(RT=100kW, No Load, Ta=25ºC)
(VDD_SW=3.7V, RT=100kW, No Load)
3
3
2.5
2
Switching Regulator Block
Switching Regulator Block
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
2
3
4
5
6
-50 -25
0
25 50 75 100 125 150
Supply Voltage VDD_SW (V)
Ambient Temperature Ta (ºC)
Quiescent Current vs. Supply Voltage
(VDD_SW=3.7V, fINA=fINB=10kHz, Ta=25ºC)
Quiescent Current vs. Temperature
(VDD_SW=3.7V, VDD_HB=25V, fIN1=fIN2=10kHz)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
H-Bridge Driver Block
H-Bridge Driver Block
0
5
10 15 20 25 30 35 40
Supply Voltage VDD_HB (V)
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Quiecent Current vs. Input Frequency
Standby Current vs. Temperature
(VDD_SW=3.7V, VDD_HB=25V, Ta=25˚C)
(VDD_SW=3.7V, VDD_HB=0V, VSTBYb=VSHDNb=0V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10
9
8
7
6
5
4
3
2
1
0
H-Bridge Driver Block
0
50
100
150
200
250
300
-50 -25
0
25 50 75 100 125 150
Input Frequency fIN (kHz)
Ambient Temperature Ta (ºC)
Ver.2015-04-07
- 10 -
NJW4814
H-Bridge Driver Block Pin Operation Table
Ach
INPUT
OUTPUT
SHDNAb
Low
INA1
INA2
*
*
OUTA1
OUTA2
Hi-Z
*
*
Low
High
*
Hi-Z
Low
High
*
High
High
High
High
*
*
Low
High
Low
High
*
*
* Don’t Care
Bch
INPUT
OUTPUT
SHDNBb
Low
INB1
INB2
*
*
OUTB1
Hi-Z
Low
High
*
OUTB2
Hi-Z
*
*
Low
High
*
High
High
High
High
*
*
Low
High
Low
High
*
*
* Don’t Care
Ver.2015-04-07
- 11 -
NJW4814
Timing Chart
tr
tf
INA1
90 %
INA2
10 %
INB1
INB2
OUTA1
OUTA2
90 %
90 %
UTB1
10 %
10 %
OUTB2
td_ON
td_OFF
Fig. 1. Output Rise/Fall Time, Rise/Fall DelayTime
High
Low
INA1, INA2,
INB1, INB2
VDD_HB
ON
OFF
ON
OFF
ON
Highside SW Gate
(IC internal)
Lowside SW Gate
(IC internal)
OFF
ON
OFF
ON
OFF
PGND
VDD_HB
PGND
90 %
10 %
OUTA1, OUTA2,
OUTB1, OUTB2
90 %
tr
10 %
tf
Dead-time
Dtr
Dead-time
Dtf
Dead-time
Dtr
Dead-time
Dtf
Dead-time
Dtr
Dead-time
Dtf
Fig. 2. H-Bridge Driver Block
Ver.2015-04-07
- 12 -
NJW4814
PIN DESCRIPTIONS
PIN NAME
PIN
NUMBER
FUNCTION
Output Voltage Detecting pin.
1
Connects output voltage through the resistor divider tap to this pin in order to voltage
of the IN- pin become 1.0V (typ.).
IN-
Power Supply pin for SW.REG. block.
2
3
Insert a bypass capacitor close to the VDD_SW pin – the GND pin connection in
order to lower high frequency impedance.
Standby Control pin.
The STBYb pin is pulled down with 300k (typ.) internally. Normal Operation at the
time of High Level. Standby Mode at the time of Low Level or OPEN.
Shutdown Control pin for H-Bridge driverAch.
The SHDNAb pin is pulled down with 300k (typ.) internally.
Normal Operation at the time of High Level.
VDD_SW
STBYb
4
SHDNAb
The FETof H-Bridge driverAch becomes OFF (Hi-Z) by Low Level or OPEN.
Shutdown Control pin for H-Bridge driver Bch.
The function is same as 4pin.
Control input pin for H-Bridge driverAch (one side).
High Side SW Operation at the time of High Level. Low Side SW Operation at the
time of Low Level.
5
6
SHDNBb
INA1
Control input pin for H-Bridge driverAch (one side).
The function is same as 6pin.
Control input pin for H-Bridge driver Bch (one side).
The function is same as 6pin.
Control input pin for H-Bridge driver Bch (one side).
The function is same as 6pin.
7
8
9
INA2
INB1
INB2
FLTpin outputs a signal at the time of abnormality.
You should be connected to the outside power supply through pull up resistance.
Normally: FET is OFF (Output voltage High Level)
Abnormality: FET is ON (Output voltage Low Level)
Power GND pin for H-Bridge driver (Note 1)
10
FLT
11
12
PGND
Output pin of H-Bridge driverAch (one side).
The output current is limited to 300mA(typ.) by the overcurrent protection function.
OUTA2
Output pin of H-Bridge driverAch (one side).
The function is same as 12pin.
Power GND pin for H-Bridge driver (Note 1)
Output pin of H-Bridge driver Bch (one side).
13
14
15
OUTA1
PGND
OUTB1
The function is same as 12pin.
Ver.2015-04-07
- 13 -
NJW4814
PIN DESCRIPTIONS (Continued)
PIN
PIN NAME
FUNCTION
Power Supply pin for H-Bridge driver block.
NUMBER
16
Insert a bypass capacitor close to the VDD_HB pin – the GND pin connection in
order to lower high frequency impedance.
VDD_HB
Overvoltage detection pin of SW.REG.
When it detected overvoltage, the VOVP pin sinks a current and discharges the
output voltage.
VOVP pin should be connected to VDD_HB pin.
Output pin of H-Bridge driver Bch (one side).
The function is same as 12pin.
17
18
VOVP
OUTB2
19
20
Switch Output pin for SW.REG. Power MOSFET
SW
Power GND pin for SW.REG. (Note 1)
PGND
The RADJ pin becomes the high impedance at standby.
It prevents a current flowing into the output voltage setting resistor.
Feedback Setting pin
21
RADJ
22
The feedback resistor and capacitor are connected between the FB pin and the IN-
pin.
FB
Oscillating Frequency Setting pin byTiming Resistor.
Oscillating Frequency should set between 380kHz and 1MHz.
GND pin (Note 1)
23
24
–
RT
GND
Exposed
PAD
Connect to GND.
(Note 1) GND and PGND are connected inside.
Ver.2015-04-07
- 14 -
NJW4814
H Bridge Driver Block Over Current Protection
The overcurrent protection function operates when the high side SW current flows more than IDCTH or the low side SW
current flows more than IDCTL. The overcurrent protection operates in three steps.
(1) Sensing step
·Turn off power MOSFETof the switching regulator
·Turn off power MOSFETof the H-bridge driver
·Reset a soft start
·Reset an FB pin voltage
·Connect a dummy road between VOVP pin-GND pin
(2) Output stop step
After the overcurrent detection, 500 ms (typ.) continues an output stop.
(3) Return step
After an output stop, the soft start operates. Then the IC operation shifts to normal operation.
Ver.2015-04-07
- 15 -
NJW4814
APPLICATION EXAMPLE
L1
3.3
H
D1
VOUT
VIN
R4
100
C6
0.1
C3
4.7
C1
10
C2
0.1
R2
240 k
F
F
F
F
C5
1,500 pF
VDD_SW
RT
SW
R1
10 k
R5
100 k
IN-
R3
100
C4
22 nF
STBYb
Stand-by
FB
NJW4814
SHDNAb
Shutdown
(H-Bridge Driver Ach.)
RADJ
Shutdown
(H-Bridge Driver Bch.)
SHDNBb
RON_RADJ
VDD_HB
VOVP
INA1
INA2
INB1
INB2
INA1
INA2
INB1
INB2
R2
240(k
10(k
)
VOUT
1
VB
1
1(V) 25.0(V)
R1
)
OUTA1
OUTA2
OUTB1
FLT
FAULT
Pull-Up
OUTB2
GND
PGND
R6
100 k
[CAUTION]
Thespecificationsonthisdatabookareonly
givenforinformation,withoutanyguarantee
asregardseither mistakesoromissions.The
applicationcircuitsinthisdatabookare
describedonlytoshowrepresentativeusages
oftheproductandnotintendedforthe
guaranteeorpermissionofanyrightincluding
theindustrialrights.
Ver.2015-04-07
- 16 -
相关型号：
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