SM5847 [NPC]
High-fidelity Digital Audio, Multi-function Digital Filter; 高端音响保真度数字音频，多功能数字滤波器
| 型号： | SM5847 |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | High-fidelity Digital Audio, Multi-function Digital Filter |
| 文件： | 总30页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5847AF
High-fidelity Digital Audio, Multi-function Digital Filter
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
The SM5847AF is a 4/8-times oversampling (inter-
polation), 2-channel, linear-phase FIR, multi-func-
tion digital filter for digital audio reproduction
equipment. It features independent left and right-
channel digital deemphasis filters and soft muting
function.
The internal system clock operates at either 192fs or
256fs selectable speed (where fs is the audio sam-
pling frequency). Plus, the divide-by 1, 2, or 4
counter settings means that external clocks of 768fs/
384fs/192fs (192fs input) and 1024fs/512fs/256fs
(256fs input) are supported.
The input/output interface supports input data in
16/18/20/24-bit words, and output data in
18/20/22/24-bit words in either 4-times or 8-times
oversampling selectable output mode.
The SM5847AF operates from a single 3 to 5 V sup-
ply, and is available in 44-pin QFP packages.
FEATURES
■ Left/right-channel (2-channel processing)
■ 4-times/8-times oversampling (interpolation)
• 8-times interpolation filter
- 3-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
• 2s complement, MSB first
• 3 selectable formats
- LR alternating, 16/18/20/24-bit serial, right-
justified data
- LR alternating, 24-bit serial, left-justified
data
- LR simultaneous, 24-bit serial, left-justified
data
2nd stage (2fs to 4fs): 29-tap
3rd stage (4fs to 8fs): 17-tap
- ≤ ±0.00002 dB passband ripple (0 to
0.4535fs)
■ Output data format
- ≥ 117 dB stopband attenuation (0.5465fs to
7.4535fs)
• 2s complement, MSB first, LR simultaneous
• 18/20/22/24-bit serial
• 4-times interpolation filter
- 2-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
- ≤ ±0.00002 dB passband ripple (0 to
0.4535fs)
• BCKO burst (NPC format)
■ Dither round-off processing
• Dither round-off ON/OFF selectable
■ 25-bit internal data word length
■ Internal system clock
• 192fs/256fs selectable
- ≥ 116 dB stopband attenuation (0.5465fs to
3.4535fs)
■ Digital deemphasis
• Maximum operating frequency
192fs mode: 37 MHz max (5 V)
20.7 MHz max (3 V)
• IIR filter configuration
256fs mode: 27.6 MHz max (5 V)
25 MHz max (3 V)
■ Jitter-free function
• Jitter-free/Sync mode selectable
■ Crystal oscillator circuit built-in
■ 3 to 5 V supply
• fs = 32kHz, 44.1kHz, 48kHz
• 2-channel independent ON/OFF control
■ 26 × 24-bit parallel multiplier/32-bit accumulator
■ Overflow limiter
■ Soft muting
• 2-channel independent ON/OFF control
■ Input data format
■ 44-pin plastic QFP
■ CMOS process
ORDERING INFORMATION
De vice
Packag e
SM5847AF
44-pin QFP
NIPPON PRECISION CIRCUITS—1
SM5847AF
PINOUT
(Top View)
1
2
33
32
31
30
29
28
27
26
25
24
23
OMD
DOR
DOL
RSTN
SYNCN
OW2N
OW1N
VDD
3
4
WCKO
BCKO
VSS
5
6
VSS
7
VSSAC
VDDAC
VDD
IW2N/DIR
IW1N/DIL
INF1N
CKSLN
NC
8
9
10
11
DG
NC
PACKAGE DIMENSIONS
(Unit: mm)
44-pin plastic QFP
+
12.80 0.30
−
+
10.00 0.30
−
(1.40)
+
0.60 0.20
−
+
0.35 0.10
−
0.20 M
0.80
0.15
NIPPON PRECISION CIRCUITS—2
SM5847AF
BLOCK DIAGRAM
XTI
IW1N/DIL
IW2N/DIR
INF1N
XTO
Input Data
Interface
CKO
System
Clock
CKSLN
CKDV1
CKDV2
DITHN
SYNCN
RSTN
VDD
VSS
Filter and
Attenuation
Arithmetic
Block
Timing
Controller
VDDAC
VSSAC
DEMPL
DEMPR
Deemphasis
Controller
FSEL1
FSEL2
OMD
Output Data
Interface
Block
OW1N
MUTEL
MUTER
Mute
Controller
OW2N
DG
NIPPON PRECISION CIRCUITS—3
SM5847AF
PIN DESCRIPTION
Nu mb e r
1
Na me
OMD
I/O
Des cription
1
Ip
Output data rate (4fs/8fs) select pin
Right-channel data output
Left-channel data output
W ord clock output
2
2
DOR
O
2
3
DOL
O
2
4
WCKO
BCKO
VS S
O
2
5
O
Bit clock output
6
–
–
–
–
Ground
7
VS S AC
VDDAC
VDD
Ground
8
Supply voltage
9
Supply voltage
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DG
O
Deglitched signal output
No internal connection (must be open)
Master clock output
NC
–
2
CKO
O
VS S
–
–
O
I
Ground
VDD
Supply voltage
XTO
Oscillator output
XTI
Oscillator input/master clock input
Ground
VS S
–
–
VDD
Supply voltage
1
I
LRCI
Input data sample rate (fs) clock input
Data input/input format select pin 2
Bit clock input
1
I
DI/INF2N
BCKI
1
I
NC
–
–
No internal connection (must be open)
No internal connection (must be open)
NC
2
CKS LN
INF1N
IW1N/DIL
IW2N/DIR
VS S
Ip
Master clock frequency (192fs/256fs) select pin
Input format select pin 1
2
Ip
1
Ip
Input data word length select pin 1/left-channel data input
Input data word length select pin 2/right-channel data input
Ground
1
Ip
–
VDD
–
Supply voltage
2
OW1N
OW2N
S YNCN
RS TN
CKDV1
CKDV2
DEMP R
DEMP L
VDD
Ip
Output data word length select pin 1
Output data word length select pin 2
Sync mode select pin
2
Ip
2
Ip
1
Ip
Reset input
1
Ip
Internal system clock frequency divider set pin 1
Internal system clock frequency divider set pin 2
Right-channel deemphasis ON/OFF pin
Left-channel deemphasis ON/OFF pin
Supply voltage
1
Ip
1
Ip
1
Ip
–
–
VS S
Ground
1
FSEL1
FSEL2
MUTEL
MUTER
DITHN
Ip
Deemphasis filter sample rate (fs) select pin 1
Deemphasis filter sample rate (fs) select pin 2
Left-channel mute ON/OFF pin
Right-channel mute ON/OFF pin
Output data dither ON/OFF pin
1
Ip
1
Ip
1
Ip
1
Ip
1. Schmitt input, TTL level
2. TTL level
Ip = Pull-up input
NIPPON PRECISION CIRCUITS—4
SM5847AF
SPECIFICATIONS
Absolute Maximum Ratings
V
= V
= 0 V, V = V
SS
SSAC DD DDAC
Parameter
Symbol
, V
Condition
Rating
Unit
V
1
Supply voltage range
Input voltage range
V
−
0.3 to 6.5
DD DDAC
V
V
−
0.3 to V +
DD
0.3
V
I
S S
Storage temperature range
T
−55 to 125
°C
stg
≤ 70
≤ 85
°
°
C
900
Power dissipation
P
m W
D
C
700
1. Supply lines for VDD and VDDAC, and ground lines for VSS and VS S AC, should be connected on the printed circuit board to prevent device break-
down due to potential difference when the power is applied.
Recommended Operating Conditions
V
= V
= 0 V, V = V
DDAC
SS
SSAC
DD
Parameter
Symbol
, V
Rating
Unit
1
Supply voltage range
V
3.00 to 5.25
V
DD DDAC
Operating temperature range
T
−40 to 85
°C
a
1. The minimum required operating voltage and consequent operating temperature vary with the maximum operating frequency and sampling mode
selected, as shown in the following table.
V
= V
= 0 V, V = V
SS
SSAC DD DDAC
Internal s ys tem clock
Ma ximum operating
Sampling frequency
fs (kHz)
Minimum s upply voltag e
Operating temperature
C)
1
V
, V
(V)
T (°
a
DD DDAC
Mo d e
frequency (MHz)
192fs
256fs
192fs
256fs
192fs
256fs
192fs
256fs
37
4.75 (5.0
−
5%)
−
40 to 70
192
Not guaranteed
Not guaranteed
Not guaranteed
20.7
27.6
18.5
25
3.00 (3.3
4.50 (5.0
3.00 (3.3
3.00 (3.3
3.00 (3.3
3.00 (3.3
−
−
−
−
−
−
10%)
10%)
10%)
10%)
10%)
10%)
2
108
96
−40 to 85
10.6
14.2
3
55.2
1. Mode with internal frequency divider ratio set to 1 (CKDV1 = CKDV2 = LOW).
2. 96 kHz + 12.5% variable pitch
3. 48 kHz + 15% variable pitch
NIPPON PRECISION CIRCUITS—5
SM5847AF
DC Electrical Characteristics
V
= V
= 3.00 to 5.25 V, V = V
= 0 V, T = −40 to 85 °C
DD
DDAC
SS
SSAC
a
Rating
Parameter
Symbol
Condition
Unit
min
0.7V
typ
–
ma x
1
HIGH-level input voltage
HIGH-level input voltage
V
V
–
–
–
–
V
V
IH1
DD
2,4
2.0
2.4
2.0
–
–
IH2
V
V
V
V
V
V
V
V
V
V
= V
= V
= V
= V
= V
= V
= V
= V
= 4.75 to 5.25 V
= 3.00 to 4.75 V
= 4.75 to 5.25 V
= 3.00 to 4.75 V
= 4.75 to 5.25 V
= 3.00 to 4.75 V
= 4.75 to 5.25 V
= 3.00 to 4.75 V
–
DD
DD
DD
DD
DD
DD
DD
DD
DDAC
DDAC
DDAC
DDAC
DDAC
DDAC
DDAC
DDAC
3
HIGH-level input voltage
V
V
V
V
V
IH3
–
–
0.3V
DD
1
LOW -level input voltage
LOW -level input voltage
LOW -level input voltage
V
V
V
IL1
IL2
IL3
–
–
0.2V
DD
–
–
0.8
0.2V
2,4
3
–
–
DD
–
–
0.8
0.2V
–
–
DD
1,2
Input leakage current
I
= 0 to 5.25 V
= 0 V
−10
–
10
µA
µA
V
IL1
IN
IN
3,4
Input current
I
−10
−50
−120
IL2
5
HIGH-level output voltage
V
I
=
−
4 mA
= 4 mA
OL
2.4
–
–
–
–
OH
OH
5
LOW -level output voltage
V
I
0.4
V
OL
1. Pin XTI
2. Pins LRCI, DI/INF2N, BCKI
3. Pins IW1N/DIL, IW2N/DIR
4. Pins OMD, CKSLN, INF1N, OW1N, OW2N, SYNCN, RSTN, CKDV1, CKDV2, DEMPR, DEMPL, FSEL1, FSEL2, MUTEL, MUTER, DITHN
5. Pins DOR, DOL, WCKO, BCKO, DG, CKO
V
= V
= 4.75 to 5.25 V, V = V
= 0 V, T = −40 to 85 °C, XTI = external input, no output load
DD
DDAC
SS
SSAC
a
Rating
Parameter
Symbol
Condition
Unit
min
typ
ma x
192fs, XTI = 27 ns (37 MHz),
fs = 192 kHz,T 40 to 70 °C
I
–
–
166
mA
mA
mA
mA
mA
DD1
=
−
a
256fs, XTI = 40 ns (25 MHz),
fs = 96 kHz
I
–
–
–
–
–
–
–
–
115
105
95
DD2
384fs, XTI = 27 ns (37 MHz),
fs = 96 kHz, estimated value
Current consumption
I
DD3
192fs, XTI = 54 ns (18.5 MHz),
fs = 96 kHz, estimated value
I
DD4
384fs, XTI = 54 ns (18.5 MHz),
fs = 48 kHz, estimated value
I
65
DD5
V
= V
= 3.00 to 3.60 V, V = V
= 0 V, T = −40 to 85 °C, XTI = external input, no output load
DD
DDAC
SS
SSAC
a
Rating
Parameter
Symbol
Condition
Unit
min
typ
ma x
256fs, XTI = 81 ns (12.3 MHz),
fs = 48 kHz, estimated value
I
–
–
27
mA
mA
DD6
Current consumption
384fs, XTI = 54 ns (18.5 MHz),
fs = 48 kHz, estimated value
I
–
–
28
DD7
NIPPON PRECISION CIRCUITS—6
SM5847AF
AC Electrical Characteristics
Crystal oscillator (XTI, XTO)
V
= V
= 3.00 to 5.25 V, V = V
= 0 V, T = −40 to 85 °C
DD
DDAC
SS
SSAC
a
Rating
typ
Parameter
Symbol
Condition
Unit
min
ma x
1
Oscillator frequency
f
–
–
50
MHz
OS C
1. External circuit components should be matched for the crystal oscillator element used.
External clock input (XTI)
V
= V
= 3.00 to 5.25 V, V = V
= 0 V, T = −40 to 85 °C
DD
DDAC
SS
SSAC
a
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
ma x
60
Master clock frequency
Master clock duty
f
MHz
%
XTI
1/2V thresholds
40
–
60
DD
Internal system clock
The crystal oscillator frequency or external clock input master clock frequency ratings are described in the pre-
ceding tables, but it is the internal system clock frequency rating, set by the internal frequency divider
(CKDV1, CKDV2), that must be satisfied. The master clock frequency is a multiple of the sampling frequency
fs.
CKDV1 = CKDV2 = LOW (internal system clock frequency = XTI input frequency),
V
= V
= 0 V, T = −40 to 85 °C
SS
SSAC a
Rating
typ
Parameter
Symbol
Condition
Unit
min
ma x
256fs (CKSLN = LOW, CKDV1 = LOW, CKDV2 = LOW)
V
V
= V
= V
= 4.50 to 5.25 V
0.256
0.256
–
–
27.6
25
DD
DDAC
System clock frequency
f
MHz
S YS 1
= 3.00 to 5.25 V
DD
DDAC
192fs (CKSLN = HIGH, CKDV1 = LOW, CKDV2 = LOW)
V
= V
= 4.75 to 5.25 V,
°C
DD
=
DDAC
0.384
0.384
–
–
37
T
−40 to 70
a
System clock frequency
f
MHz
S YS 2
V
= V = 3.00 to 5.25 V
DDAC
20.7
DD
NIPPON PRECISION CIRCUITS—7
SM5847AF
Serial input timing (BCKI, LRCI, DI/INF2N, IW1N/DIL, IW2N/DIR)
V
= V
= 0 V, T = −40 to 85 °C
SS
SSAC a
Rating
Parameter
Symbol
Condition
Unit
min
55
80
100
25
35
45
25
35
45
10
20
30
10
20
30
10
20
30
10
20
30
typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ma x
–
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
BCKI pulse cycle
t
–
ns
IBCY
–
–
BCKI HIGH-level pulsewidth
BCKI LOW-level pulsewidth
DI, DIL, DIR setup time
t
–
ns
ns
ns
ns
ns
ns
BCWH
–
–
t
–
BCWL
–
–
t
–
DS
–
–
DI, DIL, DIR hold time
t
–
DH
–
–
Last BCKI rising edge to LRCI edge
LRCI edge to first BCKI rising edge
t
–
BL
–
–
t
–
LB
–
1. CKSLN = HIGH (192fs), V
2. CKSLN = LOW (256fs), V
= V
= 4.75 to 5.25 V, T = −40 to 70 °C
a
DD
DD
DDAC
DDAC
= V
= V
= 4.50 to 5.25 V
= 3.00 to 4.75 V
= 3.00 to 4.50 V
CKSLN = HIGH (192fs), V
DD
DD
DDAC
DDAC
3. CKSLN = LOW (256fs), V
= V
tIBCY
1.5V
BCKI
tBCWH
tBCWL
DI
DIL
DIR
1.5V
tDS
tDH
tLB
tBL
1.5V
LRCI
NIPPON PRECISION CIRCUITS—8
SM5847AF
Reset timing (RSTN)
= V = 3.00 to 5.25 V, V = V
V
= 0 V, T = −40 to 85 °C
DD
DDAC
SS
SSAC
a
Rating
typ
Parameter
Symbol
Condition
Unit
1
min
2t
ma x
RSTN LOW-level reset pulsewidth
t
–
–
ns
RS T
MCK
1.
t
is equal to 1/f
or 1/f
. For example, t
= 54 ns when f
= 37 MHz.
MCK
XTI
OS C
RS T
XTI
1.5V
RSTN
tRST
Output timing (CKO, BCKO, WCKO, DOL, DOR, DG)
V
= V
= 4.75 to 5.25 V, V = V
= 0 V, T = −40 to 70 °C, C = 50 pF
DD
DDAC
SS
SSAC
a
L
Rating
typ
Parameter
Symbol
Condition
Unit
min
ma x
4
–
9
ns
ns
XTI falling edge to CKO falling edge delay
t
XTO
V
= V
= 3.00 to 5.25 V,
DD
DDAC
4
–
–
11
2
T
= −40 to 85 °C
a
BCKO falling edge to WCKO, DOL, DOR,
DG delay
t
−4
ns
BDO
BCKO rising edge to WCKO falling edge
WCKO falling edge to BCKO rising edge
BCKO period
t
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WOH
Output mode: 8fs
OMD = HIGH (fs = 192 kHz)
External clock input:
XTI = 27 ns (37 MHz),
CKSLN = HIGH (192fs)
Divider ratio: 1
CKDV1 = CKDV2 = LOW
Output data length: 24 bits
OW1N = OW2N = LOW
t
8
WOS
t
27
7
OBCY
BCKO HIGH-level pulsewidth
BCKO LOW -level pulsewidth
DOL, DOR setup time
t
OBCH
t
7
OBCL
t
7
ODS
DOL, DOR hold time
t
7
ODH
BCKO rising edge to WCKO falling edge
WCKO falling edge to BCKO rising edge
BCKO period
t
17
17
54
18
18
18
18
WOH
Output mode: 4fs
OMD = LOW (fs = 192 kHz)
External clock input:
XTI = 27 ns (37 MHz),
CKSLN = HIGH (192fs)
Divider ratio: 1
CKDV1 = CKDV2 = LOW
Output data length: 24 bits
OW1N = OW2N = LOW
t
WOS
t
OBCY
BCKO HIGH-level pulsewidth
BCKO LOW -level pulsewidth
DOL, DOR setup time
t
OBCH
t
OBCL
t
ODS
DOL, DOR hold time
t
ODH
NIPPON PRECISION CIRCUITS—9
SM5847AF
V
= V
= 4.50 to 5.25 V, V = V
= 0 V, T = −40 to 85 °C, C = 50 pF
DD
DDAC
SS
SSAC
a
L
Rating
Parameter
Symbol
Condition
Unit
min
10
10
11
11
26
26
27
27
typ
–
ma x
BCKO HIGH-level pulsewidth
BCKO LOW -level pulsewidth
DOL, DOR setup time
t
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
External clock input: XTI = 36 ns
(27.6 MHz), CKSLN = LOW
(256fs), fs = 108 kHz
Divider ratio: 1
CKDV1 = CKDV2 = LOW
Output mode: 8fs, OMD = HIGH
OBCH
t
–
OBCL
t
–
ODS
DOL, DOR hold time
t
–
ODH
BCKO HIGH-level pulsewidth
BCKO LOW -level pulsewidth
DOL, DOR setup time
t
–
External clock input: XTI = 36 ns
(27.6 MHz), CKSLN = LOW
(256fs), fs = 108 kHz
Divider ratio: 1
CKDV1 = CKDV2 = LOW
Output mode: 4fs, OMD = LOW
OBCH
t
–
OBCL
t
–
ODS
DOL, DOR hold time
t
–
ODH
1.5V
1.5V
XTI
CKO
tXTO
BCKO
1.5V
1.5V
WCKO
DOL
DOR
DG
tBDO
WCKO
BCKO
1.5V
1.5V
tWOH
tWOS
tOBCL
tOBCH
tOBCY
DOL
DOR
1.5V
tODS
tODH
NIPPON PRECISION CIRCUITS—10
SM5847AF
Filter Characteristics
8-times interpolation filter
Parameter
Passband
Rating
0 to 0.4535fs
0.5465fs to 7.4535fs
≤ ±0.00002 dB
≥ 117 dB
Stopband
Passband ripple
Stopband attenuation
Group delay
Constant
8fs filter response with deemphasis OFF
0
20
40
60
80
100
120
140
0.0
1.0
2.0
4.0
5.0
6.0
7.0
8.0
3.0
Frequency (× fs)
8fs filter band transition response with deemphasis OFF
-0.00008
-0.00004
0.00000
0.00004
0.00008
0.000
0.125
0.250
0.375
0.500
Frequency (× fs)
8fs filter passband response with deemphasis OFF
0
20
40
60
80
100
120
140
0.440
0.465
0.490
0.515
0.540
0.565
0.590
0.615
0.640
Frequency
(× fs)
NIPPON PRECISION CIRCUITS—11
SM5847AF
4-times interpolation filter
Parameter
Passband
Rating
0 to 0.4535fs
0.5465fs to 3.4535fs
≤ ±0.00002 dB
≥ 116 dB
Stopband
Passband ripple
Stopband attenuation
Group delay
Constant
4fs filter response with deemphasis OFF
0
20
40
60
80
100
120
140
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Frequency (× fs)
4fs filter band transition response with deemphasis OFF
-0.00008
-0.00004
0.00000
0.00004
0.00008
0.000
0.125
0.250
0.375
0.500
Frequency (× fs)
4fs filter passband response with deemphasis OFF
0
20
40
60
80
100
120
140
0.440
0.465
0.490
0.515
0.565
0.590
0.615
0.640
0.540
Frequency (× fs)
NIPPON PRECISION CIRCUITS—12
SM5847AF
Deemphasis filter
Sampling frequency (fs)
44.1 kHz
Parameter
32 kHz
48 kHz
Passband bandwidth (kHz)
0 to 14.5
0 to 20.0
0 to 21.7
Attenuation
Phase,
≤ ±0.01 dB
Deviation from ideal characteristic
θ
0 to 1.5°
Passband response with deemphasis ON
0
2
0
32kHz
-20
-40
-60
Phase
44.1kHz
48kHz
4
Attenuation
6
8
32kHz
44.1kHz
48kHz
10
10
20
50
100
200
500
1k
2k
5k
10k
20k
[Hz]
Frequency (Hz)
NIPPON PRECISION CIRCUITS—13
SM5847AF
FUNCTIONAL DESCRIPTION
Oversampling (Interpolation)
The interpolation arithmetic block is comprised of 3
cascaded, 2-times FIR interpolation filters, as shown
in figure 1. The input signal is sampled at rate fs, and
then either 4-times or 8-times oversampling data is
output. Sampling noise in the 0.5465fs to 3.4535fs
(4fs output) or 0.5465fs to 7.4535fs (8fs output)
region is removed.
Input
fs
2-times interpolator
1st FIR
169-tap
2fs
2-times interpolator
2nd FIR 29-tap
4fs
Deemphasis IIR filter
Deemphasis OFF
Deemphasis ON
4fs
Soft mute
4fs
2 -times interpolator
3rd FIR 17-tap
8fs
4fs
Output
Figure 1. Arithmetic operating block
NIPPON PRECISION CIRCUITS—14
SM5847AF
Digital Deemphasis (DEMPL, DEMPR, FSEL1, FSEL2)
Most deemphasis filters are constructed using analog
circuit techniques. Here, an IIR filter is employed to
faithfully reproduce the gain and phase characteris-
tics of standard analog deemphasis filters, corre-
Filter coefficient select (FSEL1, FSEL2)
Table 2. Deemphasis filter coefficient select
FSEL1
LOW
FSEL2
LOW
Sampling frequency (fs)
44.1 kHz
sponding
to
analog
50µs/15µs
frequency
characteristics. Three sets of filter coefficients for the
three fs = 32/44.1/48 kHz sampling frequencies are
supported. Deemphasis for other values of fs are not
supported.
LOW
HIGH
LOW
48 kHz
HIGH
HIGH
Prohibited mode
32 kHz
HIGH
Deemphasis ON/OFF (DEMPL, DEMPR)
Deemphasis for the left and right-channel can be
controlled independently.
Table 1. Deemphasis control
DEMP L
LOW
HIGH
×
DEMP R
×
Deemphas is
Left-channel OFF
Left-channel ON
Right-channel OFF
Right-channel ON
×
LOW
HIGH
×
Soft Muting (MUTEL, MUTER)
The muting function controls the muting of left and
right-channel independently. Input data continues to
be accepted even when mute is operating.
Mute operation at reset
When RSTN goes LOW, the DOL and DOR outputs
are immediately muted to −∞ dB. When RSTN goes
HIGH, reset is released and the outputs are immedi-
ately set to 0 dB attenuation.
Mute ON/OFF
When MUTEL (MUTER) goes HIGH, the attenua-
tion changes smoothly from 0 to −∞ dB. Similarly,
when MUTEL (MUTER) goes LOW, muting is
released and the attenuation changes smoothly from
−∞ to 0 dB. This operation is termed soft muting.
Note that even when either MUTEL or MUTER or
both are HIGH, the reset operation takes precedence.
Soft muting takes an interval of approximately
512/fs, or about 11.6 ms when fs = 44.1 kHz.
Table 3. Mute control
MUTEL
LOW
HIGH
×
MUTER
×
Soft muting
Left-channel OFF
Left-channel ON
Right-channel OFF
Right-channel ON
×
LOW
HIGH
×
NIPPON PRECISION CIRCUITS—15
SM5847AF
Analog Output Click Noise
Under the following conditions, a click noise may be
output from the DAC (digital-to-analog converter)
connected to the SM5847AF.
■ When the audio data input mode, set by INF1N,
DI/INF2N, IW1N/DIL, and IW2N/DIR, is
switched
■ When the SYNCN jitter-free mode switch timing
exceeds the internal timing delay limit
■ When a system reset on RSTN occurs
■ When the internal system clock mode, set by
CKSLN, CKDV1, and CKDV2, is switched
■ When the deemphasis mode, set by DEMPL,
DEMPR, FSEL1, and FSEL2, is switched
An external muting circuit connected to the analog
output may be required to eliminate this noise.
DI/INF2N,
IW1N/DIL, IW2N/DIR
Normal operation
MUTEL/MUTER
RSTN
H
L
H
L
soft mute
soft mute
H
L
H
L
512/fs
512/fs
reset
reset
0dB
Gain
−∞
+FS
zero
-FS
External DAC
analog output
(full scale signal)
click noise
FS: full scale
Figure 2. Soft muting/reset operation
NIPPON PRECISION CIRCUITS—16
SM5847AF
Internal System Clock (XTI, XTO, CKO, CKSLN, CKDV1, CKDV2)
Table 4. Internal system clock select
The SM5847AF supports two system clock frequen-
cies selected by CKSLN, 192fs and 256fs, where fs
is the sampling frequency.
CKS LN
LOW
Sys tem clock
256fs
The master clock can be provided either by a crystal
oscillator connected between XTI and XTO, or by an
external master clock input on XTI. Note that the
feedback resistor required by the oscillator option is
not built-in. External components should be selected
to match the crystal oscillator element. Note also that
XTO must be left open (floating) for the external
master clock input option.
HIGH
192fs
Table 5. System clock frequency divider ratio select
Divider
ratio
CKDV1
CKDV2
Mas ter clock
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
1
–
4
2
192fs, 256fs
Prohibited mode
768fs, 1024fs
384fs,512fs
Note that even though it is necessary that the master
clock and LRCI clock (sampling frequency fs) be in
sync, it is not necessary that they be exactly in-phase
(see jitter-free mode description).
The SM5847AF features independent divide-by 1, 2,
or 4counter, selected by CKDV1 and CKDV2. This
provides the 192fs or 256fs system clock with the
necessary divider ratios to support master clocks
with frequencies of 768fs, 384fs, 192fs, 1024fs,
512fs or 256fs.
Divider
Normal sampling frequencies 32 kHz, 44.1 kHz,
48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz
are supported. However, some combinations of sam-
pling frequency and master clock frequency are not
supported, as follows.
16
XTI
15
12
SM5847AF
XTO CKO
R1
Master Clock
Buffer output
XTAL
C1
C2
■ 768fs and 1024fs at 88.2 and 96 kHz
■ 768fs, 384fs, 1024fs, 512fs, and 256fs at
176.4 kHz
■ 768fs, 384fs, 1024fs, 512fs and 256fs at 192 kHz
Figure 3. Crystal oscillator connection
Note also that the internal crystal oscillator circuit
cannot operate at frequencies ≥ 50 MHz. The master
clock input on XTI is output on CKO.
Divider
Master clock stop operation
The master clock is input after power is applied.
But if, after the XTI and LRCI clocks are input and
power-ON reset occurs with all-zero input audio
data, the master clock input on XTI is held either
HIGH or LOW level, operation effectively stops.
Note also that a reset signal is not accepted when the
master clock and LRCI clock stop.
16
15
12
CKO
SM5847AF
XTI
External Clock
XTO
XTO : open
Master Clock
Buffer output
Figure 4. External clock connection
NIPPON PRECISION CIRCUITS—17
SM5847AF
Table 6. Master clock frequency example
XTI s ys tem clock frequency (MHz)
CKSLN = HIGH (192fs )
CKSLN = LOW (256fs )
Sampling
frequency
fs (kHz)
CKDV1
LOW
CKDV2
LOW
CKDV1
HIGH
CKDV2
HIGH
CKDV1
HIGH
CKDV2
LOW
CKDV1
LOW
CKDV2
LOW
CKDV1
HIGH
CKDV2
HIGH
CKDV1
HIGH
CKDV2
LOW
192fs
384fs
768fs
256fs
512fs
1024fs
32
44.1
48
6.144
8.4627
9.216
12.288
16.9344
24.576
33.8688
8.192
11.2896
16.384
22.5792
32.768
45.1584
18.432
36.864
12.288
24.576
49.152
1
88.2
96
16.9344
18.432
33.8688
36.864
33.8688
Not guaranteed
22.5792
45.1584
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
36.864
Not guaranteed
Not guaranteed
24.576
49.152
176.4
192
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
1
Not guaranteed
1. Refer to the AC characteristics system clock ratings.
System Reset (RSTN)
During normal device operation, reset signals are not
required. However, the SM5847AF must be reset
under the following conditions.
When RSTN is LOW, the DOL and DOR outputs are
tied LOW, muting the output signal to an attenuation
level of −∞.
■ At power-ON
After system reset, when RSTN goes HIGH, the
arithmetic and output timing counters are reset on
the first LRCI start edge, assuming that the XTI and
LRCI input clocks have already stabilized. The LRCI
start edge is determined by the state of INF1N and
INF2N. When INF1N is LOW or when both INF1N
and INF2N are HIGH, the start edge is the rising
edge. When INF1N is HIGH and INF2N is LOW, the
start edge is the falling edge.
■ When the LRCI clock and internal operation tim-
ing need to be resynchronized in jitter-free mode.
■ After the LRCI or XTI clocks, or both, stop and
are subsequently started.
The system is reset by applying a LOW-level pulse
on RSTN.
RSTN=L
RSTN
LRCI
Internal reset
OMD=H
8fs
WCKO
OMD=L
4fs
zero
DOL/DOR
Figure 5. System reset timing and output muting (INF1N = LOW or INF1N = INF2N = HIGH)
NIPPON PRECISION CIRCUITS—18
SM5847AF
Audio Data Input (INF1N, DI/INF2N, IW1N/DIL, IW2N/DIR, BCKI, LRCI)
The input data format and input pin functions are
selected by the state of INF1N and INF2N. When
INF1N is LOW, the inputs are left and right-channel
data inputs, and when INF1N is HIGH, the
DI/INF2N input is an input format select pin, and
DIL and DIR are the audio data inputs.
Input data format select
Table 7. Input settings and functions
Pin function s election
INF1N
DI/INF2N
Input format
DI/INF2N
IW1N/DIL
IW2N/DIR
LOW
LOW
HIGH
HIGH
−
−
1
LR alternating , right-justified data
DI
IW1N
IW2N
LOW
HIGH
LR alternating, left-justified data
INF2N
DIL
DIR
2
LR simultaneous , left-justified data
1. Alternating left-channel and right-channel data input on a single input DI.
2. Simultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.
Input data word length
Table 8. Input data word length select
The input data word length is selected by the state of
IW1N and IW2N when INF1N is LOW. 20-bit is
selected when INF1N is HIGH.
INF1N
IW1N/DIL
LOW
HIGH
LOW
HIGH
–
IW2N/DIR
LOW
LOW
HIGH
HIGH
–
Input word length
24 bits
20 bits
LOW
18 bits
16 bits
HIGH
24 bits
Jitter-free Function (SYNCN)
The arithmetic circuit and output control timing is
derived from the system clock, and is therefore inde-
pendent of the input LRCI and BCKI clocks.
Accordingly, any jitter in the data input clock (LRCI
and BCKI) does not cause jitter in the output.
resynchronized and all functions continue to operate
normally.
Sync mode (SYNCN = LOW)
When SYNCN is LOW, the timing error value is ±1
× (XTI master clock period), which is a much
smaller timing error tolerance than in jitter-free
mode. In this mode, the internal timing is guaranteed
to follow the LRCI clock timing within this toler-
ance, making this mode useful for systems con-
structed from a multiple number of SM5847AF
devices.
Generally, the internal timing is synchronized to the
LRCI input timing after a system reset release, when
RSTN goes from LOW to HIGH, on the first LRCI
clock start edge. If the input timing and LRCI start
edge timing subsequently drift, the input timing is
automatically resynchronized when the timing error
exceeds a certain value. There are 2 timing error val-
ues at which resynchronization occurs, selected by
the state of SYNCN.
Jitter-free mode (SYNCN = HIGH)
When SYNCN is HIGH, the timing error value is
±3/8 × (LRCI clock period). When the difference
between the input timing and LRCI start edge posi-
tion do not exceed this value, internal timing is not
NIPPON PRECISION CIRCUITS—19
SM5847AF
Audio Data Output (DOL, DOR, BCKO, WCKO, DG, OW1N, OW2N, OMD, DITHN)
Output data format
Output timing
The output data is in serial, simultaneous left and
right-channel, 2s complement, MSB first, BCKO
burst (NPC format) format. Left-channel data is out-
put on DOL, and right-channel data is output on
DOR.
The output timing is dependent on the CKSLN level
and output data word length.
When CKSLN is LOW, the output timing does not
change with the output data word length. However,
when CKSLN is HIGH, the DOL and DOR output
timing for 24-bit output data length (OW1N =
OW2N = LOW) start 1 clock cycle earlier than for
18, 20, or 22-bit output data length.
Output data word length
The output data word length is selected by the state
of OW1N and OW2N.
Table 9. Output data word length select
OW1N
LOW
OW2 N
LOW
Output word length
24 bits
HIGH
LOW
LOW
22 bits
HIGH
HIGH
20 bits
HIGH
18 bits
Table 10. Output timing
Parameter
Symbol
CKS LN
OMD = HIGH
1/192fs
OMD = LOW
1/96fs
HIGH
LOW
HIGH
LOW
Bit clock rate
T
B
1/256fs
1/128fs
24t
32t
48t
64t
S YS
S YS
S YS
S YS
Data word length
T
DW
Output mode
Output dither processing
The output mode, either 4fs oversampling or 8fs
oversampling, is selected by the level on OMD,
where fs is the input sampling rate.
The output data word length is set by OW1N and
OW2N, whereas the SM5847AF performs all inter-
nal calculations in 25-bit words. As a consequence,
dither processing is provided to round-off errors. The
SM5847AF uses triangular dither processing (trian-
gular probability density function or TPDF) and can
be turned ON or OFF. Simple round-off processing
occurs when dither is OFF (DITHN = HIGH).
Table 11. Output mode select
OMD
LOW
HIGH
Output mode
4fs
8fs
Table 12. Dither select
DITHN
LOW
Dither
ON
HIGH
OFF
NIPPON PRECISION CIRCUITS—20
SM5847AF
Group Delay
The data input to data output group delay is the delay
which occurs due to the digital filter calculations. It
is the time between the serial input data is com-
pletely read in (at rate fs) until the serial data is out-
put (at rate 8fs or 4fs, depending on the mode
selected).
t
represents the LRCI clock rising edge after
INPUT
the serial input data has been read in at rate fs.
t
represents the WCKO clock falling edge at
OUTPUT
the start of serial data output at rate 8fs or 4fs.
Table 13. Group delay
Mo d e
Group delay
Unit
CKS LN
S YNCN
t
− t
OUTP UT INPUT
LOW
HIGH
LOW
HIGH
After reset, or sync mode
Jitter-free mode
48.625/fs
LOW (256fs)
48.25/fs
−
49.0/fs
sec
After reset, or sync mode
Jitter-free mode
48.75/fs
HIGH (192fs)
48.375/fs
− 49.125/fs
1/fs
LRCI
serial data input (DI/INF2N,
IW1N/DIL, IW2N/DIR)
48/fs
tINPUT
LRCI
1/fs
WCKO
8fs
OMD=H
serial data output (DOL,DOR)
serial data output (DOL,DOR)
tOUTPUT
CKSLN=L
(256fs)
WCKO
4fs
OMD=L
tOUTPUT
WCKO
8fs
OMD=H
serial data output (DOL,DOR)
serial data output (DOL,DOR)
tOUTPUT
CKSLN=H
(192fs)
WCKO
4fs
OMD=L
tOUTPUT
Figure 6. Group delay timing (SYNCN = LOW)
NIPPON PRECISION CIRCUITS—21
SM5847AF
TIMING DIAGRAMS
Input Timing Examples
1 / fs
Lch
Rch
LRCI
BCKI
*1
16
1
16
1
16bit
DI/
MSB
LSB
MSB
LSB
Don't care
Don't care
INF2N
IW1N/DIL = H, IW2N/DIR = H
1
18
18
1
BCKI
18bit
20bit
24bit
MSB
LSB
MSB
LSB
DI/
INF2N
Don't care
Don't care
IW1N/DIL = L, IW2N/DIR = H
1
20
1
20
BCKI
MSB
MSB
LSB
LSB
DI/
INF2N
Don't care
Don't care
IW1N/DIL = H, IW2N/DIR = L
24
24
1
1
BCKI
MSB
LSB
MSB
LSB
DI/
INF2N
Don't care
Don't care
IW1N/DIL = L, IW2N/DIR = L
*1: Optional BCKI clock cycles
Figure 7. LR alternating, right-justified data, 2s complement, MSB first, INF1N = L
NIPPON PRECISION CIRCUITS—22
SM5847AF
1 / fs
Lch
Rch
LRCI
*1
1
24
1
24
BCKI
IW1N/DIL
IW2N/DIR
MSB
LSB
Don't care
Don't care
MSB
LSB
Don't care
Don't care
*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.
Figure 8. LR alternating, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = L, 24-bit
1 / fs
LRCI
1
24
* 1
BCKI
IW1N/DIL
IW2N/DIR
MSB
MSB
LSB
LSB
Don't care
Don't care
*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.
Figure 9. LR simultaneous, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = H, 24-bit
NIPPON PRECISION CIRCUITS—23
SM5847AF
Output Timing Examples
1 / 8fs
WCKO
18
LSB
LSB
1
BCKO
18bit
OW1N = H
OW2N = H
MSB
MSB
DOL
DOR
1
20
LSB
LSB
BCKO
20bit
MSB
MSB
OW1N = L
OW2N = H
DOL
DOR
1
22
LSB
LSB
BCKO
22bit
MSB
MSB
OW1N = H
OW2N = L
DOL
DOR
1
24
BCKO
MSB
MSB
24bit
OW1N = L
OW2N = L
LSB
LSB
DOL
DOR
DG
1
12
22
10
24
192fs
internal
system clock
TB
TDW
Figure 10. 2s complement, MSB first, CKSLN = H, OMD = H
NIPPON PRECISION CIRCUITS—24
SM5847AF
1 / 4fs
WCKO
BCKO
18
LSB
LSB
1
18bit
OW1N = H
OW2N = H
MSB
MSB
DOL
DOR
1
20
LSB
LSB
BCKO
20bit
MSB
MSB
OW1N = L
OW2N = H
DOL
DOR
1
22
LSB
LSB
BCKO
22bit
MSB
MSB
OW1N = H
OW2N = L
DOL
DOR
1
24
BCKO
MSB
MSB
24bit
OW1N = L
OW2N = L
LSB
LSB
DOL
DOR
DG
44
24
48
2
20
192fs
internal
system clock
TB
TDW
Figure 11. 2s complement, MSB first, CKSLN = H, OMD = L
NIPPON PRECISION CIRCUITS—25
SM5847AF
1 / 8fs
WCKO
BCKO
18
LSB
LSB
1
18bit
OW1N = H
OW2N = H
MSB
MSB
DOL
DOR
1
20
LSB
LSB
BCKO
20bit
MSB
MSB
OW1N = L
OW2N = H
DOL
DOR
1
22
LSB
LSB
BCKO
22bit
MSB
MSB
OW1N = H
OW2N = L
DOL
DOR
24
1
BCKO
MSB
MSB
24bit
OW1N = L
OW2N = L
LSB
LSB
DOL
DOR
DG
30
1
32
16
14
25
256fs
internal
system clock
TB
TDW
Figure 12. 2s complement, MSB first, CKSLN = L, OMD = H
NIPPON PRECISION CIRCUITS—26
SM5847AF
1 / 4fs
WCKO
BCKO
18
LSB
LSB
1
18bit
OW1N = H
OW2N = H
MSB
MSB
DOL
DOR
1
20
LSB
LSB
BCKO
20bit
MSB
MSB
OW1N = L
OW2N = H
DOL
DOR
1
22
LSB
LSB
BCKO
22bit
MSB
MSB
OW1N = H
OW2N = L
DOL
DOR
24
1
BCKO
MSB
MSB
24bit
OW1N = L
OW2N = L
LSB
LSB
DOL
DOR
DG
32
64
2
28
50
60
256fs
internal
system clock
TB
TDW
Figure 13. 2s complement, MSB first, CKSLN = L, OMD = L
NIPPON PRECISION CIRCUITS—27
SM5847AF
TYPICAL APPLICATION (1)
This circuit shows a basic connection to a 24-bit
input DAC (SM5865BM).
(Note that certain circuit details required for good
DAC analog output characteristics have been omit-
ted.)
36.864 MHz external clock, 48/96/192 kHz sam-
pling rate fs, 24-bit data, 8fs oversampling operation
+5V
36.864MHz
fs
SM5865BM
AVSSA
1
DVSS
24
+5V
24-bit Data
Bit Clock
DI
RAP 23
2
3
I/V Converter
BCKI
IOUTA 22
21
20
19
WCKI IOUTAN
4
5
6
7
8
9
20 19 18 17 16 15 14 13 12
22 21
IWSL
RAN
23
RSTN AVDDA
11
10
9
24
TSTN AVDDB 18
CKSLN
TO
RBP
17
25
VDD
VDDAC
VSSAC
VSS
INF1N
IW1N/DIL
IW2N/DIR
VSS
I/V Converter
26
27
28
29
30
31
32
33
8
DVDD
IOUTB 16
10 CKI
IOUTBN
15
7
14
13
6
11 CKDVN
RBN
SM5847AF
5
CVSS AVSSB
BCKO
WCKO
DOL
12
VDD
4
OW1N
OW2N
AVSSA
DVSS
3
1
24
23
2
DI
RAP
DOR
2
3
I/V Converter
OMD
1
BCKI
IOUTA 22
21
WCKI IOUTAN
4
5
6
7
8
9
34 35 36 37 38 39 40 41 42 43 44
IWSL
RSTN AVDDA
TSTN AVDDB 18
RAN 20
19
CKDV1
CKDV2
OMD
TO
RBP
17
I/V Converter
DVDD
IOUTB 16
10 CKI
IOUTBN
RBN
15
14
13
11 CKDVN
RSTN
CVSS AVSSB
12
SM5865BM
Figure 14. SM5847AF and SM5865BM connection
Table 14. Operating mode select
Internal s ys tem clock frequency divider ratio select
CKSLN = HIGH (192fs )
Sampling
frequency
fs (kHz)
External
clock XTI
(MHz)
Output mode s elect
Mo d e
768fs
384fs
192fs
CKDV1
HIGH
HIGH
LOW
CKDV2
LOW
Divider
OMD
Output mode
48
96
4
2
1
HIGH
HIGH
HIGH
8fs
8fs
8fs
HIGH
LOW
36.864
192
NIPPON PRECISION CIRCUITS—28
SM5847AF
TYPICAL APPLICATION (2)
This circuit shows a basic connection to a 24-bit
input DAC (Burr-Brown PCM1704U).
operation (Note that certain circuit details required
for good DAC analog output characteristics have
been omitted.)
36.864 MHz external clock, 48/96/192 kHz sam-
pling rate fs, 24-bit data, 8fs or 4fs oversampling
36.864MHz
fs
+5V
-5V
24-bit Data
Bit Clock
1
20
19
18
17
16
15
14
DATA
BCLK
-VCC
20 19 18 17 16 15 14 13 12
22 21
2
3
4
5
6
7
8
9
23
24
25
26
27
28
29
30
31
32
33
11
10
9
PCM1704U
-VDD
CKSLN
INF1N
IW1N/DIL
IW2N/DIR
VSS
VDD
VDDAC
VSSAC
DGND AGND
8
DD
AGND
IOUT
+V
7
I/V Converter
WCLK
6
VSS
13
12
11
SM5847AF
5
BCKO
WCKO
DOL
20BIT
VDD
4
10 INVERT +VCC
OW1N
OW2N
3
1
2
20
19
18
17
16
15
DOR
DATA
BCLK
-VCC
OMD
1
2
3
PCM1704U
34 35 36 37 38 39 40 41 42 43 44
4
DD
-V
5
DGND AGND
+VDD AGND
6
CKDV1
CKDV2
OMD
7
OUT 14
I
WCLK
I/V Converter
8
13
12
9
20BIT
11
CC
10
+V
INVERT
RSTN
+5V
Figure 15. SM5847AF and Burr-Brown PCM1704U connection
Table 15. Operating mode select
Internal s ys tem clock frequency divider ratio select
CKSLN = HIGH (192fs )
Sampling
frequency
fs (kHz)
External
clock XTI
(MHz)
Output mode s elect
Mo d e
768fs
384fs
192fs
CKDV1
HIGH
HIGH
LOW
CKDV2
LOW
Divider
OMD
Output mode
48
96
4
2
1
HIGH
HIGH
LOW
8fs
8fs
4fs
HIGH
LOW
36.864
192
NIPPON PRECISION CIRCUITS—29
SM5847AF
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
NIPPON PRECISION CIRCUITS INC.
Facsimile: 03-3642-6698
NC9803DE 2000.2
NIPPON PRECISION CIRCUITS—30
相关型号：
©2020 ICPDF网 联系我们和版权申明