SM5879AV [NPC]
3rd-order , 2-channel D/A Converter; 3阶， 2路D / A转换器
| 型号： | SM5879AV |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | 3rd-order , 2-channel D/A Converter |
| 文件： | 总20页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5879AV
3rd-order Σ∆, 2-channel D/A Converter
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT (TOP VIEW)
The SM5879AV is a 3rd-order ∑∆, two-channel D/A
convertor LSI for digital audio reproduction equip-
ment. This device incorporate NPC's molybdenum-
gate CMOS technology and incorporates an 8-times
oversampling digital filter and analog 3rd-order ∑∆
post-converter low-pass filters.
1
24
LRCI
DVDD
BCKI
TEST
P / M
DI
AVDDR
RO
BB2 / BBON
BB1 / MDT
DEEM / MCK
MUTE / MLEN
XVDD
The SM5879AV also incorporates built-in digital
bass boost and deemphasis filters, an attenuator, and
soft mute function. Low-voltage operation is also
supported.
AVSSR
TO1
AVSSL
LO
XTO
XTI
This device features a compact 24-pin VSOP pack-
age and a D/A converter that provides both compact
size and low power consumption.
AVDDL
MUTEO
DVSS
XVSS
CKO
12
13
FEATURES
■ 2.7 to 3.3 V operating supply voltage
■ 44.1 kHz sampling frequency
■ 16.9344 MHz (384fs) system clock
■ Built-in crystal oscillator circuit
■ 16-bit, MSB first, rear-packed serial data input
format (≤ 64 fs bit clock)
PACKAGE DIMENSIONS
Unit: mm
24-pin VSOP
■ 8-times oversampling digital filter
• 32 dB stopband attenuation
• +0.05 to -0.05 dB passband ripple
■ Deemphasis filter operation
• 36 dB stopband attenuation
+ 0.05
0.15 − 0.02
7.8 ± 0.1
• -0.09 to +0.23 dB deviation from ideal deem-
phasis filter characteristics
■ Attenuator
• 7-bit attenuator (128 steps) set by microcontrol-
ler
■ Soft mute function set by parallel setting
• (approximately 1024/fs total muting time)
■ Mono setting
• Left or right channel mono selectable by micro-
controller
0 to 10
+0.1
−0.05
0.22
0.65
■ Built-in infinity-zero detection circuit
■ ∑∆, two-channel D/A converter
• 3rd-order noise shaper
ORDERING INFOMATION
• 32fs oversampling
Device
Package
■ Built-in 3rd-order post-converter low-pass filters
■ 24-pin VSOP package
SM5879AV
24pin VSOP
■ Molybdenum-gate CMOS process
NIPPON PRECISION CIRCUITS—1
SM5879AV
Theoretical Filter Characteristics
Deemphasis OFF overall characteristics
Frequency band
Attenuation (dB)
Parameter
Passband ripple
f
@ fs = 44.1 kHz
0 to 20.0 kHz
24.1 to 328.7 kHz
20.0 kHz
min
−0.05
32
typ
–
max
+0.05
–
0 to 0.4535fs
0.5465fs to 7.4535fs
0.4535fs
Stopband attenuation
–
Built-in analog LPF compensation
–
−0.34
–
Overall frequency characteristic (deemphasis OFF)
0
10
20
30
40
50
60
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (Fs)
Passband characteristic (deemphasis OFF)
0.0
0.2
0.4
0.6
0.8
0.000
0.125
0.250
0.375
0.4535
0.500
Frequency (Fs)
NIPPON PRECISION CIRCUITS—2
SM5879AV
Deemphasis ON overall characteristics
Frequency band
@ fs = 44.1 kHz
Attenuation (dB)
typ
Parameter
f
min
max
Deviation from ideal deemphasis filter
characteristics
0 to 0.4535fs
0 to 20.0 kHz
−0.09
–
+0.23
Stopband attenuation
0.5465fs to 7.4535fs
0.4535fs
24.1 to 328.7 kHz
20.0 kHz
36
–
–
–
–
Built-in analog LPF compensation
−0.34
Overall frequency characteristic (deemphasis ON)
0
10
20
30
40
50
60
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequncy (Fs)
Passband characteristic (deemphasis ON)
0
2
4
6
8
10
12
0.000
0.125
0.250
0.375
0.4535
0.500
Frequncy (Fs)
NIPPON PRECISION CIRCUITS—3
SM5879AV
PIN DESCRIPTION
Number
Name
DVDD
TEST
P/M
I/O
I-
I
Description
1
2
Digital supply pin.
Input for testing LSI. Test mode when HIGH.
3
I
Parallel/microcontroller setting selection pin. Parallel setting when HIGH.
Right-channel analog supply pin.
Right channel analog output pin.
Right-channel analog ground pin.
Test mode output. Normally LOW.
Left-channel analog ground pin.
Left-channel analog output pin.
4
AVDDR
RO
-
5
O
-
6
AVSSR
TO1
7
O
-
8
AVSSL
LO
9
O
O
O
-
10
11
12
13
14
15
16
17
AVDDL
MUTEO
DVSS
CKO
Left-channel analog supply pin.
Infinity-zero detection output
Digital ground pin
O
-
Oscillator clock output. 16.9344 MHz.
Crystal oscillator ground pin
XVSS
XTI
I
Crystal oscillator or 16.9344-MHz external clock input pin
Crystal oscillator output pin
XTO
O
-
XVDD
Crystal oscillator supply pin
P/M=H; soft mute control pin. Mute is active when HIGH.
P/M=L; microcontroller interface clock
18
19
20
21
MUTE/ MLEN
DEEM/ MCK
BB1/ MDT
I
I
P/M=H; deemphasis control pin. Deemphasis is ON when HIGH.
P/M=L; microcontroller interface clock
P/M=H; bass boost setting switch pin 1
P/M=L; microcontroller interface serial data
I
P/M=H; bass boost setting switch pin 2
P/M=L; bass boost detection output
BB2/ BBON
IO
22
23
24
DI
I
I
I
Serial data input pin
BCKI
LRCI
Bit clock input pin
Sample rate clock (fs) input pin. Left channel when HIGH, and right channel when LOW.
NIPPON PRECISION CIRCUITS—4
SM5879AV
BLOCK DIAGRAM
LRCI
BCKI
DI
Input interface
MUTEO
P /M
MUTE / MLEN
DEEM / MCK
BB1 / MDT
L
R
Microcontroller
interface
Filter & attenuation
operation block
BB2 / BBON
L
R
Timing
control
CKO
XVSS
XTO
XTI
DVSS
DVDD
TEST
L
R
PWM data
generation block
Noise shaper
operation block
XVDD
TO1
AVDDL
AVDDR
+
−
−
+
LO
AVSSL AVSSR
RO
NIPPON PRECISION CIRCUITS—5
SM5879AV
SPECIFICATIONS
Absolute Maximum Ratings
DV = AV
= AV = XV = 0 V, AV = AV
= AV
SS
SSL
SSR
SS
DD
DDL DDR
Parameter
Symbol
DV , AV , XV
DD
Rating
Unit
V
Supply voltage range
−0.3 to 7.0
DD
DD
1
Input voltage range
V
DV − 0.3 to DV + 0.3
V
IN1
SS
DD
XTI input voltage range
V
XV − 0.3 to XV + 0.3
V
IN
SS
DD
Storage temperature range
Power dissipation
T
−55 to 125
°C
mW
°C
s
stg
P
250
255
10
D
Soldering temperature
Soldering time
T
sld
t
sld
1. Pins TEST, P/ M, MUTE/ MLEN, DEEM/ MCK, BB1/ MDT, BB2/ BBON, DI, BCKI, LRCI
Also applicable during supply switching.
Recommended Operating Conditions
DV = AV
= AV
= XV = 0 V, AV = AV
= AV
SS
SSL
SSR
SS
DD
DDL DDR
Parameter
Symbol
DV , AV , XV
DD
Rating
Unit
Supply voltage range
2.7 to 3.3
V
DD
DD
DV − XV ,
DD
DD
DV − AV ,
DD
DD
XV − AV ,
DD
DD
Supply voltage variation
±0.1
V
DV − XV ,
SS
SS
DV − AV ,
SS
SS
XV − AV
SS
SS
Operating temperature range
T
−20 to 70
°C
opr
note) Since DVDD, XVDD, AVDDL, and AVDDR are connected via the LSI base board, current may flow if potential difference occurs among them.
NIPPON PRECISION CIRCUITS—6
SM5879AV
DC Electrical Characteristics
Rating
Parameter
DVDD digital supply current
Symbol
Condition
Unit
min
–
typ
3.70
0.55
0.68
–
max
7.40
1.10
1.36
–
1
I
mA
mA
mA
V
DDD
1
XVDD system clock supply current
I
–
DDX
1
2
AVDD analog supply current
I
–
DDA
XTI HIGH-level input voltage
XTI LOW-level input voltage
XTI AC-coupled input voltage
V
Clock input
Clock input
0.7XV
DD
IH1
V
–
–
0.3XV
V
IL1
DD
V
0.3XV
–
–
–
V
p-p
INAC
DD
3
HIGH-level input voltage
V
0.7DV
–
V
V
IH2
DD
3
LOW-level input voltage
V
–
–
0.3DV
DD
IL2
4
HIGH-level output voltage
V
I
= −0.5mA
DV − 0.4
–
–
V
OH
OH
DD
4
LOW-level output voltage
V
I
= 0.5mA
–
–
–
0.4
10
10
1.0
1.0
V
OL
OL
XTI HIGH-level input current
XTI LOW-level input current
I
V = XV
DD
4
µA
µA
µA
µA
IH1
IN
I
V = 0 V
–
4
IL1
IN
I
V = DV
DD
-1.0
-1.0
–
ILH
IN
3
Input leakage current
I
V = 0V
–
LL
IN
1. DV = AV = XV = 2.7V, XTI clock input frequency f = 16.9344 MHz, no output load.
DD
DD
DD
XTI
2. I is the total current.
DDA
3. Pins TEST, P/ M, MUTE/ MLEN, DEEM/ MCK, BB1/ MDT, BB2/ BBON, DI, BCKI, LRCI
4. Pins MUTEO, CKO, BB2/ BBON, TO1
NIPPON PRECISION CIRCUITS—7
SM5879AV
AC Electrical Characteristics
System clock (XTI)
Crystal Oscillator
Rating
typ
Parameter
Symbol
Unit
min
max
Oscillator frequency
f
10.0
16.9344
18.5
MHz
OSC
External clock input
Rating
typ
Parameter
Symbol
Unit
min
20.0
20.0
54.0
max
50
HIGH-level clock pulsewidth
LOW-level clock pulsewidth
Clock pulse cycle
t
29.5
29.5
59.0
ns
ns
ns
CWH
t
50
CWL
t
100
XI
XTI input clock
tXI
V
IH1
0.5V
DD
V
IL1
tCWL
tCWH
Serial input (BCKI, DI, LRCI)
Rating
Parameter
Symbol
Unit
min
50
typ
–
max
–
BCKI HIGH-level pulsewidth
BCKI LOW-level pulsewidth
BCKI pulse cycle
t
ns
ns
ns
ns
ns
ns
ns
BCWH
t
50
–
–
BCWL
t
6t
–
–
BCY
XI
DI setup time
t
50
–
–
DS
DI hold time
t
50
50
50
–
–
DH
Last BCKI rising edge to LRCI edge
LRCI edge to first BCKI rising edge
t
–
–
BL
t
–
–
LB
Serial input timing
BCKI
0.5VDD
tBCWH
tBCWL
tBCY
DI
0.5VDD
0.5VDD
tDS
tDH
LRCI
tLB
tBL
NIPPON PRECISION CIRCUITS—8
SM5879AV
Control input
P/M=H
Rating
Parameter
Symbol
Unit
min
–
typ
–
max
50
Rise time
Fall time
t
ns
ns
r
t
–
–
50
f
t
r
t
r
MUTE
DEEN
BB1
BB2
90%
10%
90%
10%
0.5VDD
Figure 1.
P/M=L
Rating
Parameter
Symbol
Unit
min
200
200
400
100
100
100
200
–
typ
–
max
–
MCK LOW-level pulsewidth
MCK HIGH-level pulsewidth
MCK pulse width
MDT setup time
MDT hold time
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCWL
t
–
–
MCWH
t
–
–
Mcy
t
–
–
MDS
t
–
–
MDH
MLEN setup time
MLEN hold time
Rise time
t
–
–
MLH
t
–
–
MLW
t
–
50
50
r
Fall time
t
–
–
f
0.5VDD
0.5VDD
MCK
MDT
tMCWH
tMCWL
tMCY
tMDS
tMDH
MLEN
0.5VDD
tMLS
tMLH
tMLW
NIPPON PRECISION CIRCUITS—9
SM5879AV
AC Analog Characteristics
DV = AV = AV
= XV = 0 V, DV = AV
= AV
= XV = 2.7V, P/M=2.7V, MUTE=0V,
SS
SSL
SSR
SS
DD
DDL
DDR DD
DEEM=0V, BB1=2.7V, BB2=2.7V, crystal oscillator frequency f
= 16.9344 MHz, T = 25 °C
OSC
a
Rating
Parameter
Symbol
Condition
1 kHz, 0 dB
Unit
min
–
typ
0.0075
0.70
0.70
91.0
91.5
87.0
max
0.015
0.75
–
Total harmonic distortion
LSI output level
THD + N
%
V
1 kHz, 0 dB
0.65
–
V
rms
out1
Evaluation board output level
Dynamic range
V
1 kHz, 0 dB
V
rms
out2
D.R
S/N
1 kHz, −60 dB
1 kHz, 0/−∞ dB
1 kHz, −∞/0 dB
86.0
86.0
80.0
–
dB
dB
dB
1
Signal-to-noise ratio
–
Channel separation
Ch. Sep
–
1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper
noise.
AC Measurement Circuit and Conditions
Measurement circuit block diagram
CKO(384fs)
Left Channel
BCK
Evaluation
Board
L/R Channel
Selector
Distortion
Analyzer
Signal
Generator
LRCK(fs)
DATA
Right Channel
10kΩ Input Impedance
NF Corporation 3346A
fs= 44.1kHz
DATA= 16bit
RMS Measurement
Shibasoku AD725C
Measurement conditions
3346A left/right-channel selector
switch
AD725C distortion analyzer with
built-in filter
1
Parameter
Symbol
Total harmonic distortion
Output level
THD + N
THRU
20 kHz lowpass filter ON
400 Hz highpass filter OFF
V
out
Dynamic range
DR
D-RANGE
20 kHz lowpass filter ON
400 Hz highpass filter OFF
JIS A filter ON
Signal-to-noise ratio
Channel separation
S/N
THRU
THRU
20 kHz lowpass filter ON
400 Hz highpass filter OFF
Ch. Sep
1. Pins LO and RO should have an output load of 10 kΩ (min).
NIPPON PRECISION CIRCUITS—10
SM5879AV
Measurement circuit
-
-
-
-
-
-
-
CKO
XVSS
XTI
DVSS
MUTEO
AVDDL
LO
0.01u
XTO
AVSSL
TO1
XVDD
MUTE/MLEN
DEEM/MCK AVSSR
BB1/MDT RO
BB2/BBON AVDDR
DI
P/M
BCKI
TEST
LRCI
DVDD
SM5879
NIPPON PRECISION CIRCUITS—11
SM5879AV
FUNCTIONAL DESCRIPTION
System Clock
Note that the input clock accuracy and jitter greatly
influence the AC analog characteristics.
tively, an external system clock. Since the built-in
CMOS invertor has a feedback resistor, the external
system clock can be AC coupled to XTI. The system
clock is output from CKO.
The system clock can be controlled by a crystal oscil-
lator consisting of a crystal connected between XTI
and XTO and a built-in CMOS invertor or, alterna-
System Reset (RSTN)
System reset for SM5879AV is performed by a built-
in power ON reset circuit.
Analog output is muted by this resetting, and muting
is cleared by the ninth LCRI rise (See Figure 1).
At system reset, the internal arithmetic operation and
output timing counter are synchronized with the next
LCRI rising edge and thereby reset again for syn-
chronization with external elements.
However, noise is generated due to the change in
PWM output during a timing reset. An external mute
circuit is necessary to prevent this noise.
Power on Switch
1
2
3
9
10
LRCI
Internal
Reset
LO
RO
Output Muted
Figure 2. System reset timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s-
complement, 16-bit serial format.
The bit clock frequency on BCKI should be between
32fs and 64fs.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of the
bit clock BCKI.
1 / fs
LRCI
BCKI
(MAX64fs)
DI
Lch
Rch
16bit
16bit
MSB
LSB
MSB
LSB
Figure 3.
NIPPON PRECISION CIRCUITS—12
SM5879AV
Selection and Setting of Functions
SM5879AV offers a variety of functions. Fundamen-
tally, there are two methods available for selecting
and setting these functions.
Microcontroller interface refers here to serial data
transfer from the microcontroller using the three pins
MDT, MCK, and MLEN.
One method is using an external input pin; this is
called parallel setting. The other method is by using
the microcontroller interface, which is called micro-
controller setting.
These two methods of setting and selection are set by
the P/M pin.
When P/M is HIGH, parallel setting is used.
When P/M is LOW, microcontroller setting is used.
Table 1. Selection and Setting of Functions
Function Setting Methods
Parallel setting
Related external pin name
(When P/M is HIGH)
Microcontroller setting
Related flag
(When P/M is LOW)
Function
Notes
Bass boost
BB1, BB2
None
FBB1, FBB2
Output to BBON
FDEM
Bass boost
Bass boost detection output
Deemphasis filter
Bass boost detection output
Deemphasis filter
DEEM
None
Soft mute
MUTE
Soft mute
(Enabled by attenuator)
Attenuator setting
Monaural setting
None
None
7 bits (A6 - A0)
MONO, CSEL
Attenuation
Stereo/mono output setting
NIPPON PRECISION CIRCUITS—13
SM5879AV
Microcontroller Interface
For microcontroller setting (when P/M is HIGH), the
microcontroller interface consisting of MDT (data),
MCK (clock) and MLEN (latch enable) can be used.
Serial data in the shift registers is latched in parallel
to the flag registers at the rise of MLEN.
Two flag registers are available, divided into the
attenuation factor and mode flag by the D7 data.
Data from the microcontroller is input to the input-
stage shift registers at the rise of MCK. Changes in
MDT should be performed at the rise of MCK.
MLEN
MCK
MDT
D0
D1
D2
D3 D4
D5 D6
D7
Figure 4. Format of microcontroller interface input
Table 2. microcontroller setting flags
Microcontroller
Flag
serial data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
A6
A5
A4
A3
A2
A1
A0
-
FDEM
FBB1
FBB2
MONO
CSEL
-
A0 to A6: Attenuation factor (A6: MSB)
FDEM: Deemphasis ON/OFF (ON when 1)
FBB1: Bass boost setting switch flag 1
FBB2: Bass boost setting switch flag 2
MONO: Stereo/mono setting (Mono when 1)
CSEL: Mono output channel selection
(Right channel when 1)
NIPPON PRECISION CIRCUITS—14
SM5879AV
Bass Boost
Two types of bass boost and gain modification can be
set by either parallel or microcontroller.
Table 3.
Parallel setting
pin name
BB1
BB2
Mode
Microcontroller
setting flag
FBB1
FBB2
H
H
L
L
H
L
H
L
Flat 1
Bass boost MIN
Bass boost MAX
Flat2
3
Max. Chrasteristic
2
1
Flat1 (0dB)
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
Min. Charasteristic
Flat2 (-8dB)
10
100
1000
104
105
Frequency (Fs)
Figure 5. Bass boost mode frequency response
Bass boost detection output
With microcontroller setting (when P/M is LOW),
the 21st pin is the BBON output pin and functions as
output that detects the bass boost mode.
BBON output is LOW when the bass boost mode is
set to Flat 1 and HIGH in all other cases.
Table 4.
Microcontroller
setting flag
BB1
BB2
Mode
BBON pin
H
H
L
L
H
L
H
L
Flat 1
L
H
H
H
Bass boost MIN
Bass boost MAX
Flat 2
NIPPON PRECISION CIRCUITS—15
SM5879AV
Deemphasis filter
The built-in deemphasis filter in the SM5879AV
operates at fs = 44.1 kHz.
Table 5.
Parallel setting pin name
DEEM
FDEM
Deemphasis mode
Microcontroller setting
flag
H
L
ON
OFF
Soft Mute
With parallel setting (when P/M is HIGH), soft mute
can be activated by the MUTE pin level setting using
the built-in attenuation counter. When muting is acti-
vated, MUTE is HIGH.
When soft mute is activated, the attenuation counter
operates and lowers gain in 128 steps.
The time until mute is activated is approximately
1024/fs ≈ 23.2 msec. The time required to release
muting is the same.
MUTE
0dB
(Gain)
−∞
1024/fs
1024/fs
Figure 6. Example of soft mute operation
NIPPON PRECISION CIRCUITS—16
SM5879AV
Attenuation
The SM5879AV loads the attenuation factor with
serial data by means of the microcontroller interface,
thus enabling attenuation operation.
MLEN
MCK
MDT
A0
(LSB)
D0
A1
A3
A4
A5
A6
0
A2
(MSB)
D1
D2 D3 D4
D5 D6
D7
Figure 7. Method of setting the attenuation factor
The attenuation computation is performed by multi-
plying the output of the internal 7-bit UP/DOWN
counter output data by the signal data. When the con-
tents of the counter are DATT, gain can be expressed
by the following equations.
L channel
DATT
127
---------------
=
×
Gain 20 log
[dB]
[dB]
R channel
DATT
127
---------------
=
×
Gain 20 log
When DATT = 0, this becomes -∞.
When the attenuation factor is changed, it is
smoothly changed from the previous setting until it
reaches the value of the new setting as expressed by
the above equations. The time required to change
gain is approximately 1024 fs ≈ 23.2 msec when the
time required to change one step of the attenuation
factor is approximately 8 / fs ≈ 181.4 µsec over the
range 0 dB to -∞.
Setting1
Setting5
Setting3
(Gain)
Setting2
Setting4
Time
Figure 8. Example of attenuation gain
NIPPON PRECISION CIRCUITS—17
SM5879AV
Stereo/Mono Output Setting
Mono output can be set via the microcontroller
(when P/M is HIGH).
Table 6.
Microcontroller
setting flag
MONO
CSEL
Output
H
H
L
L
H
L
H
L
R channel
L channel
Stereo
Infinity-Zero Detection Output
HIGH level is output from the infinity-zero detection
output pin in the following cases with the
SM5879AV.
(1) From the time that power ON is reset until the
first data comes in.
(2) When the LOW level space of the DI pin has con-
14
tinued for 2 × (1/fs) ≈ 0.37 [sec] or more.
214/fs
1
2
3
9
LRCI
DI
Signal
No Signal
Signal
RSTN
MUTEO
Internal
Status
Initialize
Figure 9.
NIPPON PRECISION CIRCUITS—18
SM5879AV
TIMING DIAGRAMS
Input Timing (DI, BCKI, LRCI)
1 / fs
LRCI
BCKI
(MAX64fs)
DI
Lch
Rch
16bit
16bit
MSB
LSB
MSB
LSB
TYPICAL APPLICATIONS
Input Interface Circuits
Normal Speed
X'tal (16.9344MHz)
XTI
XTO
16.9344MHz
44.1kHz
XTAI
LRCK
DA16
DA15
CKO
LRCI
DI
SONY
CXD2500
SM5879
2.1168MHz
BCKI
PSSL
NIPPON PRECISION CIRCUITS—19
SM5879AV
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2 chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NIPPON PRECISION CIRCUITS INC.
NC9702BE 1997.11
NIPPON PRECISION CIRCUITS—20
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