概述
数据手册54F573PCX 概述
Octal D-Type Latch with TRI-STATE Outputs 八D型锁存器与三态输出
54F573PCX 数据手册
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PDF下载August 1995
54F/74F573
Octal D-Type Latch with TRI-STATE Outputs
É
General Description
The ’F573 is a high speed octal latch with buffered common
Latch Enable (LE) and buffered common Output Enable
(OE) inputs.
Features
Y
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to ’F373
Y
Y
Y
Y
This device is functionally identical to the ’F373 but has
different pinouts.
TRI-STATE outputs for bus interfacing
Guaranteed 4000V minimum ESD protection
Package
Commercial
74F573PC
Military
Package Description
Number
N20A
J20A
20-Lead (0.300 Wide) Molded Dual-In-Line
×
54F573DM (Note 2)
20-Lead Ceramic Dual-In-Line
74F573SC (Note 1)
74F573SJ (Note 1)
M20B
M20D
W20A
E20A
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F573FM (Note 2)
54F573LM (Note 2)
20-Lead Cerpak
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9566–1
IEEE/IEC
TL/F/9566–3
TL/F/9566–2
TL/F/9566–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9566
RRD-B30M115/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
7
LE
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input
(Active LOW)
OE
b
1.0/1.0
20 mA/ 0.6 mA
b
O –O
0
TRI-STATE Latch Outputs
150/40(33.3)
3 mA/24 mA (20 mA)
7
Functional Description
The ’F573 contains eight D-type latches with 3-state output
Function Table
buffers. When the Latch Enable (LE) input is HIGH, data on
the D inputs enters the latches. In this condition the latch-
n
Inputs
LE
Outputs
O
es are transparent, i.e., a latch output will change state each
time its D input changes. When LE is LOW the latches store
the information that was present on the D inputs a setup
time preceding the HIGH-to-LOW transition of LE. The 3-
state buffers are controlled by the Output Enable (OE) input.
When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfer with entering new data into
the latches.
OE
D
L
L
H
H
L
H
L
H
L
L
X
X
O
0
H
X
Z
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
O
e
Value stored from previous clock cycle
0
Logic Diagram
TL/F/9566–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.4
2.5
2.4
2.7
2.7
I
I
I
I
I
I
1 mA
3 mA
1 mA
3 mA
1 mA
3 mA
CC
CC
CC
CC
OH
OH
OH
OH
OH
OH
54F 10% V
74F 10% V
74F 10% V
V
74F 5% V
74F 5% V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
0.5
I
I
20 mA
24 mA
OL
CC
CC
OL
OL
V
Min
Max
Max
Max
0.0
e
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
2.7V
IH
IN
mA
mA
mA
V
e
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
7.0V
BVI
IN
e
V
CC
Output HIGH
Leakage Current
54F
74F
250
50
CEX
OUT
e
All Other Pins Grounded
V
ID
Input Leakage
Test
I
1.9 mA
ID
74F
74F
4.75
e
V 150 mV
IOD
All Other Pins Grounded
I
Output Leakage
Circuit Current
OD
3.75
mA
0.0
b
e
0.5V
I
I
I
I
I
I
I
Input LOW Current
0.6
mA
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
0.0V
Max
Max
V
V
V
V
V
V
V
IL
IN
e
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
50
2.7V
0.5V
0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
b
e
e
e
50
b
b
150
500
60
5.25V
ZZ
e
Power Supply Current
Power Supply Current
35
35
55
55
LOW
CCL
CCZ
O
e
HIGH Z
O
3
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
t
t
Propagation Delay
3.0
2.0
5.3
3.7
7.0
6.0
3.0
2.0
9.0
7.0
3.0
2.0
8.0
6.5
PLH
ns
ns
D
n
to O
n
PHL
t
t
Propagation Delay
LE to O
5.0
3.0
9.0
5.2
11.0
7.0
5.0
3.0
13.5
7.5
5.0
3.0
12.0
7.0
PLH
PHL
n
t
t
Output Enable Time
2.0
2.0
5.0
5.6
8.0
8.5
2.0
2.0
10.0
10.0
2.0
2.0
9.0
9.5
PZH
PZL
ns
t
t
Output Disable Time
1.5
1.5
4.5
3.8
5.5
5.5
1.5
1.5
7.0
5.5
1.5
1.5
6.5
5.5
PHZ
PLZ
AC Operating Requirements
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
e a
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
2.0
2.0
2.0
2.0
2.0
2.0
t (L)
s
D to LE
n
ns
ns
t (H)
h
Hold Time, HIGH or LOW
D to LE
n
3.0
3.5
3.0
4.0
3.0
3.5
t (L)
h
t (H)
w
LE Pulse Width, HIGH
4.0
4.0
4.0
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 573
S
C
X
Temperature Range Family
e
e
54F Military
Special Variations
e
74F Commercial
QB
Military grade device with
environmental and burn-in
processing
Device Type
e
X
Devices shipped in 13 reels
×
Package Code
Temperature Range
e
e
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
a
C
Commercial (0 C to 70 C)
§
§
e
b a
Military ( 55 C to 125 C)
M
§
§
S
e
SJ
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Small Outline Package, EIAJ (SJ)
×
NS Package Number M20D
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
7
Physical Dimensions inches (millimeters) (Continued)
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
54F573PCX 相关器件
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| 54F573PMQB | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573PMX | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573SCQB | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573SCX | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573SDM | FAIRCHILD | Bus Driver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, CDIP20, SLIM, CERAMIC, DIP-20 | 获取价格 |
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| 54F573SJCQB | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573SJCX | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573SJMQB | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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| 54F573SJMX | NSC | Octal D-Type Latch with TRI-STATE Outputs | 获取价格 |
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