74ACT899 [NSC]
9-Bit Latchable Transceiver with Parity Generator/Checker; 9位闭锁收发器奇偶校验发生器/校验器
| 型号： | 74ACT899 |
| 厂家： | 
National Semiconductor |
| 描述： | 9-Bit Latchable Transceiver with Parity Generator/Checker |
| 文件： | 总15页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1994
74AC899 54ACT/74ACT899
#
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
Features
Y
Latchable transceiver with output sink of 24 mA
The ’AC/’ACT899 is a 9-bit to 9-bit parity transceiver with
transparent latches. The device can operate as a feed-
through transceiver or it can generate/check parity from the
8-bit data busses in either direction. The ’AC/’ACT899 fea-
tures independent latch enables for the A-to-B direction and
the B-to-A direction, a select pin for ODD/EVEN parity, and
separate error signal output pins for checking parity.
Y
Option to select generate parity and check or ‘‘feed-
through’’ data/parity in directions A-to-B or B-to-A
Independent latch enable for A-to-B and B-to-A direc-
tions
Y
Y
Y
Y
Y
Y
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
May be used in system applications in place of the ’280
May be used in system applications in place of the ’657
and ’373 (no need to change T/R to check parity)
4 kV minimum ESD immunity
Y
Logic Symbol
Connection Diagram
Pin Assignment for PCC and LCC
TL/F/10637–1
TL/F/10637–2
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10637
RRD-B30M75/Printed in U. S. A.
Pin Names
Description
Functional Description
The ’AC/’ACT899 has three principal modes of operation
which are outlined below. These modes apply to both the A-
to-B and B-to-A directions.
A –A
0
B –B
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active
LOW for EVEN Parity
7
7
0
APAR, BPAR
ODD/EVEN
Ð Bus A (B) communicates to Bus B (A), parity is generat-
ed and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
GBA, GAB
SEL
Output Enables for A or B Bus,
Active LOW
[
]
[
the parity generated from B 0:7 (A 0:7 ) can be
checked and monitored by ERRB (ERRA).
]
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Ð Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
LEA, LEB
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In,
LOW if Error Occurs
ERRA, ERRB
Ð Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Ta-
ble below).
Function Table
Inputs
GAB GBA SEL LEA LEB
Operation
H
H
H
L
X
L
X
L
X
Busses A and B are TRI-STATE .
É
[
]
H
Generates parity from B 0:7 based on O/E (Note 1). Generated parity
APAR. Generated parity checked against BPAR and output as
ERRB.
x
[
]
H
H
L
L
L
L
H
X
H
L
Generates parity from B 0:7 based on O/E. Generated parity
x
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
as ERRA.
Generates parity from B latch data based on O/E. Generated parity
x APAR. Generated parity checked against latched BPAR and
output as ERRB.
[
]
checked against BPAR and output as ERRB.
]
APAR/A0:7 Feed-through mode. Generated parity
H
H
L
L
H
H
X
H
H
BPAR/B 0:7
x
[
]
[
]
H
BPAR/B 0:7
x
APAR/A 0:7
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for
generate/check as ERRA.
[
]
Generates parity for A 0:7 based on O/E. Generated parity
BPAR. Generated parity checked against APAR and output as ERRA.
L
L
H
H
L
L
H
H
L
x
[
]
H
Generates parity from A 0:7 based on O/E. Generated parity
x
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
L
L
L
H
H
H
L
H
H
L
H
H
X
L
Generates parity from A latch data based on O/E. Generated parity
x BPAR. Generated parity checked against latched APAR and
output as ERRA.
[
]
[
]
Feed-through mode. Generated parity checked against APAR and
APAR/A 0:7
x
BPAR/B 0:7
output as ERRA.
[
]
[
]
H
APAR/A 0:7
x
BPAR/B 0:7
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for
generate/check as ERRB.
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
Note 1: O/E
ODD/EVEN
2
Functional Block Diagram
TL/F/10637–3
AC Path
TL/F/10637–4
(B , BPAR xBA ,,BAPPAARR)
A , APAR x
n
n
n
n
FIGURE 1
3
AC Path (Continued)
A
n x
(Bn xBAPPAARR)
TL/F/10637–5
FIGURE 2
A
n x
(Bn xEERRRRAB)
TL/F/10637–6
FIGURE 3
OO//EE x EERRRRBA
x
TL/F/10637–7
FIGURE 4
4
AC Path (Continued)
(O/E xBAPPAARR)
O/E x
TL/F/10637–8
FIGURE 5
(BPAR xEERRRRAB)
APAR x
TL/F/10637–9
FIGURE 6
TL/F/10637–10
ZH, HZ
FIGURE 7
5
AC Path (Continued)
TL/F/10637–11
ZL, LZ
FIGURE 8
TL/F/10637–12
(SEL xBAPPAARR)
SEL x
FIGURE 9
TL/F/10637–13
[
[
]
]
LEA
x
(LEB xBAPPAARR,,BA00:7:7 )
FIGURE 10
6
AC Path (Continued)
TS(H), TH(H)
TL/F/10637–14
[
[
]
]
LEA
x
(LEB xABPPAARR,,AB00:7:7 )
FIGURE 11
TS(L), TH(L)
TL/F/10637–15
[
[
]
]
LEA
x
(LEB xABPPAARR,,AB00:7:7 )
FIGURE 12
TL/F/10637–16
FIGURE 13
7
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’AC
’ACT
)
CC
2.0V to 6.0V
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
DC Input Diode Current (I
)
IK
Input Voltage (V )
I
0V to V
0V to V
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Output Voltage (V
)
O
CC
e
V
CC
0.5V
Operating Temperature (T )
A
74AC/ACT
54ACT
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
b
b
a
40 C to 85 C
§
55 C to 125 C
§
§
DC Output Diode Current (I
)
a
OK
§
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
Minimum Input Edge Rate DV/Dt
’AC Devices
e
V
CC
0.5V
a
DC Output Voltage (V
DC Output Source
)
O
0.5V
50 mA
50 mA
CC
V
V
from 30% to 70% of V
@
IN
CC
3.0V, 4.5V, 5.5V
125 mV/ns
CC
g
g
or Sink Current (I
)
O
Minimum Input Edge Rate DV/Dt
’ACT Devices
DC V
or Ground Current
CC
per Output Pin (I or I
CC
)
V
V
from 0.8V to 2.0V
@
GND
)
IN
4.5V, 5.5V
125 mV/ns
b
a
65 C to 150 C
CC
Storage Temperature (T
§
§
STG
Note: PLCC packaging is not recommended for applications requiring great-
a
er than 2000 temperature cycles from 40 C to 125 C.
DC Latch-Up Source or
Sink Current
b
§
§
g
300 mA
Junction Temperature (T )
J
CDIP
PDIP
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for ’AC Family Devices
74AC
74AC
e
T
A
V
CC
(V)
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
40 C to 85 C
§
Guaranteed Limits
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.1
2.1
V
IH
OUT
b
2.25
2.75
3.15
3.85
3.15
3.85
V
V
V
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
0.9
0.9
V
OUT
0.1V
IL
b
2.25
2.75
1.35
1.65
1.35
1.65
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
50 mA
OH
e
*V
IN
V
or V
IH
12 mA
IL
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
V
V
I
24 mA
24 mA
OH
e
e
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
e
(Note)
I
Maximum Input
Leakage Current
V
V
, GND
CC
IN
I
g
g
1.0
5.5
0.1
mA
*Maximum of 9 outputs loaded; thresholds on input associated with output under test.
8
DC Electrical Characteristics for ’AC Family Devices (Continued)
74AC
74AC
e
T
A
V
CC
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
40 C to 85 C
(V)
§
§
Typ
Guaranteed Limits
e
²
I
I
I
Minimum Dynamic
5.5
5.5
75
mA
mA
V
V
V
1.65V Max
OLD
OHD
CC
OLD
Output Current
b
e
3.85V Min
75
OHD
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
5.5
8.0
80.0
mA
mA
or GND (Note)
e
I
Maximum TRI-STATE
Leakage Current
V (OE)
I
V , V
IL IH
OZ
e
e
g
g
5.0
0.5
V
V
V
, GND
CC
I
V
CC
, GND
O
²
Maximum test duration 2.0 ms, one output loaded at a time.
@
@
@
for 54AC 25 C is identical to 74AC 25 C.
@
Note: I and I
IN
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V . I
CC CC
§
§
CC
DC Electrical Characteristics for ’ACT Family Devices
74ACT
54ACT
74ACT
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
0.1V
IL
b
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
b
b
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
V
V
I
24 mA
24 mA
OH
e
e
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V
or V
IL IH
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
I
24 mA
OL
V
24 mA
e
e
I
I
Maximum Input
Leakage Current
V
V
, GND
CC
IN
I
g
g
g
g
g
5.5
5.5
0.1
0.5
1.0
1.0
5.0
mA
mA
Maximum TRI-STATE
Leakage Current
V
V
V , V
IL IH
OZ
I
g
10.0
e
V
, GND
O
CC
e
b
2.1V
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
0.6
1.6
50
1.5
75
mA
mA
mA
V
V
V
V
V
CC
CCT
OLD
OHD
CC
I
e
²
Minimum Dynamic
1.65V Max
e
3.85V Min
OLD
OHD
Output Current
b
b
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
8.0
160.0
80.0
mA
or GND (Note)
*Maximum of 9 outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25 C is identical to 74ACT 25 C.
§ §
Note: I
CC
9
AC Electrical Characteristics
74AC
74AC
e b
T
40 C
§
A
e a
A
V
*
T
25 C
Fig.
No.
§
50 pF
CC
a
Symbol
Parameter
to 85 C
Units
§
50 pF
e
(V)
C
L
e
C
L
Min
Typ
Max
Min
Max
t
t
Propagation Delay
3.3
5.0
2.5
1.5
12.0
7.0
15.0
10.0
2.5
1.5
15.5
10.5
PLH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
A , B to B , A
n
PHL
n
n
n
t
t
Propagation Delay
3.3
5.0
2.5
1.5
9.5
5.5
12.0
8.0
2.5
1.5
12.5
8.5
PLH
APAR, BPAR to BPAR, APAR
PHL
t
t
Propagation Delay
3.3
5.0
3.0
2.0
13.5
8.0
16.5
11.0
3.0
2.0
17.0
11.5
PLH
2
A , B to BPAR, APAR
n n
PHL
t
t
Propagation Delay
A , B to ERRA, ERRB
3.3
5.0
2.5
1.5
12.5
7.5
15.5
10.5
2.5
1.5
16.5
11.0
PLH
3
PHL
n
n
t
t
Propagation Delay
3.3
5.0
2.5
1.5
12.5
7.5
15.5
10.5
2.5
1.5
16.5
11.0
PLH
4
ODD/EVEN to ERRA, ERRB
PHL
t
t
Propagation Delay
3.3
5.0
3.0
2.0
12.5
7.5
15.5
10.5
3.0
2.0
16.5
11.0
PLH
5
ODD/EVEN to APAR, BPAR
PHL
t
t
Propagation Delay
3.3
5.0
2.0
1.5
12.5
7.5
15.5
10.5
2.0
1.5
16.5
11.0
PLH
6
APAR, BPAR to ERRA, ERRB
PHL
t
t
Propagation Delay
3.3
5.0
2.0
1.5
10.0
6.0
12.5
8.5
2.0
1.5
13.5
9.0
PLH
9
SEL to APAR, BPAR
PHL
t
t
Propagation Delay
3.3
5.0
4.0
2.5
12.0
7.0
15.5
10.5
4.0
2.5
16.5
11.0
PLH
10, 11
10, 11
12
LEB, LEA to A , B
n
PHL
n
t
t
Propagation Delay
3.3
5.0
3.0
2.0
13.5
8.0
17.0
11.5
3.0
2.0
18.0
12.0
PLH
LEB, LEA to APAR, BPAR
PHL
t
t
Propagation Delay
3.3
5.0
4.0
2.5
13.5
8.0
17.0
11.5
4.0
2.5
18.0
12.0
PLH
LEB, LEA to ERRA, ERRB
PHL
t
t
Output Enable Time
3.3
5.0
3.0
2.0
12.5
7.5
15.5
10.5
3.0
2.0
16.5
11.0
PZH
7, 8
7, 8
7, 8
7, 8
GBA, GAB to A , B
n
PZL
n
t
t
Output Enable Time
3.3
5.0
2.5
1.5
10.5
6.0
13.5
9.0
2.5
1.5
14.0
9.5
PZH
GBA, GAB to APAR, BPAR
PZL
t
t
Output Disable Time
3.3
5.0
1.5
1.0
11.0
6.5
14.0
9.5
1.5
1.0
14.0
9.5
PHZ
GBA, GAB to A , B
n
PLZ
n
t
t
Output Disable Time
3.3
5.0
1.5
1.0
11.0
6.5
14.0
9.5
1.5
1.0
14.0
9.5
PHZ
GBA, GAB to APAR, BPAR
PHL
g
*Voltage Range 5.0 is 5.0V 0.5V.
g
Voltage Range 3.3 is 3.3V 0.3V.
10
AC Operating Requirements
74AC
74AC
e b
T
40 C
§
A
e a
A
V *
CC
(V)
T
25 C
Fig.
No.
§
50 pF
a
Symbol
Parameter
to 85 C
Units
§
50 pF
e
C
L
e
C
L
Guaranteed Minimum
3.0
t
t
t
Setup Time, HIGH or LOW
3.3
5.0
3.0
s
ns
ns
ns
11, 12
11, 12
13
A , B , PAR to LEA, LEB
n n
3.0
3.0
Hold Time, HIGH or LOW
A , B , PAR to LEA, LEB
3.3
5.0
2.0
1.5
2.0
1.5
h
w
n
n
Pulse Width for LEA, LEB
3.3
5.0
4.0
4.0
4.0
4.0
g
*Voltage Range 5.0 is 5.0V 0.5V.
g
Voltage Range 3.3 is 3.3V 0.3V.
AC Electrical Characteristics
74ACT
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
Fig.
No.
§
50 pF
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
t
t
Propagation Delay
PLH
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.5
7.5
6.0
8.5
8.0
8.0
8.0
7.5
6.5
7.0
8.0
8.0
7.0
6.0
6.5
6.5
11.5
1.5
13.5
11.0
16.0
16.0
16.0
14.5
11.5
12.5
13.5
16.0
16.0
16.0
11.0
11.0
11.0
2.5
12.0
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
A , B to B , A
n
PHL
n
n
n
t
t
Propagation Delay
PLH
1.5
2.5
2.0
2.0
2.5
1.5
1.5
2.5
2.0
2.5
2.5
1.5
1.5
1.5
8.5
12.0
11.5
11.5
11.5
10.5
9.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.0
2.0
2.5
1.5
1.5
2.5
2.0
2.5
2.5
1.5
1.5
1.5
APAR, BPAR to BPAR , APAR
PHL
t
t
Propagation Delay
PLH
12.5
12.0
12.0
12.0
11.5
9.5
2
A , B to BPAR, APAR
n n
PHL
t
t
Propagation Delay
A , B to ERRA, ERRB
PLH
3
PHL
n
n
t
t
Propagation Delay
PLH
4
ODD/EVEN to ERRA, ERRB
PHL
t
t
Propagation Delay
PLH
5
ODD/EVEN to APAR, BPAR
PHL
t
t
Propagation Delay
PLH
6
APAR, BPAR to ERRA, ERRB
PHL
t
t
Propagation Delay
PLH
9
SEL to APAR, BPAR
PHL
t
t
Propagation Delay
PLH
10.5
11.5
11.5
10.5
9.0
11.0
12.0
12.0
11.0
9.5
10, 11
10, 11
12
LEB to A , B
n
PHL
n
t
t
Propagation Delay
PLH
LEA to APAR, BPAR
PHL
t
t
Propagation Delay
PLH
LEA, LEB to ERRA, ERRB
PHL
t
t
Output Enable Time
PZH
7, 8
7, 8
7, 8
7, 8
GBA or GAB to A , B
n
PZL
n
t
t
Output Enable Time
PZH
GBA or GAB to BPAR or APAR
PZL
t
t
Output Disable Time
PHZ
9.5
9.5
GBA or GAB to A , B
n
PHL
n
t
t
Output Disable Time
PHZ
9.5
9.5
GBA or GAB to BPAR, APAR
PLZ
g
*Voltage Range 5.0 is 5.0V
0.5V.
11
AC Operating Requirements
74ACT
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V
CC
(V)
*
T
25 C
Fig.
No.
§
50 pF
a
e
a
Symbol
Parameter
to 85 C
Units
§
50 pF
§
e
C
L
e
50 pF
C
C
L
L
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
s
5.0
3.0
3.0
3.0
ns
11, 12
A , B , PAR to LEA, LEB
n n
Hold Time, HIGH or LOW
A , B , PAR to LEA, LEB
h
5.0
5.0
1.5
4.0
3.0
4.0
1.5
4.0
ns
ns
11, 12
13
n
n
Pulse Width for LEB, LEA
w
e
g
5.0V 0.5V.
*Voltage Range 5.0
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
e
C
C
Input Capacitance
4.5
pF
V
V
5.0V
5.0V
IN
CC
Power Dissipation
Capacitance
PD
CC
210
pF
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT 899
Q
C
X
Temperature Range Family
e
Special Variations
e
e
74AC
74ACT
54ACT
Commercial
Commercial TTL-Compatible
Military TTL-Compatible
X
QB
Devices shipped in 13 reels
×
e
e
Military grade with environmental
and burn-in processing shipped
in tubes
Device Type
Temperature Range
e
Package Code
e
b a
C
Commercial ( 40 C to 85 C)
§
§
Q
Plastic Leaded Chip Carrier (PCC)
e
b a
Military ( 55 C to 125 C)
M
§
§
12
13
Ý
Lit. 115200
Physical Dimensions inches (millimeters)
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
Tel: 1(800) 272-9959
TWX: (910) 339-9240
National Semiconductor
GmbH
Livry-Gargan-Str. 10
D-82256 Furstenfeldbruck
Germany
Tel: (81-41) 35-0
Telex: 527649
Fax: (81-41) 35-1
National Semiconductor National Semiconductor
National Semiconductores
Do Brazil Ltda.
Rue Deputado Lacorda Franco
120-3A
Sao Paulo-SP
Brazil 05418-000
Tel: (55-11) 212-5066
Telex: 391-1131931 NSBR BR
Fax: (55-11) 212-1181
National Semiconductor
(Australia) Pty, Ltd.
Building 16
Business Park Drive
Monash Business Park
Nottinghill, Melbourne
Victoria 3168 Australia
Tel: (3) 558-9999
Japan Ltd.
Hong Kong Ltd.
Sumitomo Chemical
Engineering Center
Bldg. 7F
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
1-7-1, Nakase, Mihama-Ku Hong Kong
Chiba-City,
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Ciba Prefecture 261
Tel: (043) 299-2300
Fax: (043) 299-2500
Fax: (3) 558-9998
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
WWW.ALLDATASHEET.COM
Copyright © Each Manufacturing Company.
All Datasheets cannot be modified without permission.
This datasheet has been download from :
www.AllDataSheet.com
100% Free DataSheet Search Site.
Free Download.
No Register.
Fast Search System.
www.AllDataSheet.com
相关型号：
74ACT899QCX_NL
Registered Bus Transceiver, ACT Series, 1-Func, 9-Bit, True Output, CMOS, PQCC28, 0.450 X 0.450 INCH, PLASTIC, MO-047, LCC-28
FAIRCHILD
74ACT899SC
Registered Bus Transceiver, ACT Series, 1-Func, 9-Bit, True Output, CMOS, PDSO20, SO-20
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明