74F174SJ [NSC]
Hex D Flip-Flop with Master Reset; HEX D触发器与主复位
| 型号： | 74F174SJ |
| 厂家： | 
National Semiconductor |
| 描述： | Hex D Flip-Flop with Master Reset |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1994
54F/74F174 Hex D Flip-Flop with Master Reset
General Description
Features
Y
Edge-triggered D-type inputs
The ’F174 is a high-speed hex D flip-flop. The device is
used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
Y
Buffered positive edge-triggered clock
Y
Asynchronous common reset
Y
Guaranteed 4000V minimum ESD protection
Package
Commercial
74F174PC
Military
Package Description
Number
N16E
J16A
16-Lead (0.300 Wide) Molded Dual-In-Line
×
54F174DM (Note 2)
16-Lead Ceramic Dual-In-Line
74F174SC (Note 1)
74F174SJ (Note 1)
M16A
M16D
W16A
E20A
16-Lead (0.150 Wide) Molded Small Outline, JEDEC
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F174FM (Note 2)
54F174LM (Note 2)
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use Suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9489–3
TL/F/9489–1
TL/F/9489–2
IEEE/IEC
TL/F/9489–5
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9489
RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
5
CP
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
MR
b
Q –Q
0
1 mA/20 mA
5
Functional Description
Truth Table
The ’F174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Mas-
ter Reset (MR) are common to all flip-flops. Each D input’s
state is transferred to the corresponding flip-flop’s output
following the LOW-to-HIGH Clock (CP) transition. A LOW
input to the Master Reset (MR) will force all outputs LOW
independent of Clock or Data inputs. The ’F174 is useful for
applications where the true output only is required and the
Clock and Master Reset are common to all storage ele-
ments.
Inputs
Outputs
MR
CP
D
Q
n
n
L
H
H
X
X
L
L
L
H
L
H
L
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
L
LOW-to-HIGH Clock Transition
Logic Diagram
TL/F/9489–4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
TRI-STATE Output
É
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.5
2.7
I
I
I
1 mA
1 mA
1 mA
CC
OH
OH
OH
74F 10% V
74F 5% V
V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
I
I
20 mA
20 mA
OL
CC
OL
V
Min
Max
Max
Max
0.0
0.5
CC
OL
e
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
2.7V
IH
IN
mA
mA
mA
V
e
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
7.0V
BVI
IN
e
V
CC
Output HIGH
54F
74F
250
50
CEX
OUT
Leakage Current
e
All Other Pins Grounded
V
ID
Input Leakage
Test
I
ID
1.9 mA
74F
74F
4.75
e
IOD
I
Output Leakage
Circuit Current
V
150 mV
OD
3.75
mA
0.0
All Other Pins Grounded
b
e
0.5V
I
I
I
Input LOW Current
0.6
mA
mA
Max
Max
V
IL
IN
b
b
e
0V
OUT
Output Short-Circuit Current
Power Supply Current
60
150
V
OS
CCH
e
e
CP
L
MR
30
30
45
45
mA
mA
Max
Max
e
HIGH
D
n
e
I
Power Supply Current
V
LOW
CCL
O
3
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
Propagation Delay
80
70
80
MHz
ns
max
t
t
3.5
4.0
5.5
7.0
8.0
3.0
4.0
10.0
12.0
3.5
4.0
9.0
PLH
CP to Q
10.0
11.0
PHL
n
t
Propagation Delay
MR to Q
PHL
5.0
10.0
14.0
5.0
16.0
5.0
15.0
ns
n
AC Operating Requirements
74F
54F
74F
e a
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
4.8
4.0
5.0
5.0
4.8
4.0
t (L)
s
D to CP
n
ns
t (H)
h
Hold Time, HIGH or LOW
D to CP
n
0
0
2.0
2.0
0
0
t (L)
h
t
t
(H)
(L)
CP Pulse Width
HIGH or LOW
4.0
6.0
5.0
7.5
4.0
6.0
w
ns
ns
w
t
t
(L)
MR Pulse Width, LOW
5.0
5.0
6.5
6.0
5.0
5.0
w
Recovery Time, MR to CP
rec
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 174
S
C
X
Temperature Range Family
Special Variations
e
e
e
74F
54F
Commercial
Military
QB
Military grade device with
environmental and burn-in
processing
Device Type
e
X
Devices shipped in 13 reel
×
Package Code
Temperature Range
e
e
e
e
e
e
P
D
F
L
S
SS
Plastic DIP
Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
Physical Dimensions inches (millimeters)
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
16-Lead (0.150 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M16A
6
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)
×
NS Package Number M16D
16-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N16E
7
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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