74F413 [NSC]
64 x 4 First-In First-Out Buffer Memory with Parallel I/O; 64 ×4的先入先出缓冲存储器，并行I / O
| 型号： | 74F413 |
| 厂家： | 
National Semiconductor |
| 描述： | 64 x 4 First-In First-Out Buffer Memory with Parallel I/O |
| 文件： | 总6页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
54F/74F413
64 x 4 First-In First-Out Buffer Memory with Parallel I/O
General Description
Features
Y
Separate input and output clocks
The ’F413 is an expandable fall-through type high-speed
First-In First-Out (FIFO) buffer memory organized as 64
words by four bits. The 4-bit input and output registers rec-
ord and transmit, respectively, asynchronous data in parallel
form. Control pins on the input and output allow for hand-
shaking and expansion. The 4-bit wide, 62-bit deep fall-
through stack has self-contained control logic.
Y
Parallel input and output
Y
Expandable without external logic
Y
15 MHz data rate
Y
Supply current 160 mA max
Y
Available in SOIC, (300 mil only)
Package
Number
Commercial
Military
Package Description
74F413PC
N16E
J16A
16-Lead (0.300 Wide) Molded Dual-In-Line
×
54F413DM (Note 1)
16-Lead Ceramic Dual-In-Line
e
Note 1: Military grade device with environmental and burn-in processing. Use suffix
DMQB.
Logic Symbol
Connection Diagram
Pin Assignment
for DIP
TL/F/9541–1
TL/F/9541–2
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9541
RRD-B30M105/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.4 mA
D –D
0
Data Inputs
Data Outputs
Input Ready
Shift In
1.0/0.667
50/13.3
3
b
O –O
0
1 mA/8 mA
3
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
IR
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
SI
SO
OR
MR
Shift Out
Output Ready
Master Reset
b
20 mA/ 0.4 mA
Functional Description
Data InputÐData is entered into the FIFO on D –D in-
Data OutputÐData is read from the O –O outputs. When
0 3
0
3
puts. To enter data the Input Ready (IR) should be HIGH,
indicating that the first location is ready to accept data. Data
then present at the four data inputs is entered into the first
location when the Shift In (SI) is brought HIGH. An SI HIGH
signal causes the IR to go LOW. Data remains at the first
location until SI is brought LOW. When SI is brought LOW
and the FIFO is not full, IR will go HIGH, indicating that more
room is available. Simultaneously, data will propagate to the
second location and continue shifting until it reaches the
output stage or a full location. If the memory is full, IR will
remain LOW.
data is shifted to the output stage, Output Ready (OR) goes
HIGH, indicating the presence of valid data. When the OR is
HIGH, data may be shifted out by bringing the Shift Out (SO)
HIGH. A HIGH signal at SO causes the OR to go LOW. Valid
data is maintained while the SO is HIGH. When SO is
brought LOW, the upstream data, provided that stage has
valid data, is shifted to the output stage. When new valid
data is shifted to the output stage, OR goes HIGH. If the
FIFO is emptied, OR stays LOW, and O –O remains as
0
3
before, i.e., data does not change if FIFO is empty.
Input Ready and Output Ready may also be used as
status signals indicating that the FIFO is completely full (In-
Data TransferÐOnce data is entered into the second cell,
the transfer of any full cell to the adjacent (downstream)
empty cell is automatic, activated by an on-chip control.
Thus data will stack up at the end of the device while empty
put Ready stays LOW for at least t ) or completely empty
PT
(Output Ready stays LOW for at least t ).
PT
locations will ‘‘bubble’’ to the front. The t parameter de-
PT
fines the time required for the first data to travel from input
to the output of a previously empty device.
Block Diagram
TL/F/9541–4
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
TRI-STATE Output
É
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Typ
Symbol
Parameter
Units
V
Conditions
CC
Min
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.5
Min
Min
I
IN
CD
OH
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.4
2.4
2.7
I
I
I
1 mA
1 mA
1 mA
CC
OH
OH
OH
74F 10% V
74F 5% V
V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
I
I
8 mA
OL
CC
OL
V
Min
Max
Max
Max
0.0
0.5
8 mA
CC
OL
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
IH
e
e
mA
mA
mA
V
V
V
V
2.7V
IN
Input HIGH Current 54F
100
7.0
BVI
7.0V
IN
Breakdown Test
74F
Output HIGH
54F
74F
250
50
CEX
e
V
CC
OUT
Leakage Current
e
All Other Pins Grounded
V
ID
Input Leakage
Test
I
ID
1.9 mA
74F
74F
4.75
e
IOD
I
Output Leakage
Circuit Current
V
150 mV
OD
3.75
mA
0.0
All Other Pins Grounded
b
e
0.5V
I
I
I
Input LOW Current
0.4
mA
mA
mA
Max
Max
Max
V
V
V
IL
IN
b
b
e
0V
OUT
Output Short-Circuit Current
Power Supply Current
20
130
OS
CCH
e
115
160
HIGH
O
3
AC Electrical Characteristics
74F
54F
74F
e a
T
A
25 C
§
5.0V
e
50 pF
e
T
, V
CC
e
Mil
T
, V
Com
e
50 pF
A
A CC
e a
Symbol
Parameter
V
Units
CC
C
C
L
L
e
C
50 pF
L
Min
10
Typ
Max
Min
8.0
8.0
Max
Min
10
Max
f
f
Shift In Rate
MHz
MHz
max
Shift Out Rate
10
10
max
t
t
Propagation Delay
Shift In to IR
1.5
1.5
44.0
31.0
1.5
1.5
50.0
37.0
1.5
1.5
48.0
35.0
PLH
ns
ns
ns
ns
ns
PHL
t
t
Propagation Delay
Shift Out to OR
1.5
1.5
52.0
31.0
1.5
1.5
57.0
37.0
1.5
1.5
55.0
35.0
PLH
PHL
t
t
Propagation Delay
Output Data Delay
1.5
1.5
46.0
34.0
1.5
1.5
52.0
39.0
1.5
1.5
50.0
37.0
PLH
PHL
t
Propagation Delay
Master Reset to IR
PLH
1.5
1.5
27.0
30.0
1.5
1.5
33.0
34.0
1.5
1.5
31.0
32.0
t
Propagation Delay
Master Reset to OR
PLH
AC Operating Requirements
74F
e a
54F
74F
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
T
, V
CC
Com
Max
Units
A
A
e a
V
CC
Min
Max
Min
Max
Min
t (H)
s
Setup Time, HIGH or LOW
1.0
1.0
1.0
1.0
1.0
1.0
t (L)
s
D to SI
n
ns
t (H)
h
Hold Time, HIGH or LOW
D to SI
n
10.0
10.0
10.0
10.0
10.0
10.0
t (L)
h
t
t
(H)
(L)
Shift In Pulse Width
HIGH or LOW
5.0
5.0
5.0
w
10.0
10.0
10.0
w
ns
t
t
(H)
(L)
Shift Out Pulse Width
HIGH or LOW
7.5
8.5
7.5
w
10.0
10.0
10.0
w
t
t
t
(H)
(L)
(L)
Input Ready Pulse Width,
HIGH
w
w
w
7.5
5.0
8.5
5.0
7.5
5.0
ns
ns
ns
Output Ready Pulse Width,
LOW
Master Reset Pulse Width,
LOW
10.0
32.0
10.0
35.0
10.0
35.0
t
t
Recovery Time, MR to SI
Data Throughput Time
ns
rec
PT
0.9
1.0
1.0
ms
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 413
P
C
X
Temperature Range Family
Special Variations
e
e
e
74F
54F
Commercial
Military
QB
Military grade device with
environmental and burn-in
processing
Device Type
Temperature Range
Package Code
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
e
e
P
D
Plastic DIP
Ceramic DIP
b a
Military ( 55 C to 125 C)
§
§
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N16E
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