74F537SJ [NSC]
IC F/FAST SERIES, DECIMAL DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO20, 0.300 INCH, EIAJ, PLASTIC, SOP-20, Decoder/Driver;
| 型号： | 74F537SJ |
| 厂家： | 
National Semiconductor |
| 描述： | IC F/FAST SERIES, DECIMAL DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO20, 0.300 INCH, EIAJ, PLASTIC, SOP-20, Decoder/Driver 驱动 光电二极管 输出元件 |
| 文件： | 总6页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1995
74F537
1-of-10 Decoder with TRI-STATE Outputs
É
General Description
The ’F537 is one-of-ten decoder/demultiplexer with four ac-
tive HIGH BCD inputs and ten mutually exclusive outputs. A
polarity control input determines whether the outputs are
active LOW or active HIGH. The ’F537 has TRI-STATE out-
puts, and a HIGH signal on the Output Enable (OE) input
forces all outputs to the high impedance state. Two input
enables, active HIGH E and active LOW E , are available
2 1
for demultiplexing data to the selected output in either non-
inverted or inverted form. Input codes greater than BCD
nine cause all outputs to go to the inactive state (i.e., same
polarity as the P input).
Package
Commercial
Number
Package Description
74F537PC
N20A
M20B
M20D
20-Lead (0.300 Wide) Molded Dual-In-Line
×
74F537SC (Note 1)
74F537SJ (Note 1)
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
e
Note 1: Devices also available in 13 reel. Use suffix
×
SCX and SJX.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Assignment for
DIP and SOIC
TL/F/9550–3
TL/F/9550–1
TL/F/9550–5
Unit Loading/Fan Out
74F
Pin Names
Description
U.L.
Input I /I
IH IL
HIGH/LOW
Output I /I
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
A –A
0
Address Inputs
1.0/1.0
1.0/1.0
3
E
E
Enable Input (Active LOW)
Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Polarity Control Input
1
2
1.0/1.0
OE
P
1.0/1.0
b
1.0/1.0
20 mA/ 0.6 mA
3 mA/24 mA (20 mA)
b
O –O
0
TRI-STATE Outputs
150/40 (33.3)
9
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9550
RRD-B30M105/Printed in U. S. A.
Truth Table
Inputs
Outputs
Function
OE
E
1
E
2
A
3
A
A
1
A
0
O
O
O
O
O
O
O
O
O
O
9
2
0
1
2
3
4
5
6
7
8
High Impedance
Disable
H
X
X
X
X
X
X
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
L
H
X
X
L
X
X
X
X
X
X
X
X
Outputs Equal P Input
Active HIGH
Output
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
e
(P
L)
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
X
H
L
L
H
X
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
Active LOW
Output
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
e
(P
H)
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
X
H
L
L
H
X
L
H
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
e
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Z
High Impedance
Logic Diagram
TL/F/9550–4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
Free Air Ambient Temperature
b
a
65 C to 150 C
Storage Temperature
§
§
§
b
a
55 C to 125 C
Ambient Temperature under Bias
§
§
§
b
b
a
a
0 C to 70 C
Junction Temperature under Bias
Plastic
55 C to 175 C
Commercial
§
§
§
§
a
55 C to 150 C
Supply Voltage
Commercial
a a
4.5V to 5.5V
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
74F
Typ
Symbol
Parameter
Units
V
CC
Conditions
Min
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
e b
Output HIGH
Voltage
74F 10% V
2.5
2.4
2.7
2.7
I
I
I
I
1 mA
3 mA
1 mA
3 mA
CC
OH
OH
OH
OH
74F 10% V
CC
V
74F 5% V
74F 5% V
CC
CC
e
V
Output LOW
Voltage
I
24 mA
OL
OL
74F 10% V
0.5
V
Min
Max
Max
Max
0.0
CC
I
I
I
Input HIGH
Current
IH
e
e
74F
5.0
7.0
50
mA
mA
mA
V
V
V
V
2.7V
7.0V
IN
Input HIGH Current
Breakdown Test
BVI
74F
IN
Output HIGH
CEX
e
74F
V
CC
OUT
Leakage Current
e
All Other Pins Grounded
V
ID
Input Leakage
Test
I
ID
1.9 mA
74F
4.75
e
IOD
I
Output Leakage
Circuit Current
V
150 mV
OD
74F
3.75
mA
0.0
All Other Pins Grounded
b
e
0.5V
I
I
I
I
I
I
I
Input LOW Current
0.6
mA
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
0.0V
Max
Max
V
V
V
V
V
V
V
IL
IN
e
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
50
2.7V
0.5V
0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
b
e
e
e
50
b
b
150
500
60
5.25V
ZZ
e
Power Supply Current
Power Supply Current
56
66
HIGH
CCH
CCZ
O
e
44
HIGH Z
O
3
AC Electrical Characteristics
74F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
T
A
, V
CC
Com
e a
Symbol
Parameter
V
Units
CC
e
C
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
t
t
Propagation Delay
6.0
4.0
11.0
7.5
16.0
11.0
6.0
4.0
17.0
12.0
PLH
A
n
to O
n
PHL
ns
ns
ns
t
t
Propagation Delay
to O
5.0
4.0
8.5
6.5
14.5
9.0
5.0
4.0
15.5
10.0
PLH
E
1
PHL
n
t
t
Propagation Delay
to O
6.0
5.0
11.0
10.0
16.0
14.0
6.0
5.0
17.0
15.0
PLH
E
2
PHL
n
t
t
Propagation Delay
P to O
6.0
6.0
11.5
11.0
18.0
16.0
6.0
6.0
20.0
17.0
PLH
PHL
n
t
t
Output Enable Time
OE to O
3.0
5.0
5.5
9.0
10.5
13.0
3.0
5.0
11.5
14.0
PZH
PZL
n
t
t
Output Disable Time
OE to O
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
7.0
8.0
PHZ
PLZ
n
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 537
S
C
X
Temperature Range Family
e
Special Variations
e
Devices shipped in 13 reel
74F
Commercial
X
×
Device Type
Temperature Range
e
a
Commercial (0 C to 70 C)
C
§
§
Package Code
e
e
e
P
S
SJ
Plastic DIP
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
4
Physical Dimensions inches (millimeters)
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
20-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)
×
NS Package Number M20D
5
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
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Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
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(
49) 0-180-530 85 85
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